DE102013105356A1 - Method for operating non-volatile memory device for use in smart-TV system, involves detecting errors generated during programming operation for programming portion of non-volatile multi-bit memory cells in non-volatile memory device - Google Patents

Abstract

The method involves detecting errors generated during a programming operation for programming a portion of non-volatile multi-bit memory cells (MC1-MCM) in non-volatile memory device (100) by reading the non-volatile multi-bit memory cells (MC1- MCM) and a force bit data vector, which is checked during the programming operation in order to identify whether any of the non-volatile multi-containing memory cells invalid data. An independent claim is included for an integrated circuit memory system.

Description

REFERENCE TO PRIORITY APPLICATION

A claim of priority under 35 USC § 119 will be applied to the Korean Patent Application No. 10-2012-0056641 filed on May 29, 2012 with the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.

TERRITORY

This invention relates to memory devices and methods of operating the same, and more particularly to non-volatile memory devices and methods of operating the same.

BACKGROUND

Semiconductor memory devices may be volatile or non-volatile. A nonvolatile semiconductor memory device can obtain data stored therein even when it is turned off. The nonvolatile memory device may be permanent or reprogrammable, depending on the manufacturing technology that is used. The nonvolatile memory device may be used for user data, program and microcode storage in a wide variety of applications in the computer, avionics, telecommunications and consumer electronics industries.

SHORT VERSION

Methods of operating non-volatile memory devices use several aspects of programming operations to assist in post-programming error detection in non-volatile multi-bit memory cells. These error detection operations may include identifying one or more non-volatile multi-bit memory cells in a memory device that have undergone unwanted programming from an erased state to an at least partially programmed state.

According to some embodiments of the invention, errors generated during an operation for programming a first plurality of non-volatile multi-bit memory cells in a nonvolatile memory device may be performed by performing a plurality of read operations to generate error detection data and then decoding the error detection data to identify specific cells which have errors in it, be detected. For example, a programmed first plurality of multibit nonvolatile memory cells and a force-bit data vector modified during the program operation may be read to facilitate error detection. This read information, along with data read from a page buffer associated with the first plurality of multibit nonvolatile memory cells, may then be decoded to identify which of the first plurality of nonvolatile multibit memory cells are erased cells which are unacceptable have high threshold voltages.

To further aid in error detection, the programming operations may include modifying an initial force-bit data vector having equivalent first data values (eg, all "1s") into a modified force-bit data vector having a plurality of of second data values therein, which respectively identify one of the first plurality of non-volatile multi-bit memory cells having undergone at least partial programming during the programming operation. Operations may also be performed to update data in the page buffer in response to successfully programming one or more of the first plurality of non-volatile multi-bit memory cells during the program operation.

According to additional embodiments of the invention, a method of operating a nonvolatile memory device may include detecting errors generated during an operation to program a page of nonvolatile multi-bit memory cells in the nonvolatile memory device by evaluating (e.g., decoding): (i ) Data read from the programmed page of non-volatile multi-bit memory cells, (ii) a force-bit data vector which is modified during the program operation, and (iii) data in a page buffer which is the nonvolatile multi-bit side Memory cells is assigned. This evaluation is performed to identify if any of the multivit non-volatile memory cells in the page are erased cells that have unacceptably high threshold voltages (ie unintentionally "programmed" cells). To assist in these error detection operations, the programming operations may include modifying an initial force-bit data vector having equivalent first data values therein into a modified force-bit data vector having a plurality of second data values therein. These second data values identify a respective plurality of nonvolatile multibit memory cells in the page as at least partial programming during the program operation going through. The programming operations may also include resetting at least some of the data in the page buffer to default values in response to successful programming of one or more of the multibit nonvolatile memory cells in the page during the program operation.

In accordance with still other embodiments of the invention, a method of operating a non-volatile memory device includes changing a first multi-bit data value associated with a first programming state of a first non-volatile multi-bit memory cell in the nonvolatile memory device into a second multi-bit data value representing an erased state or erasure state of the first non-volatile multi-bit memory cell is assigned to. This data value change operation is performed in response to verifying that the first non-volatile multi-bit memory cell was validated in the first programming state during a program operation. Force bit data that has been modified during the program operation is then read to confirm that the second multi-bit data value associated with the first non-volatile multi-bit memory cell reflects a precisely programmed cell. The program operation may also include resetting the first multi-bit data value to the second multi-bit data value in a page buffer. Moreover, the step of reading the modified force bit data may include reading the page buffer, the force bit data modified during the program operation, and a plurality of non-volatile multi-bit memory cells in the nonvolatile memory device, and then using the same read information to identify erased cells in the plurality of non-volatile multi-bit memory cells having unacceptably high threshold voltages. The step of reading the modified force-bit data may be preceded by an operation to load a multibit force-bit vector of equivalent logic values into a force-bit register. In addition, the operation to modify at least a portion of the multi-bit force-bit vector in the force-bit register during the program operation may be performed to identify a plurality of nonvolatile multi-bit memory cells in the nonvolatile memory device that is a random one Have undergone programming using an ISSP programming technique.

According to still further embodiments of the invention, a method of operating a nonvolatile memory device may perform an error detection operation on a row of nonvolatile multi-bit memory cells in the nonvolatile memory device by reading the row of nonvolatile multi-bit memory cells together with reading post-program data from a page buffer and force bit data used during programming of the row of non-volatile multi-bit memory cells. These operations are performed to identify if any of the multivit nonvolatile memory cells in the row are erased cells having unacceptably high threshold voltages. This implementation may be preceded by loading the page buffer with a plurality of pages of data and then programming the line of multibit nonvolatile memory cells with the plurality of pages of data from the page buffer. This programming of the row of non-volatile multi-bit memory cells may include resetting at least some of the data in the page buffer if corresponding programming states of nonvolatile multi-bit memory cells in the row are verified as being accurate. Programming the row of multibit nonvolatile memory cells may also involve modifying bits of a precharged force-bit vector to thereby indicate the performance of ISSP programming operations on respective nonvolatile multi-bit memory cells within the row.

BRIEF DESCRIPTION OF THE FIGURES

The above and other objects and features will become apparent from the following description with reference to the following figures, in which like reference numbers refer, unless otherwise specified, to like parts throughout the several figures, and wherein:

1 FIG. 12 is a block diagram schematically illustrating a nonvolatile memory device according to an embodiment of the inventive concept.

2 is a block diagram which schematically shows a page buffer in 1 illustrated according to an embodiment of the inventive concept.

3 Figure 12 is a diagram illustrating a lower tail data recovery procedure when a cell program operation failed.

4 FIG. 12 is a diagram illustrating data states of page buffer latches in a lower-tail data recovery operation in FIG 3 illustrated.

5 Figure 12 is a diagram illustrating an upper-tail data recovery procedure when a cell-program operation has been performed.

6 FIG. 12 is a diagram illustrating data states of page buffer latches in an upper-tail data recovery operation in FIG 5 illustrated.

7 is a diagram illustrating a data recovery method according to an embodiment of the inventive concept.

8th FIG. 12 is a diagram illustrating data states of page buffer latches in a data recovery operation in FIG 7 illustrated.

9 FIG. 10 is a flowchart schematically illustrating a programming method of a nonvolatile memory device according to an embodiment of the inventive concept.

10 FIG. 10 is a flowchart schematically illustrating a data recovery operation which is described in FIG 9 is described.

11 FIG. 10 is a flowchart schematically illustrating a programming method of a nonvolatile memory device according to an embodiment of the inventive concept.

12 FIG. 12 is a flowchart schematically illustrating a programming method of a nonvolatile memory device according to another embodiment of the inventive concept.

13 Fig. 12 is a block diagram schematically illustrating a page buffer according to another embodiment of the inventive concept.

14 Fig. 10 is a diagram for describing bit line forcing according to an embodiment of the inventive concept.

15 FIG. 12 is a diagram schematically illustrating a two-step verification method of a page buffer in FIG 13 illustrated.

16 is a diagram showing a variation in data of page buffer latches in 13 during a programming operation.

17 12 is a diagram illustrating a variation in data of latches of a page buffer corresponding to a target state in a program operation according to an embodiment of the inventive concept.

18 FIG. 12 is a diagram schematically illustrating a method for restoring data between an erase state and a first program state. FIG.

19 Fig. 3 is a diagram schematically illustrating a method for restoring data between an erase state and a second program state.

20 FIG. 12 is a diagram schematically illustrating a method for restoring data between an erase state and a third program state. FIG.

21 FIG. 12 is a diagram schematically illustrating an upper-bit recovery process in a program operation according to an embodiment of the inventive concept. FIG.

22A and 22B Are flowcharts illustrating a multi-bit programming method of a nonvolatile memory device according to an embodiment of the inventive concept.

23 Fig. 10 is a flowchart illustrating a multi-bit programming method of a nonvolatile memory device according to another embodiment of the inventive concept.

24 FIG. 10 is a flowchart illustrating a multi-bit programming method of a nonvolatile memory device according to still another embodiment of the inventive concept.

25 FIG. 10 is a flowchart illustrating a data recovery operation of a storage system according to an embodiment of the inventive concept. FIG.

26 Fig. 10 is a flowchart illustrating a data recovery operation of a storage system according to another embodiment of the inventive concept.

27 is a flowchart illustrating a data recovery operation of a Storage system illustrated according to yet another embodiment of the inventive concept.

28 Fig. 10 is a flowchart illustrating a data recovery operation of a memory system according to still another embodiment of the inventive concept.

29 a perspective view of a memory block according to the inventive concept is.

30 FIG. 4 is a block diagram schematically illustrating a memory system according to an embodiment of the inventive concept.

31 is a block diagram schematically illustrating a memory card according to an embodiment of the inventive concept.

32 is a block diagram schematically illustrating a moviNAND according to an embodiment of the inventive concept.

33 FIG. 12 is a block diagram schematically illustrating a solid-state drive according to an embodiment of the inventive concept. FIG.

34 is a block diagram schematically illustrating a communication device according to an embodiment of the inventive concept.

35 is a block diagram schematically illustrating a smart TV system according to an embodiment of the inventive concept.

DETAILED DESCRIPTION

Embodiments will be described in detail with reference to the accompanying drawings. However, the inventive concept may be embodied in various different forms, and should not be construed as limited only to the illustrated embodiments. Rather, these embodiments are provided as examples, so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. Accordingly, known methods, elements, and techniques are not described with respect to some of the embodiments of the inventive concept. Unless otherwise noted, like reference numerals refer to like elements throughout the drawings and description, and thus descriptions will not be repeated. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

It will be understood that although the words "first / first / first", "second / second / second", "third / third / third", etc. can be used herein to refer to various elements, components, To describe regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by those words. These words are used only to distinguish one element, component, region, layer, or section from another region, layer, and / or section , Thus, a first element, a first component, a first region, a first layer, or a first section, which may be discussed below, could be used as a second element, a second component, or a second component. a second component, a second region, a second layer or a second section or a second section are referred to, without departing from the teachings of the inventive concept.

Spatially relative terms, such as "below," "below," "below," "below," "above," "above," and the like, may be used herein for ease of description to refer to a feature or relationship of feature (s). to describe other element (s) or feature (s) as illustrated in the figures. It will be understood that the spatial relative terms are provided to capture various orientations of the device in use or operation in addition to the orientation illustrated in the figures. For example, if the device in the figures is turned over, elements described as "below," "below," or "below" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary phrases "below" and "below" may capture both an orientation above and below. The device may be otherwise oriented (rotated 90 degrees or under other orientations) and the spatially relative descriptions used herein may be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as "between" two layers, it may be the only layer between the two layers, or one or more intervening layers may also be present.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting for the inventive concept. As used herein, the singular forms "one" and "the" are intended to encompass the plural forms as well, unless the context clearly indicates otherwise. It will further be understood that the words "pointing to" and / or "having" when used in this specification specify the presence of said features, integers, steps, operations, elements, and / or components but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the wording "and / or" includes any and all combinations of one or more of the listed items. Likewise, the wording "exemplary" is provided to refer to an example or an illustration.

It will be understood that when reference is made to an element or layer as being "connected to," "coupled to," or "adjacent to" another element or layer, it directly relates to , may be coupled to or adjacent to the other element or layer, or intervening elements or layers may be present. In contrast, when referring to an element as being "directly on" "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept belongs. It will be further understood that terms such as those defined in commonly used dictionaries are to be interpreted as having the meaning consistent with their meaning in the context of the relevant scope and / or description herein, and they will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

1 FIG. 10 is a block diagram schematically illustrating a nonvolatile memory device according to an embodiment of the inventive concept. FIG. Referring to 1 can be a non-volatile storage device 100 a memory cell array or memory cell array 110 , an address decoder 120 , an input / output circuit 130 and a control logic 140 exhibit. The nonvolatile storage device 100 For example, it may be a NAND flash memory device. However, it is understood that the non-volatile memory device 100 is not limited to the NAND flash memory device. For example, the inventive concept can be applied to a NOR flash memory device, a resistive random access memory (RRAM) device, a phase change memory (PRAM) device, a magneto-magnetic memory device. Resistive Random Access Memory (MRAM) device, a ferroelectric random access memory (FRAM) device, a spin-transfer torque-read-write memory (STTRAM = Spin Transfer Torque Random Access Memory) and the like can be applied. Furthermore, the nonvolatile memory device can be implemented to have a three-dimensional array structure. A nonvolatile memory device having the three-dimensional array structure can be referred to as a vertical NAND flash memory device. The inventive concept can be applied to a charge trap flash (CTF) memory device having a charge storage layer formed of an insulating film and a thin insulating layer, respectively, and to a flash memory device having a charge storage layer is formed of a conductive floating gate. Below, the inventive concept will be described on the condition that the nonvolatile memory device 100 a NAND flash memory device.

The memory cell array 110 may have a plurality of memory blocks. To facilitate the description, a memory block in 1 be illustrated. The memory block may have strings connected respectively to bit lines BL1 to BLn (where n is a natural number). Herein, each strand may have a string selection transistor SST, memory cells MC1 to MCm (where m is a natural number), and a ground selection transistor GST (= ground selection transistor). In each leg, the string selection transistor SST may be driven by a voltage which is transmitted over a string selection line SSL, and the ground selection transistor GST may be driven by a voltage supplied through a ground selection line GSL (Ground Selection Line) is transmitted. Each of the memory cells MC1 to MCm may store at least one bit of data and be driven by a voltage which is applied through a corresponding one of word lines WL1 to WLm is transmitted. The address decoder 120 may select one of the plurality of memory blocks in response to an address, and may transmit the word lines WL1 to WLm having word line voltages for driving (eg, a program voltage, a pass voltage, an erase voltage, a verify voltage, a read voltage, a read-pass voltage, etc.).

During a programming operation, the input / output circuit 130 temporarily store data input from an external device to load it on a page to be written. During a read operation, the input / output circuit can 130 Read data from a page to read to output to the external device. The input / output circuit 130 may include page buffers PB1 to PBn, which correspond to the bit lines BL1 to BLn, respectively. Each of the page buffers PB1 to PBn may include a plurality of latches for programming and reading operations. In each page buffer, at least one of the plurality of latches may store destination data TD for a program operation, and the destination data TD may be changed into pass pattern data when a program operation of a corresponding memory cell (hereinafter referred to as a cell program operation ) is performed. One of the plurality of latches may store / assemble a recovery reference bit RRB. Herein, the recovery reference bit RRB may be a bit used to support a data recovery operation, and may include information indicating a specific state to be restored (for example, an erase state).

The control logic 140 may be an overall operation of the nonvolatile memory device 100 Taxes. The control logic 140 may decode control signals and commands provided by an external memory controller and may include the address decoder 120 and the input / output circuit 130 control according to a decoded result. The control logic 140 For example, a voltage generating circuit for generating voltages necessary for driving (e.g., programming, reading, erasing, etc.) the address decoder 120 are required to generate the voltages to the word lines WL1 to WLm and the input / output circuit 130 for input / output of page data to be programmed and page data read. During a data recovery operation, the control logic may 140 perform a read operation on programmed memory cells at least once in response to a data recovery command. The control logic 140 may recover target data TD supplied during a program operation using data read according to the read operation and a recovery reference bit RRB. Herein, the data recovery command may be provided from the external memory controller. A conventional nonvolatile memory device may store target data at a separate memory location for a data recovery operation during a program operation. For example, during a program operation, target data may be stored in a page buffer of a nonvolatile memory device or in a buffer of the external memory controller. During a conventional data recovery operation, a program operation may be performed on another physical page using the target data stored therein. The programming operation described above may require a separate memory space for storing destination data for a data recovery operation.

On the other hand, the nonvolatile memory device 100 of the inventive concept recover target data using a read operation and a recovery reference bit RRB during a data recovery operation. That is, the nonvolatile memory device 100 of the inventive concept may not require a separate location for destination data TD for a data recovery operation. Thus, it is possible to have a chip size using the nonvolatile memory device 100 of the inventive concept.

2 is a block diagram schematically showing a page buffer in FIG 1 illustrated according to an embodiment of the inventive concept. Referring to 2 For example, a page buffer PB1 may include a sense latch SL, data latches DL1 to DLk (where k is an integer) (hereinafter referred to as at least a first latch), and an additional latch AL (hereinafter is referred to as a second latch). The sense latch SL may store data indicating whether a memory cell is an on-cell or an off-cell during a program / program verify / Read operation is. For example, during a program verify / read operation, the sense latch SL may store data indicating an on cell, when a threshold voltage of a memory cell is lower than a reference level, and data indicating an off cell when a threshold voltage of a memory cell is higher than the reference level. During a data recovery operation, the sense latch SL store a result of a read operation for recovering target data TD, that is, read data. The data latches DL to DLk may store target data TD indicating a program state in a program operation. Data of the data latches DL1 to DLk can be changed into pass pattern data when a cell program operation is performed. Herein, the pass pattern data may be data corresponding to an erase state of a memory cell.

The additional latch AL may store a recovery reference bit RRB during a program operation. Herein, the recovery reference bit RRB may be information associated with a particular error bit recovery state. The particular state may be a state previously determined by a user. For example, in the case where a user knows that error bits on an erase state are many, the additional latch AL may store a recovery reference bit RRB for restoring an error bit of an erase state. That is, when recovery is required on an erase state error bit during a data recovery operation, the recovery reference bit RRB may be a bit indicating whether target data TD supplied to the page buffer PB1 corresponds to an erase state. However, a user does not have to determine a particular state. The nonvolatile storage device 100 may determine a programming state in which an error bit is generated frequently, and may determine the particular program state as a particular state. A page buffer PB1 may be in 2 be illustrated. However, the remaining page buffers PB2 through PBn may be substantially the same as in FIG 2 be configured to be configured.

A data recovery operation performed on a page buffer PB1 according to the inventive concept may be divided into a first data recovery operation and a second data recovery operation. With the first data recovery operation, when a cell program operation has failed, data stored in the data latches DL1 to DLk can be output as the original destination data. With the second data recovery operation, when a cell program operation is performed, target data TD can be recovered by using a data recovery read operation and a recovery reference bit RRB. The page buffer PB1 of the inventive concept may be configured to restore target data TD using data stored at the data latches DL1 to DLk, a result of a data recovery read operation, and a recovery reference bit RRB , An operation of restoring target data TD will be described more fully later.

3 Figure 12 is a diagram illustrating a lower-tail recovery procedure when a cell-programming operation has failed. Herein, a lower tail can not reach a target state (eg, S2), such as memory cells which are at A and B in FIG 3 are placed. For example, in the case that the memory cell is a "slow" cell, it may not reach a second state S2, although a current program loop reaches a maximum program loop. A memory cell placed at A may have a threshold voltage higher than a read level RD, and a memory cell placed at B may have a threshold voltage lower than the read level RD. Herein, the read level RD may be a level for a data restoration operation. A memory cell placed at A or B does not require a data recovery read operation. The reason may be that data latches DL1 to DLk (refer to FIG 2 ) corresponding to a memory cell placed at A or B store data indicating an error state of a cell program operation. That is, data latches DL1 to DLk (refer to FIG 2 ) corresponding to a memory cell placed at A or B may maintain target data TD corresponding to the second state S2 which has been previously charged. Thus, a memory cell placed at A or B may be judged as a lower-tail error bit, and data stored at the data latches DL1 to DLk may be restored as original target data during a data recovery operation ,

4 FIG. 15 is a diagram illustrating data states of page buffer latches when performing a lower-tail data recovery operation in FIG 3 illustrated. Hereinafter, data states of latches in a lower-tail data recovery operation will be described with reference to FIGS 2 . 3 , and 4 to be discribed. For convenience of description, it is assumed that the target state is a second state S2. When a target state is a second state S2, in a program operation, data latches DL1 to DLk may receive data corresponding to the second state S2, and an additional latch AL may store a value of 0. The data latches DL1 to DLk corresponding to the second state may respectively store data according to whether a cell program operation has been performed or failed. When data of the data latches DL1 to DLk have a pass pattern indicating that a cell program operation has been performed, a lower tail data recovery operation may not be needed. On the other hand, when data of the data latches DL1 to DLk have no pass pattern indicating that a cell program operation is performed, that is, when data of the data latches DL1 to DLk hold data corresponding to the second state S2, a memory cell may placed at A or B are judged to be a lower tail error bit. Thus, data S2 maintained at the latches DL1 to DLk can be restored as the original target data. With the above-described lower-tail data recovery operation, when data of the data latches DL1 to DLk are not a pass pattern indicative of a performed cell program operation, they can be restored as the original target data.

5 FIG. 15 is a diagram illustrating an upper-tail data restoration process when a cell-program operation is performed. FIG. Herein, an upper-tail may indicate a leaked memory cell which is over programmed due to a program disturbance (eg, coupling) or a read disturb. An upper-tail data recovery operation may be divided into a first upper-tail recovery operation (➀) performed during a data-recovery read operation and a second upper-tail data recovery operation (➁) using a read operation and a recovery reference bit RRB, according to a judgment result of an upper-tail error bit. Herein, judgment of an upper tail error bit may be made according to a read operation on a memory cell which has passed the cell program operation. For example, a memory cell placed at C (judged as an on cell according to a result of the read operation) may not be judged as an upper tail error bit. A memory cell placed at D (judged as an off cell) may be judged as an upper tail error bit. A recovery reference bit RRB may be a value associated with upper tail data recovery of a first state S1. "1" may correspond to the first state S1 and "0" may correspond to the second state S2. With the first upper-tail data recovery operation, in the case that a result of the data recovery read operation indicates an on cell (for example, a memory cell placed at C), data corresponding to the first state S1 may be used as destination data TD be restored. With the second upper-tail data recovery operation, in the case where a result of a data recovery read operation indicates an off-cell (for example, a memory cell placed at D), data corresponding to the first state may be used as target data based on a value (for example, "1") of a recovery reference bit RRB.

6 FIG. 15 is a diagram showing data states of page buffer latches in an upper tail recovery operation in FIG 5 illustrated. Hereinafter, data states of latches during an upper-tail data recovery operation will be described with reference to FIGS 2 . 5 and 6 to be discribed. For convenience of description, it is assumed that a target state is a first state S1. When a target state is a first state S1, in a program operation, data latches DL1 to DLk may receive data corresponding to the first state S1, and an additional latch AL may store a value of one. For ease of description, it is assumed that a cell program operation of a memory cell corresponding to the first state S1 is performed. In this case, data of the data latches DL1 to DLk corresponding to the first state S1 may be changed to a pass pattern indicating that a cell program operation has been performed. When a sense latch SL stores data corresponding to an on cell as a result of a data recovery read operation in an upper tail recovery operation of the first state S1, data corresponding to the first state S1 may be used as destination data TD be restored based on read data. However, a memory cell placed at C may be judged not to be an upper-tail error bit. When a sense latch SL stores data corresponding to an off-cell as a result of a data recovery read operation in a top-state restore operation of the first state S1, a memory cell placed at D can be judged. to be an upper-tail error bit of the first state S1, using read data and a recovery reference bit RRB of "1" stored in the additional latch AL, and data S1 corresponding to the first state S1 , can be recovered to destination data TD. Briefly, with the above-described upper-tail data recovery operation, when data of data latches DL1 to DLk are a pass pattern indicating a performed cell program operation, target data TD can be used by using a data recovery read operation and a recovery operation. Reference bit RRB be restored. A lower-tail Data recovery method can be with reference to the 3 and 4 and an upper-tail data recovery method can be described with reference to FIGS 5 and 6 to be discribed. Meanwhile, it is possible to recover target data TD regardless of whether a cell program operation has been performed or failed.

7 FIG. 15 is a diagram illustrating a data recovery method according to an embodiment of the inventive concept. FIG. Referring to 7 For example, a data recovery method may include a combination of a lower tail data recovery method of a second state S2 in FIG 3 and an upper-tail data recovery method of a first state S1 in FIG 5 be. Since a memory cell A / B which is judged to be a lower-tail error bit of the second state S2 is in a state in which a cell program operation is not performed, original destination data obtained at data latches DL1 until DLk are stored as the target data TD is restored. Since a memory cell C, which is an upper tail of the first state S1 and is not judged to be an upper tail error bit, as a result of a data recovery read operation, is an on cell, data corresponding to the one first state S1, to be restored to target data TD. Since a memory cell D, which is an upper tail of the first state S1 and judged to be an upper tail bit, is an off-cell as a result of a data recovery read operation, and a recovery reference bit RRB has a value of "1" indicating restoration of an upper-tail error bit of the first state S1, data corresponding to the first state S1 can be restored to destination data TD.

8th FIG. 15 is a diagram showing data states of page buffer latches in a data recovery operation in FIG 7 illustrated. Referring to the 2 . 7 and 8th For example, data states of latches in a data recovery operation may be obtained from a combination of data states of latches on a second state of S2 in FIG 4 and data states latches on a first state S1 in FIG 6 be formed. As in 8th 1, when data of data latches DL1 to DLk at a second state S2 are not a passing pattern indicative of a performed cell program operation, a memory cell placed at A or B may be judged to be a lower tail. Error bit of the second state S2, and data stored in the data latches DL1 to DLk can be directly restored as the data TD. However, if data of the data latches DL1 to DLk at the first state S1 are a pass pattern indicating a performed cell program operation, and data corresponding to an on cell at a sense latch SL as a result of a read operation for one Data recovery are stored, data S1 corresponding to the first state may be recovered as the destination data TD based on read data. Herein, a memory cell placed at B may not be judged to be an upper-tail error bit. When data of the data latches DL1 to DLk at the first state S1 is a pass pattern indicating a performed cell program operation, and data corresponding to an off cell at a sense latch SL as a result of a read operation for a data Recovery, a memory cell placed at D may be judged to be an upper-tail error bit of the first state S1 based on read data and a recovery reference bit RRB, and data S1 corresponding to the first state S1 can be recovered as target data TD. In short, with the data restoration operation described above, when a cell program operation has failed, original destination data stored in data latches DL1 to DLk can be restored as the destination data TD. When a cell program operation is performed, destination data TD can be recovered by using a data recovery read operation and a recovery reference bit RRB.

9 FIG. 10 is a flowchart schematically illustrating a programming method of a nonvolatile memory device according to an embodiment of the inventive concept. Referring to 9 For example, a program operation may be performed using destination data TD. In operation S110, page buffers PB1 to PBn corresponding to memory cells may be set by a recovery reference bit RRB, respectively. In operation S120, it may be judged whether a data recovery operation is needed. Herein, the data recovery operation may start when a total program operation has failed or when a data recovery command is received from an external device. If a data recovery operation is not needed, a program operation may be terminated. If a data recovery operation is needed, in operation S130 destination data TD may be recovered using data latches DL1 to DLk, a read operation on memory cells, and a recovery reference bit RRB.

10 FIG. 3 is a flowchart schematically illustrating a data Restore operation, which in 9 is illustrated. Referring to 10 For example, in operation S131, it can be judged whether data of data latches DL1 to DLk have a pass pattern indicative of a performed cell program operation. When data of data latches DL1 to DLk have no pass pattern therein, the data latches DL1 to DLk can maintain original target data. The reason may be that a cell programming operation has failed. In operation S132, original target data can be recovered directly from the data latches DL1 to DLk. On the other hand, when data of data latches DL1 to DLk have a pass pattern, that is, when a cell program operation is performed, a data recovery read operation may be performed in operation S133. In operation S134, it can be judged whether the read data is out-of-cell data.

If the read data is not off-cell data but on-cell data, in operation S135, data corresponding to a first state S1 may be restored to target data TD based on a pass pattern of the data latches DL1 to DLk and the read data become. If the read data is out-of-cell data, in operation S136, an upper-tail error bit (eg, D in 7 ) of the first state S1 according to data of the data latches DL1 to DLk, the read data and a recovery reference bit RRB, and data S1 corresponding to the first state S1 can be restored as the target data TD. With the data recovery operation, target data TD can be recovered by using data of the data latches DL1 to DLk, read data, and a recovery reference bit RRB.

11 FIG. 10 is a flowchart schematically illustrating a programming method of a nonvolatile memory device according to an embodiment of the inventive concept. Hereinafter, a programming method of a nonvolatile memory device will be described with reference to the accompanying drawings. In operation S210, target data TD may be loaded onto at least a first latch (eg, data latches DL1 to DLk), and a recovery reference bit RRB may be stored at a second latch (eg, additional latch AL). In operation S220, the control logic 140 an address decoder 120 and an input / output circuit 130 such that the loaded target data TD is programmed into selected memory cells. For example, programming voltages may be applied to word lines connected to the memory cells such that threshold voltages of the memory cells reach programming states corresponding to the target data TD. In operation S230, a program verification operation may be performed to judge whether the memory cells are programmed normally. Herein, the program verification operation may be a read operation performed using a verification level of each memory cell. When a verification operation of each memory cell is performed, data latches DL1 to DLk of a page buffer corresponding to a memory cell may be described with pass pattern data (for example, data indicating a cleared state). Thus, a pass / fail result of a total program verify operation may be judged according to data stored in the data latches DL1 to DLk of each page buffer.

When the program verification operation is performed, in operation 240 the programming operation is determined to have been performed. Thereafter, the process proceeds to operation S250. If the program verify operation has failed, the program operation may be determined to be failed in operation S245. Thereafter, the process proceeds to operation S260. In operation S250, it may be judged whether recovery of the target data TD is needed. A target data recovery operation TD may be performed in response to a data recovery command used for a non-volatile memory device 100 provided by an external device.

As described above, although the program operation is determined to be performed, a lower tail error bit (e.g., A and B in the 3 and 7 ) of a second state S2 exist. The reason may be that an upper-tail error bit (for example, D in the 5 and 7 ) of a first state S1 exists and the programming operation is performed. Thus, it is necessary to recover the upper or lower tail error bit for data reliability improvement.

In exemplary embodiments, a memory system that requires high data reliability may be configured to have a data recovery command for the nonvolatile memory device 100 at any time during a program operation for data reliability. In other exemplary embodiments, a data recovery command may be instantaneous for the non-volatile storage device 100 from an external device according to information associated with a programming error.

When recovery of target data TD is required, target data TD may be recovered using at least one read operation and a recovery reference bit RRB stored at a second latch. Herein, a target data recovery operation corresponding to operation S260 may be performed the same as referring to FIG 1 to 10 is described, and a description thereof is therefore omitted. In operation S280, a copy back program operation may be performed to program the recovered target data TD at a new physical page. After that, the procedure can be ended. When a data recovery operation is needed, an error bit (eg, an upper tail error bit) of a particular state may be recovered using data from data latches DL1 to DLk, at least one read operation, and a recovery reference bit RRB , Target data TD, which is recovered by a data recovery operation, can be used directly for a new program operation. However, the inventive concept is not limited thereto. For example, an error of the restored target data TD may be corrected and the error corrected target data TD may be used for a new program operation.

12 FIG. 10 is a flowchart schematically illustrating a programming method of a nonvolatile memory device according to another embodiment of the inventive concept. FIG. A programming procedure in 12 can be equal to the one in 11 with the exception that S275 and S270 operations are added. In operation S265, restored destination data may be output to an external memory controller. In operation S270, the memory controller may correct an error in the recovered target data. For example, the memory controller may correct an error in the recovered target data using an Error Correction Code (ECC). However, the inventive concept is not limited thereto. An error correction operation may be performed by an ECC circuit operating within a nonvolatile memory device 100 is provided. With a programming method of the inventive concept, it is possible to improve data reliability by correcting an error of restored target data. A page buffer PB1 in 2 may have an additional latch AL for storing a recovery reference bit RRB. The additional latch AL can be used as a latch which provides a different function. For example, the additional latch AL may be used as a forcing bit latch for bit line forcing.

As will be described hereinbelow, a bit line forcing operation may be performed to apply a voltage to a bit line in a program operation using a two-step verification method higher than a bit line programming voltage (for example, a ground voltage). and lower than a bit line inhibition voltage (for example, a power supply voltage). The two-step verification method may be performed to verify a programming state, and may include a pre-verification operation performed using a first voltage level and a main verification operation performed using a second voltage level. The two-step verification method is in the U.S. Patents No. 7692970 and 8068361 and the US Patent Publication No. 2011-0515520 and 2011-0110154 the entirety of which is hereby incorporated by reference herein.

13 Fig. 10 is a block diagram schematically illustrating a page buffer according to another embodiment of the inventive concept. Referring to 13 For example, a page buffer PB1 'may include a sense latch SL, an upper bit latch ML, a lower bit latch LL, and a forcing bit latch FL. Target data TD may comprise an upper bit (or a must significant bit: MSB) and a lower bit (or a least significant bit: LSB). During a program operation, the upper bit MSB may be stored at the upper bit latch ML and a lower bit LSB may be stored at the lower bit latch LL. A bit-line forcing bit BFB may be stored at the forcing bit latch FL. The forcing bit latch FL can also be used as an additional latch which stores a recovery reference bit RRB. The bit-line forcing bit BFB may be used as a recovery reference bit RRB during a data recovery operation. The reason may be that a special relationship exists between the bit-line forcing bit BFB and the recovery reference bit RRB.

Since an erase state does not require a program operation, bit-line forcing may not be necessary. Likewise, the change or likelihood of an upper tail error bit being generated may be high due to a program disturb / read disturb. Thus, data stored at the forcing bit latch FL may be used as a bit-line forcing bit BFB indicating whether the bit-line forcing or as a recovery reference bit RRB for restoring an upper-tail error bit of an erase state. On the other hand, since a program state makes a program operation necessary, bit line forcing may be needed. Likewise, the change or likelihood that an upper tail error bit is generated may become lower compared to the erase state. When a program operation is performed, pass pattern data may be stored at the upper and lower bit latches ML and LL, respectively. Herein, the pass data pattern may be data (for example, "11") corresponding to an erase state. When a cell program operation is performed, target data TD can be recovered by using a data recovery read operation, data of the upper and lower bit latches ML and LL, and data of the forcing bit latch FL. When a cell program operation has failed, data stored in the upper and lower bit latches ML and LL can be directly restored as the original target data. The page buffer PB1 'of the inventive concept may be configured to recover target data TD using a data recovery read operation, data of the upper and lower bit latches ML and LL, and data of the forcing bit latch FL.

14 FIG. 10 is a diagram for describing bit line forcing according to an embodiment of the inventive concept. FIG. Referring to 14 For example, when a program voltage VWL is applied to a word line during a program operation of a memory cell ➀ having a threshold voltage in a first region RA, a bit line programming voltage BLPV (for example, 0 volts) may be applied to a bit line. When the program voltage VWL is applied to the word line during a program operation of a memory cell ➁ having a threshold voltage in a second region RB, a slightly raised bit line forcing voltage BLFV may be applied to a bit line.

When a programming loop is iterated, a memory cell of a region RA can be programmed far from a target state P to an adjacent region RB, and a memory cell of the adjacent region RB can be programmed to the target state P. Herein, it is assumed that the bit line programming voltage BLPV may be 0 volts and a bit line programming inhibition voltage BLIV may be a power supply voltage VDD. The memory cell ➀ in the region RA can be programmed by a difference (VWL) between a word line voltage VWL and a bit line voltage VBL. The memory cell ➁ in the region RB can be programmed by a difference (VWLP - BLFV) between the word line voltage VWL and the bit line voltage VBL. A memory cell ➂ entering the target state P may be a program inhibited cell, but a difference (VWL-VDD) between the word line voltage VWL and the bit line voltage VBL may be applied to the memory cell ➂. Compared to the memory cell ➀ in the area RA, the memory cell in the area RB can be programmed more finely.

A bit-line forcing period may be a period of time in which a bit-line forcing voltage BLFV is applied during a program operation of a memory cell in a region RB adjacent to the target state P. Bit line forcing may begin when a threshold voltage exceeds a predetermined value but is less than a lower limit of a target state. A bit-line forcing bit BFB may indicate whether bit-line forcing is to be performed or not. For example, if a bit-line forcing bit BFB of "0" is stored in a forcing bit latch FL, the bit-line forcing may be performed during a next programing loop. However, if a bit-line forcing bit BFB of "1" is stored in the forcing bit latch FL, bit-line forcing can not be performed during a next programing loop. How through 14 is shown to be ΔISPP> (BLFV - BLPV) and ΔISPP> (BLIV - BLFV).

15 FIG. 15 is a diagram schematically showing a two-step verification method of a page buffer in FIG 13 illustrated. In 15 For example, an erase state E and first through third program states P1, P2, and P3 may be illustrated. In the case where target data TD indicates an erase state E and a memory cell has a threshold voltage corresponding to the erase state E, a bit line inhibit voltage BLIV (eg, a power supply voltage) may be applied to a bit line corresponding to the memory cell in a program operation become. Here, target data TD may be data to be programmed.

In the case where target data TD indicates the first program state P1 and a memory cell has a threshold voltage higher than the erase state E and lower than a first pre-verify level PVR1, a bit line programming voltage BLPV (e.g., a ground voltage ) to a bit line corresponding to the memory cell. Also, in the case where target data TD indicates the first program state P1 and a memory cell indicates a threshold voltage higher than the first one, Verification level PVR1 and lower than a first verification level VR1 has, in a program operation, applied a bit line forcing voltage BLFV (for example, 1 volt) to a bit line corresponding to the memory cell.

A memory cell in the I / O area may reach the first programming state P1 through the EB area or may directly reach the first programming state P1. Until a memory cell reaches the first programming state P1, a bit line voltage may be applied to a higher bit line forcing voltage BLFV from a lower bit line programming voltage BLPV or to a bit line programming inhibit voltage BLIV from the bit line forcing voltage BLFV according to FIG an increase in a programming loop. Or, a bit line voltage may be changed to the bit line programming inhibit voltage BLIV from the bit line programming voltage BLPV according to an increase in a program loop.

In the case that the target data TD indicates the second program state P2 and a memory cell has a threshold voltage higher than the first program state P1 and lower than a second verify level PVR2, a bit line programming voltage BLPV may be applied to a bit line in a program operation Memory cell corresponds to be created. Also, in the case that target data TD indicates the second program state P2 and a memory cell has a threshold voltage higher than the second pre-verify level PVR2 and lower than a second verify level VR2, a bit line forcing voltage may be applied during a program operation BLFV is applied to a bit line corresponding to the memory cell.

In the case where target data TD indicates the second program state P2 and a memory cell has a threshold voltage higher than the third program state P3 and lower than a third pre-verify level PVR3, a bit line programming voltage BLPV may be applied to a bit line in a program operation the memory cell corresponds to be created. Also, in the case where target data TD indicates the third program state P3 and a memory cell has a threshold voltage higher than the third pre-verification level PVR3 and lower than a third verification level VR3, a bit line forcing voltage BLFV in a program operation to a bit line corresponding to the memory cell.

In summary, in a program operation, a bit line programming voltage BLPV may be applied to a bit line at each programming state until a pre-verify operation is performed. After the pre-verification operation is performed, a bit line forcing voltage BLFV may be applied to a bit line until a complete verify operation is performed. When the complete verification operation is performed, a bit line programming inhibit voltage BLIV may be applied to a bit line.

As in 15 1, a memory cell to be programmed with target data TD corresponding to an erase state E, which does not require bit line forcing, and a memory cell having target data TD corresponding to one of the first to third states P1 to P3 need to be programmed To program bit-line forcing may be necessary. The erase state E may be over programmed due to a program disturb or a read disturb as illustrated by a dashed line. As with reference to the 5 and 6 10, a value indicating whether bit-line forcing is being performed may be used as a recovery reference bit RRB for restoring upper-tail data of the erase state E.

A nonvolatile storage device 100 of the inventive concept can perform a data recovery operation by using a bit line forcing bit BFB as a recovery reference bit RRB without an additional latch for storing the recovery reference bit RRB.

16 is a diagram showing a variation in data of page buffer latches in 13 during a programming operation. Below is a variation in data of page buffer latches in 13 in a programming operation with reference to FIGS 13 to 16 to be discribed. Herein, a program operation may be a second page program operation (or an upper bit page program operation). When a second page program operation begins, states of latches ML, LL and FL may be as follows. In the case of one Page buffer, which corresponds to a memory cell whose target state is an erase state E, the upper bit latch ML can store a value of "1", the lower bit latch LL can store a value of "1", and the Forcing Bit-latch FL can store a value of "1". In the case of a page buffer corresponding to a memory cell whose target state is a first program state P1, the upper bit latch ML may store a value of "0", the lower bit latch LL may store a value of "1" and the forcing bit latch FL can store a value of "1". In the case of a page buffer corresponding to a memory cell whose target state is a second program state P2, the upper bit latch ML may store a value of "0", the lower bit latch LL may store a value of "0", and the forcing bit latch FL can store a value of "1". In the case of a page buffer corresponding to a memory cell whose target state is a third programming state P3, the upper bit latch ML may store a value of "1", the lower bit latch LL may store a value of "0", and the forcing bit latch FL can store a value of "1".

After the second page program operation is completed, states of the latches ML, LL, and FL may be as follows. In the case of a page buffer corresponding to a memory cell whose target state is the erase state E or a program state, the upper bit latch ML may maintain a value of "1", the lower bit latch LL may have a value of "1". and the forcing bit latch FL can maintain a value of "1". In the case of a page buffer corresponding to a memory cell whose target state is the first program state P1, data of the upper-bit latch ML may be changed from "0" to "1", the lower-bit latch LL may have a value of " 1 ", and data of the forcing bit latch FL can be changed from" 1 "to" 0 ". Since a program operation for programming a memory cell in the first program state P1 is performed, the upper bit latch ML and the lower bit latch LL can store a data pattern of "11" corresponding to the erase state E. Also, since bit line forcing is performed, the forcing bit latch FL can store a value of "0".

In the case of a page buffer corresponding to a memory cell whose target state is the second program state P2, data of the upper bit latch ML may be changed from "0" to "1", data of the lower bit latch LL may be changed from "0 Can be changed to "1", and data of the forcing bit latch can be changed from "1" to "0". Since a program operation for programming a memory cell into the second program state P2 is performed, the upper-bit latch ML and the lower-bit latch LL can store a data pattern of "11" corresponding to the erase state E. Also, since bit line forcing is performed, the forcing bit latch FL can store a value of "0".

In the case of a page buffer corresponding to a memory cell whose target state is the third program state P3, the upper-bit latch ML can maintain a value of "1", data of the lower-bit latch LL can be changed from "0" to "1" Can be changed, and data of the forcing bit latch FL can be changed from "1" to "0". Since a program operation for programming a memory cell in the third program state P3 is performed, the upper-bit latch ML and the lower-bit latch LL can store a data pattern of "11" corresponding to the erase state E. Also, since bit line forcing is performed, the forcing bit latch FL can store a value of "0".

17 FIG. 15 is a diagram illustrating a variation in data of latches of a page buffer corresponding to a target state in a program operation according to an embodiment of the inventive concept. Referring to 17 For example, an erase state E may correspond to data "11", a first program state P1 data "01", a second program state P2 data "00" and a third program state data "10". However, the inventive concept is not limited to this. When a target state is the erase state E, a variation in data stored in latches ML, LL and FL of a page buffer corresponding to a memory cell will be as follows. The upper bit latch ML and the lower bit latch LL can store "1" regardless of a threshold voltage of a memory cell. Since no bit line forcing is needed, the forcing bit latch FL can store "1".

When a target state is the first program state P1, a variation in data corresponding to latches ML, LL and FL of a page buffer corresponding to a memory cell to be programmed will be as follows. Until a threshold voltage of a memory cell exceeds a first verify level VR1 (i.e., before a first verify operation is performed), the upper bit latch ML may store "0" and the lower bit latch LL may store "1". After a threshold voltage of a memory cell exceeds the first verify level VR1 (i.e., after the first verify operation is performed), the upper bit latch ML and the lower bit latch LL may store "1". That is, after the first verification operation is performed, the upper bit latch ML can store "1" and the lower bit latch LL can store the same pass pattern data as data corresponding to the erase state E.

Until a threshold voltage of a memory cell exceeds a first pre-verify level PVR1 (ie, before a first pre-verify operation is performed), the forcing bit latch FL may store "1". After a threshold voltage of a memory cell exceeds the first pre-verify level PVR1 (ie, after the first pre-verify operation is performed), the forcing bit latch FL may store "0". Herein, if "0" in the forcing bit latch FL stored, a bit line forcing to be performed during a next programming loop. That is, a bit-line forcing voltage BLFV may be applied to a bitline during a next programing loop.

When a target state is the second program state P2, a variation in data corresponding to the latches ML, LL and FL of a page buffer corresponding to a memory cell to be programmed will be as follows. Until a threshold voltage of a memory cell exceeds a second verify level VR2 (i.e., before a second verify operation is performed), the upper bit latch ML and the lower bit latch LL may store "0". After a threshold voltage of a memory cell exceeds the second verify level VR2 (i.e., after the second verify operation is performed), both the upper bit latch ML and the lower bit latch LL can store "1". Until a threshold voltage of a memory cell exceeds a second pre-verify level PVR2 (i.e., before a second pre-verify operation is performed), the forcing bit latch may store "1". After a threshold voltage of a memory cell exceeds the second pre-verify level PVR2 (i.e., after the second pre-verify operation is performed), the forcing bit latch FL may store "0". Herein, when "0" is stored in the forcing bit latch FL, bit line forcing may be performed during a next program loop (i.e., a next ISSP pulse).

When a target state is the third program state P3, a variation in data corresponding to the latches ML, LL and FL of a page buffer corresponding to a memory cell to be programmed will be as follows. Until a threshold voltage of a memory cell exceeds a third verify level VR3 (i.e., before a third verify operation is performed), the upper bit latch ML may store "1" and the lower bit latch LL may store "0". After a threshold voltage of a memory cell exceeds the third verify level VR2 (i.e., after the third verify operation is performed), both the upper bit latch ML and the lower bit latch LL can store "1". Until a threshold voltage of a memory cell exceeds a third pre-verify level PVR3 (i.e., before a third pre-verify operation is performed), the forcing bit latch FL may store "1". After a threshold voltage of a memory cell exceeds the third pre-verify level PVR3 (i.e., after the third pre-verify operation is performed), the forcing bit latch FL may store "0". Herein, if "0" is stored in the forcing bit latch FL, bit line forcing may be performed during a next program loop (i.e., during a next ISPP pulse). As described above, when a verification operation is performed on a target state, data of the upper-bit latch ML and the lower-bit latch LL can be changed into pass-pattern data (for example, "11"). When a pre-verification operation is performed on a target state, data of the forcing bit latch FL may be changed to data (for example, "0") which orders execution of bit line forcing during a next program loop.

18 FIG. 12 is a diagram schematically illustrating a method for restoring data between an erase state and a first program state. FIG. Referring to 18 For example, when a target state is an erase state E, a memory cell Ea may have a threshold voltage lower than a first pre-verify voltage PV1, a memory cell Eb may have a threshold voltage higher than the first pre-verify voltage PV1 and lower than a first verify voltage V1, and a Memory cell Ec may have a threshold voltage higher than the first verify voltage V1.

When a target state is a first program state P1, a memory cell P1a may have a threshold voltage lower than the first pre-verify voltage PV1, a memory cell P1b may have a threshold voltage higher than the first pre-verify voltage PV1 and lower than the first one Verification voltage V1, and a memory cell P1c may have a threshold voltage which is higher than the first Verificationsspannung V1.

Values stored in latches ML, LL, SL and FL associated with each memory cell may be as in the table of FIGS 18 is illustrated. The upper bit latch ML may store an upper bit MSB of a target state, the lower bit latch LL may store a lower bit LSB of the target state, the sense latch SL may store a value obtained by performing a read operation is obtained by using a first read level RD1 for a data recovery operation, and the forcing bit latch FL can store a bit line forcing bit BFB. When a cell program operation is performed, the upper bit latch ML and the lower bit latch LL may be written with logical "1" values. When a result of the read operation indicates an on cell, the sense latch SL may store "1". If a result of the read operation indicates an off cell, the sense latch FL may store "0". The bit-line forcing bit BFB may be "1" if no bit-line forcing and "0" when bit line forcing is performed.

When the target state is the erase state E, the upper and lower bit latches ML and LL assigned to each of the memory cells Ea, Eb and Ec can store "1", the sense latch SL assigned to the memory cell Ea can store "1", the sense latch SL associated with the remaining memory cells Eb and Ec can store "0", and the forcing bit latches FL associated with memory cells Ea, Eb and Ec, can save "1".

When the target state is the first program state P1, the upper-bit latch ML associated with each of memory cells P1a and P1b can store "0", the upper-bit latch ML associated with a memory cell P1c can " 1 ", the lower-bit latches LL associated with each of the memory cells P1a, P1b and P1c may store" 1 ", the sense latch SL associated with the memory cell P1a may store" 1 "(ie Cell), the sense latches SL associated with the remaining memory cells P1b and P1c may store "0", the forcing bit latches FL associated with the memory cell P1a may store "1" and the forcing codes Bit latches FL associated with the memory cells P1 and P1c can store "0".

As shown by dotted rectangles in 18 1, the latches ML, LL and SL associated with the memory cells Eb, Ec and P1c may store the same data. Thus, it is difficult to find a target state by a data recovery read operation using a first read level RD1. In this case, whether a target state is an erase state E or a first program state P1 may be judged according to a value stored at a forcing bit line FL. For example, a value stored in a forcing bit latch FL of each of memory cells Eb and Ec may be "1", and a value stored in a forcing bit latch FL of a memory cell P1c may be "0 " be. Although the latches ML, LL, and SL associated with the memory cells Eb, Ec, and P1c store the same data, whether a target state is an erase state E or a first program state P1 may be exactly restored according to a value that is at a Forcing bit line FL is stored. In 18 For example, the case may be illustrated that a first read level RD1 is lower than a first pre-verify level PV1. However, the inventive concept is not limited thereto. For example, the first read level RD1 may be set to be higher than the first pre-verify level PV1 and lower than a first verify level V1.

19 FIG. 15 is a diagram schematically illustrating a method for restoring data between an erase state and a second program state. FIG. Referring to 19 For example, when a target state is an erase state E, a memory cell Ed may have a threshold voltage lower than a second pre-verify voltage PV2, a memory cell Ee may have a threshold voltage higher than the second pre-verify voltage PV2 and lower than one second verification voltage V2. When a target state is a second program state P2, a memory cell P2a may have a threshold voltage lower than the second read level RD2, a memory cell P2b may have a threshold voltage higher than the second read level RD2 and lower than one second pre-verification voltage PV2, a memory cell P2c may have a threshold voltage higher than the second pre-verify voltage PV2 and lower than a second verify voltage V2, and a memory cell P2d may have a threshold voltage higher than the second verify voltage V2.

Values stored in latches ML, LL, SL and FL associated with each memory cell may be as shown in FIG 19 is illustrated. As shown by dotted rectangles in 19 is illustrated, the latches ML, LL and SL associated with the memory cells Ee and P2d can store the same data. Thus, it is difficult to find a target state by a read operation for data restoration using a second read level RD2. When a value stored at a forcing bit latch FL1 is "1", a target state may become an erase state E. When a value stored at a forcing bit latch FL is "0", a target state may become a second program state P2.

20 FIG. 15 is a diagram schematically illustrating a method for restoring data between an erase state and a third program state. FIG. Referring to 20 For example, when a target state is an erase state E, a memory cell Ef may have a threshold voltage lower than a third pre-verify voltage PV3, a memory cell Eg may have a threshold voltage higher than the third pre-verify voltage PV3 and lower than one third verification voltage V3. When a target state is a third program state P3, a memory cell P3a may have a threshold voltage lower than the third pre-verification voltage PV3, a memory cell P3b may have a threshold voltage higher than the third pre-verification voltage PV3 and lower than a third verification voltage V3, and a memory cell P3c may have a threshold voltage higher than the third verification voltage V3 ,

Values stored at latches ML, LL, SL and FL associated with each memory cell may be as in 20 is illustrated. As in 20 is illustrated by dotted rectangles, the latches ML, LL and SL associated with the memory cells Eg and P3c can store the same data. Thus, it is difficult to find a target state through a data recovery read operation using a third read level RD3. When a value stored in a forcing bit latch is "1", a target state may become an erase state E. When a value stored at a forcing bit latch FL is "0", a target state may become a third program state P3.

In the 18 - 20 For example, cases may be illustrated where a data recovery operation requires three read operations. However, the inventive concept is not limited thereto. Target data can be recovered in various manners by combining data of data latches ML and LL, data of a sense latch SL according to a read operation, and data of a forcing bit latch FL. For example, it is possible to recover an upper bit by a data recovery read operation.

21 FIG. 12 is a diagram schematically illustrating an upper-bit recovery process in a program operation according to an embodiment of the inventive concept. FIG. Referring to 21 For example, an upper-bit recovery method of each of states E, P1, P2, and P3 in a data recovery operation will be as follows. First, an upper-bit recovery method will be described when a target state is an erase state E. When "1" is stored at an upper bit latch ML, a lower bit latch LL, and a forcing bit latch FL, a target state may be judged as the clear state E. " As in 18 1, a state that "1" is stored in the upper bit latch ML, the lower bit latch LL, and the forcing bit latch FL may specify only the clear state E. " In this case, during a program operation, an erase state upper tail error bit E may be recovered from a data state of the ML, LL, and FL latches. The "1" stored at the forcing bit latch FL may be output as an upper bit of the erase state E. "

An upper bit recovery operation, when a target state is a program state P1 / P2 / P3, may be divided into two recovery operations, first RCV and second RCV. In the first recovery operation first RCV, data of the forcing bit latch FL may be changed from "1" to "0" when "0" in the upper bit latch ML of a page buffer, that of a memory cell not undergoing programming has, corresponds. As in 18 1, when "0" is stored in the upper bit latch ML in the first and second program states P1 and P2, data of the forcing bit latch FL may be changed to "0" in the first recovery operation first RCV. Thus, when a target state is the first / second program state P1 / P2, the forcing bit latch FL may eventually store "0". Herein, "0" which is finally stored at the forcing bit latch FL may be output as the upper bit of the first and second program states P1 and P2.

During the second recovery operation second RCV, a read operation may be performed using a third read level RD3. When a memory cell is judged to be an off-cell according to a result of a read operation, data of the forcing bit latch FL may be changed from "0" to "1". As in 18 is illustrated, data of the forcing bit latch FL in the third programming state P3 can be changed to "1". It is assumed that upper-tail error bits of the first and second program states P1 and P2 are hardly generated in the second recovery operation second RCV. With this assumption, "1" which is finally stored in the forcing bit latch FL can be output as an upper bit of the third program state P3. With the data recovery operation described above, it is possible to recover upper bit data using data of data latches ML and LL, data of a forcing bit latch FL, and a read operation. An operation of restoring an upper bit may be made by reference to 21 to be discribed. Similarly, a lower bit can be recovered by data from Latches ML, LL and FL and a read operation.

The 22A and 22B 13 are flowcharts illustrating a multi-bit programming method of the nonvolatile memory device according to an embodiment of the inventive concept. A multi-bit programming method of a nonvolatile memory device will be described with reference to FIGS 1 . 13 . 22A and 22B to be discribed.

In operation S311, an upper bit MSB may be loaded on an upper bit latch ML and a lower bit LSB may be loaded on a lower bit latch LL. At this time, a forcing bit latch FL having a default forcing bit (for example, "1") may be set. Or, a default forcing bit (eg, "1") may be stored at the forcing bit latch FL. Herein, the default forcing bit may be a data indicating that bit-line forcing is not being performed.

In operation S312, a bit line voltage VBL may be determined in accordance with data stored in the upper bit latch ML and the forcing bit latch FL, and a program pulse VWL may be applied to a word line. For example, when data stored at the upper bit latch ML is "0" and data stored at the forcing latch FL is "1", the bit line voltage VBL may be set to a bit line programming voltage BLPV be, d. H. a ground voltage GND. When data stored at the upper-bit latch ML is "0" and data stored at the forcing-bit latch is "1", the bit-line voltage VBL may be put on a bit-line forcing Voltage BLFV are set. When data stored at the upper-bit latch ML is "1", the bit-line voltage VBL may be set to a bit-line inhibition voltage BLIV. H. a power supply voltage VDD. The programming pulse may increase according to an iteration of program loops.

In operation S313, a pre-verification operation may be performed, and it may be judged whether the pre-verification operation is performed. When it is judged that the pre-verification operation is performed, in operation S314, the bit-line forcing bit BFB of the forcing bit latch FL may be changed from "1" to "0". When it is judged that the pre-verification operation has failed, it can be judged in operation S315 whether a main verification operation is performed. When it is judged that the main verification operation is performed, in operation S316, data of the upper and lower bit latches ML and LL may be changed into pass pattern data (for example, "11") which program at a next program loop are inhibited. In operation S317, it may be judged whether a total program operation has been performed.

In the event that the pre-verification operation, the main verification operation or the overall programming operation is judged not to be performed, it can be judged in operation S318 whether a current program loop reaches a maximum program loop. If the current program loop does not reach the maximum program loop, a program loop number may increase in S319 and a level of the program pulse may increase by a predetermined increment (eg, ΔISPP). Thereafter, the process proceeds to operation S312.

In the event that the current program loop reaches the maximum program loop, the program operation may have failed. In operation S320, a data recovery operation may be performed immediately in response to a programming error. Herein, with the data recovery operation S321, a read operation on a memory cell using at least one read level / (for example, RD3 in FIG 21 ), as in 22B is illustrated. The loaded upper and lower bits MSB and LSB may be recovered using read data and a forcing bit stored at the forcing bit latch FL. In operation S322, a data recovery operation may be performed the same as referring to FIG 21 is described. In operation S323, the recovered upper and lower bit data MSB and LSB may be error corrected. The error correction operation may be within a nonvolatile memory device 100 or by an external memory controller. After the data recovery operation is completed, in operation S330, the recovered upper and lower bit data MSB and LSB may be copied back to a new physical page. After that, the programming operation can be ended. With the multi-bit programming method of the inventive concept, loaded data (MSB or LSB) can be restored using a forcing bit indicating whether bit-line forcing is needed and a result of a read operation on a memory cell in response to a programming error become.

A complete programming error may be determined according to a number of program loops. However, the inventive concept is not limited to this. For example, a programming error may be determined according to the number of error bits. A technique for determining programming errors according to the number of error bits is described in U.S.Patent US Patent Publication No. 2011-0051514 , the entirety of which is incorporated herein by reference.

23 FIG. 10 is a flowchart illustrating a multi-bit programming method of a nonvolatile memory device according to another embodiment of the inventive concept. FIG illustrated. A multi-bit programming method of a nonvolatile memory device will be described with reference to FIGS 1 . 13 and 23 to be discribed.

In operation S410, target data TD to be programmed may be loaded into data latches (eg, ML and LL), and a forcing bit latch (e.g., FL) may be set with a forcing bit BFB indicating Whether a bit-line forcing is performed or not. In operation S420, memory cells may be programmed with the loaded data.

Thereafter, an on-cell verification operation may be performed on memory cells. The on-cell verification operation may be performed to verify whether memory cells to be programmed-inhibited are programmed. For example, in operation S430, the on-cell verify operation may be performed to verify if an erase state E is programmed by a program fault. In operation S440, an off-cell verification operation regarding memory cells may be performed. The off-cell verification operation may be performed to verify whether memory cells to be programmed reach a target state corresponding to target data. The on cell verification operation and the off cell verification operation are in U.S. Patent No. 8,050,101 and the U.S. Patent Publication No. 2010-0008149 , the entirety of which is incorporated herein by reference.

Whether a program operation has been performed or failed can be determined according to results of the on-cell verify operation and the off-cell verify operation. For example, if an error bit number as a result of the on-cell verify operation and the off-cell verify operation is over a correctable error bit count, then in operation S450 the program operation may be determined as being programmed-failed. If it is determined that the program operation has failed, a data recovery operation for restoring target data may be performed in operation S460. The data recovery operation may be performed in a manner that is described with reference to FIGS 18 to 20 or with reference to 21 is described. After a data recovery operation is completed, destination data recovered in operation S470 may be copied back to a new physical page. After that, the programming operation can be ended. With the multi-bit programming method of the inventive concept, according to results of the on-cell verification operation and the off-cell verification operation, it can be determined whether a program operation has failed, and a data recovery operation can be performed upon a programming error. As with reference to the 22 and 23 a data recovery operation may be performed in response to a programming error. However, the inventive concept is not limited to this. For example, a data recovery operation may be performed in response to a data recovery command provided from an external device.

24 FIG. 10 is a flowchart illustrating a multi-bit programming method of a nonvolatile memory device according to still another embodiment of the inventive concept. A multi-bit programming method of a nonvolatile memory device will be described with reference to FIGS 1 . 13 . 17 and 24 to be discribed.

In operation S510, target data TD indicative of a target state may be loaded into a page buffer in a program operation. In operation S520, a recovery reference bit RRB for restoring an upper-tail error bit of an erase state E may be stored in a bit-line forcing latch FL. The recovery reference bit RBB may be a bit-line forcing bit BFB indicating whether bit-line forcing is being performed or not.

In operation S530, the target data TD may be programmed into or into a memory cell. A data recovery operation may be performed in response to a data recovery command provided by a memory controller, regardless of whether a program operation has failed. When the data recovery command is received, in operation S540, the loaded target data TD may be recovered using at least one read operation and the recovery reference bit RRB. After the data recovery operation is completed, in operation S550, the recovered target data may be copied back to a new physical page. After that, the programming operation can be ended. With the multi-bit programming method of the inventive concept, target data can be recovered using a recovery reference bit RRB and at least one read operation when a data recovery command is received.

25 FIG. 10 is a flowchart illustrating a data restoration operation of a Storage system illustrated according to an embodiment of the inventive concept. A data recovery operation of a memory system will be described below with reference to FIG 25 to be discribed. Herein, a memory system may include at least one nonvolatile memory device and a memory controller that controls the at least one nonvolatile memory device.

In operation S610, the memory controller may read programmed data from the at least one non-volatile memory device where a program operation is being programmed. In operation S620, the memory controller may correct an error in the read data. In operation S630, the memory controller may judge whether an error of the read data is correctable. If an error of the read data is uncorrectable, the process proceeds to operation S650 in which a data restoration operation for recovering programmed data is performed. Herein, the data recovery operation may be performed in a manner which is described with reference to FIGS 1 to 24 is described. If an error of the read data is correctable, the memory controller may judge in operation S640 if an erroneous bit count is above a predetermined value. If so, the method proceeds to operation S650 to ensure data reliability. If not, the data recovery operation can be terminated. As described above, a data recovery operation may be determined based on an error of read data.

26 FIG. 10 is a flowchart illustrating a data recovery operation of a memory system according to another embodiment of the inventive concept. FIG. A data recovery operation of a memory system will be described below with reference to FIG 26 to be discribed. In operation S710, a memory controller may read programming status information indicating a status of a program operation of at least one nonvolatile memory device. In operation S720, the memory controller may judge whether a data recovery operation is needed based on the read programming status information. For example, if a programming status indicates a complete programming error or a complete programming malfunction, a data recovery operation may be required. In this case, in operation S730, the memory controller may issue a data recovery command to the nonvolatile memory device. In operation S740, the nonvolatile memory device may perform a data recovery operation in response to the data recovery command. The data recovery operation may be performed in a manner that is described with reference to FIGS 1 to 24 is described. As described above, a data recovery operation may be determined using programming status information of a non-volatile storage device.

27 FIG. 10 is a flowchart illustrating a data recovery operation of a memory system of still another embodiment of the inventive concept. FIG. A data recovery operation of a memory system will be described below with reference to FIG 27 to be discribed. A nonvolatile memory device may perform a lower tail data recovery operation using data latches DL1 to DLk (refer to FIG 2 ) carry out. A lower tail may be a section in which a cell program operation has failed as described with reference to FIG 3 is described. In operation S810, the data latches DL1 to DLk may maintain data of a target state when a cell program operation has failed. Also, the nonvolatile memory device may perform an upper tail data recovery operation using a recovery reference bit RRB or at least a data recovery read operation. An upper tail may be a section in which a cell programming operation is performed as described with reference to FIG 5 is described. As with reference to the 5 and 6 11, the nonvolatile memory device may restore target data TD indicative of a target state by using a recovery reference bit RRB and a read operation. A data recovery operation of the inventive concept may perform a restore operation for lower tail / upper tail data.

28 FIG. 10 is a flowchart illustrating a data recovery operation of a memory system according to still another embodiment of the inventive concept. A data recovery operation of a memory system will be described below with reference to FIG 28 to be discribed. In operation S910, a nonvolatile memory device may receive a data recovery command and an address from a memory controller. The address may point to a new page where recovered data is programmed. In operation S920, the nonvolatile memory device may perform a data recovery operation in response to the supplied data recovery command and an address. The Data recovery operation may be performed in a manner that is described with reference to FIGS 1 to 14 is described. As described above, destination data may be restored in accordance with a data restoration command, and recovered data may be programmed at a new page designated by an address.

With the inventive concept, state information (eg, RRB) associated with a specific state causing relatively many error bits can be set / stored in a program operation. In a data recovery operation, target data corresponding to the specific state can be restored by using the state information.

The inventive concept is applicable to a vertical NAND flash memory device.

29 is a perspective view of a memory block according to the inventive concept. Referring to 29 For example, at least one ground select line GSL, a plurality of word lines WL, and at least one string select line SSL may be stacked on a substrate between word line cuts. Herein, the at least one string select line SSL may be separated by a thread select line cut. A plurality of columns may penetrate at least one ground select line GSL, a plurality of word lines WL, and at least one string select line SSL. Herein, at least one ground select line SSL, a plurality of word lines WL, and at least one string select line SSL may be formed to have a substrate shape. Bit lines BL may be connected to an upper surface of the plurality of pillars. The memory block in 29 may have a merged wordline structure. However, the inventive concept is not limited thereto.

30 FIG. 15 is a block diagram schematically illustrating a memory system according to an embodiment of the inventive concept. FIG. Referring to 30 can be a storage system 1000 at least one non-volatile memory device 1100 and a memory controller 1200 exhibit. The nonvolatile storage device 1100 may be configured to perform a data recovery operation which is described with reference to FIGS 1 to 28 is described.

The nonvolatile storage device 1100 can be optionally supplied with a high voltage Vpp from outside. The memory controller 1200 can with the non-volatile memory device 1100 be connected via a plurality of channels. The memory controller 1200 at least one central processing unit (CPU = Central Processing Unit) 1210 , a cache 1220 , an ECC circuit 1230 , a ROM 1240 , a host interface or a host interface 1250 and a memory interface 1260 exhibit. Although in 30 not shown, the memory controller 1200 further comprising a random circuit which randomly arranges data. The storage system 1000 according to one embodiment of the inventive concept is applicable to a Perfect Page New (PPN) memory.

The memory controller 1200 may generate a data restoration command when a program operation of the nonvolatile memory device 1100 failed or if the reliability of a programming operation is needed, and may the data recovery command for the non-volatile memory device 1100 provide.

The memory controller 1200 can the ECC circuit 1230 which is configured for an error of data according to an Error Correction Code (ECC). The ECC circuit 1230 may calculate an error correction code value of data to be programmed in a write operation, correct an error of read data in a read operation based on the error correction code value, and an error of recovered data from the nonvolatile memory device 1100 in a data recovery operation. The memory controller 1200 can the non-volatile storage device 1100 with a program command such that data recovered in a data recovery operation is programmed on a different physical page.

The storage system 1000 can improve data reliability by restoring destination data in a data recovery operation. Likewise, the storage system 1000 reduce a chip size because it does not require a separate memory space for storing target data for a data recovery operation.

31 Fig. 10 is a block diagram schematically illustrating a memory card according to an embodiment of the inventive concept. Referring to 31 can a memory card 2000 at least one flash memory 2100 , a cache device 2200 and a memory controller 2300 to control the flash memory 2100 and the cache device 2200 exhibit.

The flash memory 2100 can be optionally supplied with a high voltage Vpp from outside. The flash memory 2100 may be configured to perform a data recovery operation contained in the 1 to 28 described to perform. The Cache Device 2200 Can be used to temporarily store data during operation of the memory card 2000 be generated to save. The Cache Device 2200 can be implemented using a DRAM or SRAM. The memory controller 2300 can with the flash memory 2100 be connected via a plurality of channels. The memory controller 2300 can be between a host and the flash memory 2100 be connected. The memory controller 2300 can be configured to access the flash memory 2100 in response to a request from the host.

The memory controller 2300 can at least a microprocessor 2310 , a host interface 2320 and a flash interface 2330 exhibit. The microprocessor 2310 can be configured to drive firmware. The host interface 2320 can communicate with the host through a card protocol (such as SD / MMC) for data exchange between the host and the memory card 2000 be coupled or connected.

The memory card 2000 It is applicable to Multimedia Cards (MMCs), Security Digitals (SDs), Mini SDs, Memory Sticks, Smart Media, Trans Flash Cards, and the like.

32 Fig. 10 is a block diagram schematically illustrating a moviNAND according to an embodiment of the inventive concept. Referring to 32 can a moviNAND device 3000 at least one NAND flash memory device 3,100 and a controller 3200 exhibit. The moviNAND device 3000 can support the MMC 4.4 (or referred to as "eMMC") standard.

The NAND flash memory device 3,100 may be a single data rate (SDR) NAND flash memory device or a double data rate (DDR) NAND flash memory device. In example embodiments, the NAND flash memory device 3,100 NAND flash memory chips have. Herein, the NAND flash memory device 3,100 be implemented by stacking the NAND flash memory memory chips on a package (eg, FBGA, fine pitch ball grid array, etc.). Each NAND flash memory memory chip may be configured to perform a data recovery operation included in the 1 to 24 is described performs.

The controller 3200 can with the flash memory device 3,100 be connected via a plurality of channels. The controller 3200 can be at least one controller core 3210 , a host interface 3250 and a NAND interface 3260 exhibit. The controller core 3210 can a total operation of the moviNAND device 3000 Taxes. The host interface 3250 can be configured to have an MMC interface or an MMC interface between the controller 3210 and a host. The NAND interface 3260 can be configured so that it is between the NAND flash memory device 3,100 and the controller 3200 coupled. In exemplary embodiments, the host interface 3250 a parallel interface (for example an MMC interface). In other exemplary embodiments, the host interface 3250 the moviNAND device 3000 a serial interface (for example, UHS-II, UFS, etc.).

The moviNAND device 3000 can receive power supply voltages Vcc and Vccq from the host. Herein, the power supply voltage Vcc (about 3.3 volts) of the NAND flash memory device 3,100 and the NAND interface 3200 while the power supply voltage Vccq (approximately 1.8 volts / 3.3 volts) is provided to the controller 3200 can be made available. In exemplary embodiments, an external high voltage Vpp of the moviNAND device 3000 be supplied.

The moviNAND device 3000 According to one embodiment of the inventive concept, it may be advantageous to store mass data as it may have an improved reading characteristic. The moviNAND device 3000 according to one embodiment of the inventive concept is applicable to small and low-performing mobile products (for example, a Galaxy S, iPhone, etc.).

33 FIG. 10 is a block diagram schematically illustrating a solid-state drive according to an embodiment of the inventive concept. FIG. Referring to 33 can a solid state drive (SSD = Solid State Drive) 4000 a plurality of flash memory device 4100 and an SSD controller 4200 exhibit. The flash memory device 4100 can be optionally supplied with a high voltage Vpp from outside. The flash memory device 4100 may be configured to perform a data recovery operation which is described with reference to FIGS 1 to 28 is described performs. The SSD controller 4200 can with the flash storage devices 4100 be connected via a plurality of channels CH1 to CHi. The SSD controller 4200 can at least one CPU 4210 , a host interface 4220 , a cache 4230 and a flash interface 4240 exhibit.

The SSD 400 According to an embodiment of the inventive concept, a programming operation capable of improving the reliability of data can be performed. A more detailed description of the SSD 4000 is in the U.S. Patent No. 7,802,054 . 8,027,194 and 8,122,193 and the US Patent Publication 2007/0106836 and 2010/0082890 , the entire contents of which are incorporated herein by reference.

34 FIG. 10 is a block diagram schematically illustrating a communication device according to an embodiment of the inventive concept. FIG. Referring to 34 can be a communication device 8000 a communication unit 8100 , a controller 8200 , a storage unit 8300 , a display unit 8400 , a touchscreen unit 8500 and an audio unit 8600 exhibit.

The storage unit 8300 can at least a DRAM 8310 , at least one OneNAND 8320 and at least one moviNAND 8330 exhibit. At least one of the OneNAND 8320 and the moviNAND 8330 can be configured so that they are a storage system 2700 in 27 are the same. A detailed description of typical mobile devices is given in FIGS US Patent Publication No. 2010/0010040 . 2010/0062715 . 2010/00199081 . 2010/0309237 and 2010/0315325 , the entire contents of which are incorporated herein by reference.

35 FIG. 10 is a block diagram schematically illustrating a smart TV system according to an embodiment of the inventive concept. FIG. Referring to 35 has a smart TV system 9000 a smart TV 9110 , a revue 9200 , a set-top box 9300 , a wireless router 9400 , a keyboard 9500 and a mobile phone or smartphone 9600 on. Wireless communication can be between the Smart TV 9100 and the router 9400 be performed. The smart TV 9100 can through the revue 9200 which is an open platform to be connected to the Internet. The smart TV TV 9100 It may allow a viewer to receive cable and satellite transmissions through the set-top box 9300 be transposed to see. The smart TV 9100 can according to the control of the keypad or the keyboard 9500 or the smart phone 9600 operate. The smart TV 9100 can be a storage system 1000 which is in 30 is illustrated.

A memory system or memory device according to the inventive concept may be mounted in various types of housings. Examples of the packages in the memory system or the memory device according to the inventive concept may include a package-on-package (PoP), ball grid arrays (BGAs), chip-scale packages (CSPs), a plastic-leaded chip carrier (PLCC), a plastic Dual Inline Package (PDIP), a die-in-wavelet pack, a die-in-wafer mold, a chip-on-board (COB), a ceramic dual-inline package (CERDIP) , a Plastic Metric Quad Flat Pack (MQFP), a Thin Quad Flat Pack (TQFP), a Small Outline Integrated Circuit (SOIC), a Shrink Small Outline Package (SSOP), a Thin Small Outline Package (TSOP), a system-in-package (SIP), a multi-chip package (MCP), a wafer-fabricated package (WFP) and a wafer-level-processed stack package (WSP).

While the inventive concept has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present invention. Thus, it should be understood that the above embodiments are not limitative but illustrative.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

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Claims (22)

Method for operating a non-volatile memory device ( 100 ), comprising: detecting errors during a program operation for programming a portion of a first plurality of multibit nonvolatile memory cells (MC1-MCm) in the nonvolatile memory device (10); 100 ) by reading the first plurality of multibit nonvolatile memory cells (MC1-MCm) and a force-bit data vector verified during the program operation to identify whether any of the first plurality of non-volatile multibit memory cells Memory cells (MC1-MCm) contain incorrect data. The method of claim 1, wherein detecting errors further comprises reading data from a page buffer (PB1-PBn) associated with the first plurality of multibit nonvolatile memory cells (MC1-MCm) to identify which of the first A plurality of non-volatile multi-bit memory cells (MC1-MCm) are erased cells having substantially high threshold voltages. The method of claim 1, wherein the programming operation comprises verifying an initial force-bit data vector having equivalent data values therein. The method of claim 1, wherein the programming operation comprises verifying an initial force-bit data vector having equivalent first data values therein, and wherein verifying comprises holding the initial force-bit vector or modifying the initial force-bit vector. Vector into a modified force-bit data vector having a plurality of second data values therein identifying respective ones of the first plurality of non-volatile multi-bit memory cells (MC1-MCm) which have undergone at least partial programming during the programming operation , The method of claim 2, wherein the programming operation comprises: verifying an initial force-bit data vector having equivalent first data values therein into a modified force-bit data vector having a plurality of second data values therein, each one of the first plurality of non-volatile multi-bit memory cells (MC1-MCm) which have undergone at least partial programming during the program operation; and updating data in the page buffer (PB1-PBn) in response to successfully programming one or more of the first plurality of multibit nonvolatile memory cells (MC1-MCm) during the program operation. Method for operating a non-volatile memory device ( 100 comprising detecting errors during a program operation to program a selected page of non-volatile multi-bit memory cells (MC1-MCm) in the nonvolatile memory device (10); 100 ) by evaluating: (i) data read from the selected page of non-volatile multi-bit memory cells (MC1-MCm), (ii) a force-bit data vector which is modified during the program operation , and (iii) data in a page buffer (PB1-PBn) associated with the page of multibit nonvolatile memory cells (MC1-MCm) to identify whether any of the multibit nonvolatile memory cells (MC1-MCm) in the selected one Page deleted cells, which have substantially high threshold voltages. The method of claim 6, wherein the programming operation comprises modifying an initial force-bit data vector having equivalent first data values therein into a modified force-bit data vector having therein a plurality of second data values identify respective plurality of non-volatile multi-bit memory cells (MC1-MCm) in the selected page as having undergone at least partial programming during the programming operation. The method of claim 7, wherein the programming operation further comprises resetting at least some of the data in the page buffer (PB1-PBn) to default values in response to successfully programming one or more of the non-volatile multi-bit memory cells (MC1-MCm) in the selected page during the programming operation. Method for operating a non-volatile memory device ( 100 comprising changing a first multi-bit data value corresponding to a first programming state of a first non-volatile multi-bit memory cell in the nonvolatile memory device ( 100 ) is assigned to a second multi-bit data value associated with an erase state of the first non-volatile multi-bit memory cell in response to verifying that the first non-volatile multi-bit memory cell was validly programmed to the first programming state during a program operation; and reading force bit data verified during the program operation to confirm that the second multi-bit data value corresponding to the first non-volatile multi-bit memory cell associated with a precisely programmed cell. The method of claim 9, wherein the program operation comprises resetting the first multi-bit data value to the second multi-bit data value in a page buffer (PB1-PBn). The method of claim 10, wherein the reading comprises reading the page buffer (PB1-PBn), the force-bit data modified during the programming operation, and a plurality of multibit nonvolatile memory cells (MC1-MCm) in the non-volatile memory device ( 100 ) to identify erased cells in the plurality of non-volatile multi-bit memory cells (MC1-MCm) which have unacceptably high threshold voltages. The method of claim 9, wherein reading force bit data modified during the program operation precedes loading of a multibit force bit vector of equivalent logic values into a force bit register. The method of claim 12, further comprising modifying at least a portion of the multi-bit force-bit vector in the force-bit register during the program operation to obtain a plurality of multi-bit nonvolatile memory cells (MC1-MCm) in the nonvolatile memory device. 100 ) who have undergone a desired programming using an ISSP programming technique. Method for operating a non-volatile memory device ( 100 comprising: performing an error detection operation on a row of non-volatile multi-bit memory cells (MC1-MCm) in the non-volatile memory device (FIG. 100 by reading the row of non-volatile multi-bit memory cells (MC1-MCm) along with reading post-program data from a page buffer (PB1-PBn) and force-bit data generated during programming of the row of non-volatile multi-bit memory cells (MC1-MCm) were used to thereby identify whether any of the nonvolatile multi-bit memory cells (MC1-MCm) in the row are erased cells having excessively high threshold voltages. The method of claim 14, wherein said performing is preceded by: loading a plurality of pages of data into the page buffer (PB1-PBn); and programming the row of non-volatile multi-bit memory cells (MC1-MCm) with the plurality of pages of data from the page buffer (PB1-PBn). The method of claim 15, wherein programming the row of non-volatile multi-bit memory cells (MC1-MCm) comprises resetting at least some of the data in the page buffer (PB1-PBn) when corresponding programming states of non-volatile multi-bit memory cells (MC1-MCm) in of the line are verified as being accurate. The method of claim 16, wherein programming the row of non-volatile multi-bit memory cells (MC1-MCm) comprises modifying bits of a preloaded force-bit vector to thereby encode the information of programming operations on respective nonvolatile multi-bit memory cells (MC1-MCm). within the line. The method of claim 16, wherein programming the row of non-volatile multi-bit memory cells (MC1-MCm) comprises modifying bits of a preloaded force-bit vector to thereby increase the performance of ISSP programming operations on respective nonvolatile multi-bit memory cells (MC1-MC). MCm) within the line. Integrated circuit memory system, comprising: at least one non-volatile memory device ( 100 ); and a memory controller ( 1200 . 2300 . 4200 ) which is electrically connected to the at least one non-volatile memory device ( 100 ), the memory controller ( 1200 . 2300 . 4200 ) has a central processing circuit and an ECC circuit therein, wherein the ECC circuit is configured to perform a data recovery operation on data stored in the at least one nonvolatile memory device (10). 100 ) during a programming operation, performed by reading a first plurality of multibit nonvolatile memory cells (MC1-MCm) in the at least one nonvolatile memory device ( 100 ) and a force-bit data vector modified during the program operation to identify whether any of the first plurality of multibit nonvolatile memory cells (MC1-MCm) contains erroneous data. The memory system of claim 19, wherein the data recovery operation comprises reading data from a page buffer (PB1-PBn) associated with the first plurality of multibit nonvolatile memory cells (MC1-MCm) to identify which of the first plurality of memory cells non-volatile multi-bit memory cells (MC1-MCm) are deleted cells which have substantially high threshold voltages. The memory system of claim 19, wherein the programming operation comprises modifying an initial force-bit data vector having equivalent first data values therein into a modified force-bit data vector having a plurality of second data values therein identify respective ones of the first plurality of non-volatile multi-bit memory cells (MC1-MCm) which have undergone at least partial programming during the programming operation. The memory system of claim 20, wherein the programming operation comprises: modifying an initial force-bit data vector having equivalent first data values therein into a modified force-bit data vector having a plurality of second data values therein, each one of the first plurality of non-volatile multi-bit memory cells (MC1-MCm) which have undergone at least partial programming during the program operation; and updating data in the page buffer (PB1-PBn) in response to successfully programming one or more of the first plurality of multibit nonvolatile memory cells (MC1-MCm) during the program operation.

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