DE102012200258A1 - Method for manufacturing three-dimension integrated chip, involves connecting contact surfaces of isolated components with integrated circuit portions of substrate, and removing another substrate from isolated components - Google Patents

Abstract

The method involves providing (14) a substrate (16) i.e. silicon wafer, with multiple integrated circuit portions (18a, 18b), which are arranged at predetermined positions. Multiple isolated components (22a, 22b) are applied (20) on another substrate (24). The substrates are placed such that contact surfaces (K22a, K22b) of the isolated components are aligned with the predetermined positions of the circuit portions. The contact surfaces of the isolated components are connected (28) with the circuit portions. The latter substrate is removed (30) from the isolated components.

Description

Embodiments of the present invention relate to a method of manufacturing a chip.

A chip or a plurality of chips are typically made in parallel on a substrate, such as on a silicon wafer. Here, the substrate z. Processed by doping, for example, to form a plurality of laterally distributed integrated circuit sections or a plurality of laterally distributed integrated circuits thereon. To a chip with multiple integrated circuit sections in several levels, d. H. With three-dimensionally distributed integrated circuit sections, for example, various components or chips, each having one or more integrated circuit sections, can be stacked. These stacked components are then connected together so that the individual, integrated circuit sections are electrically coupled and cooperate as an integrated circuit or as a chip.

In this case, integrated components are typically arranged on an already processed substrate and are connected to the same by means of wafer bonding. This assembly is also called flip-chip mounting. Such a method, in which individual components or chip are applied to a processed substrate individually and adjusted, is described in the patent DE4433845 A1 described. Another method, in which integrated components are applied individually to a target substrate by means of a carrier substrate, is described in the patent DE4433833 A1 explained. In this flip-chip assembly, however, the exact positioning of the individual, integrated component or chip on the processed substrate causes considerable expense and thus high production costs.

The object of the present invention is to provide a method for the cost-effective and reliable production of a chip.

The object of the present invention is achieved by a method for producing a chip according to claim 1.

Embodiments of the present invention provide a method of manufacturing a chip, comprising the step of providing a first substrate having a plurality of integrated circuit portions disposed at predetermined positions and the step of depositing a plurality of singulated devices on a second substrate in that the separated components are each fastened with a main surface on the second substrate, the main surface lying opposite a contacting surface of the separated components. Further, the method includes the step of arranging the first substrate and the second substrate such that the contacting surfaces of the singulated devices are aligned with the predetermined positions of the integrated circuit sections. Furthermore, the method comprises the step of connecting the contacting surfaces of the singulated devices to the integrated circuit sections of the first substrate and the step of removing the second substrate from the singulated devices mounted on the first substrate.

Embodiments of the present invention are based on having a plurality of discrete components, such as chips, microelectronic devices, or devices with microelectromechanical systems, on a first substrate with integrated circuit portions already applied, i. H. on an already processed wafer, at the same time by means of a second substrate, which acts as a temporary carrier, can be arranged or applied. Here, it proves to be advantageous that at the same time a reliable and accurate positioning of all isolated components on the first (target) substrate by the temporary carrier substrate and all components in parallel, z. B. by means of bonding, electrically and mechanically connected to the first substrate. In other words, in this method, the step of positioning the plurality of singulated devices in relation to the positions of the integrated circuit sections of the target substrate is shifted to a preferred intermediate step. This allows a simplification and in particular quality improvement of the manufacturing process and thus an increase in cost efficiency in the production, especially in the production of large quantities.

Further exemplary embodiments of the present invention provide a method for producing a chip, in which the separated components are adjusted or applied to the second substrate by means of previously applied component alignment marks. According to further embodiments, the step of arranging the first and second substrates may be effected by means of likewise previously applied substrate alignment marks. In embodiments in which the arrangement takes place on the basis of component alignment marks or substrate alignment marks, it is advantageous that the precision in the arrangement of the separated components on the second substrate and thus also the precision in the positioning of the isolated Components on the first substrate is further increased.

According to further embodiments, the separated components are subjected to a functional test before being applied and selected on the basis of this, which reduces the rejects in this production method and thus further increases the cost efficiency of the method.

According to further exemplary embodiments, the bonding of the contacting surfaces of the separated components to the integrated circuit sections of the first substrate is effected by so-called bonding, which is based, for example, on the so-called SLID technology (solid liquid interdiffusion, solid-liquid diffusion). In this case, copper and / or selenium are used as the contact means, for example at elevated pressure (greater than 1.5 bar or greater than 5 bar) and / or at elevated temperature (greater than 100 ° C. or greater than 260 ° C.) an electrical and mechanical connection produce. In this case, it is advantageous that at the same time an electrical and mechanical connection of the plurality of previously separated components is produced on the first substrate.

Embodiments of the present invention will be explained in more detail with reference to the accompanying drawings. Show it:

1 a schematic flow diagram of the method for producing a chip according to an embodiment;

2 a schematic representation of a carrier substrate having a plurality of isolated and according to component alignment marks arranged components for illustrating the step of applying according to further embodiments;

3 a schematic sectional view of a device to be connected to a target substrate for illustrating the step of arranging the target substrate and the carrier substrate according to an embodiment; and

4a -C are schematic sectional views of a connection to be made between two components to illustrate the steps of connecting according to an embodiment.

Before the embodiments are explained in more detail below with reference to the figures, it is pointed out that the same elements or method steps are provided with the same reference numerals, so that the description of which can be applied to each other or is interchangeable.

1 shows a method 10 for producing a chip 12 with three-dimensional integrated circuits. In a first step 14 becomes a first substrate 16 providing the target substrate, wherein the first substrate 16 a plurality of integrated circuit sections 18a and 18b has at predetermined positions. These integrated circuit sections 18a and 18b For example, on the surface of the first target substrate 16 may be, for example, active regions of a transistor or complex semiconductor structures which form either directly or in combination an integrated circuit. The next step is the application 20 a variety of isolated components 22a and 22b or chips on a second substrate 24 namely the so-called carrier substrate or handling substrate. This application is carried out so that the isolated components 22a and 22b each with their major surface H _22a and H _22b on the substrate 24 are attached. Here are the isolated components 22a and 22b for example, by means of a readily soluble adhesive on the second substrate 24 be temporarily attached. These main surfaces H _22a and H _22b are each chosen so that these so-called contacting surfaces K _22a and K _22b , over which the components 22a and 22b with the integrated circuit sections 18a and 18b of the target substrate 16 to be contacted, opposite. Here are the isolated components 22a and 22b on the second substrate 24 (temporary carrier substrate) aligned at defined positions, wherein the defined positions of the predetermined positions of the integrated circuit sections 18a and 18b are dependent.

Arranging 26 of the first (target) substrate 16 and the second (carrier) substrate 24 takes place in the subsequent step, so that the contacting surfaces K _22a and K _{22b of} the separated components 22a and 22b with the predetermined positions of the integrated circuit sections 18a and 18b are aligned or opposed to this (see flip-chip mounting). Through this procedure it is possible that each of the isolated components 22a and 22b precise, ie in a narrow Tolleranzbereich of example z. B. +/- 1.5 microns compared to the integrated circuit sections 18a and 18b can be arranged. The next step of the procedure is the joining 28 contacting surfaces K _22a and K _{22b of} the arranged, separated components 22a and 22b with the integrated circuit sections 18a and 18b , The connecting 28 of the components 22a and 22b For example, it can be done with a standard wafer bonding process, so that both a mechanical and an electrically conductive connection between the components 22a and 22b and the integrated circuit sections 18a and 18b will be produced. In the last step 30 will that second temporary substrate 24 , which only for positioning the isolated components 22a and 22b on the first substrate 16 serves, from the isolated and now with the first substrate 16 or the integrated circuit sections 18a and 18b of the first substrate 16 connected components 22a and 22b removed, so this along with the integrated circuit sections 18a and 18b the chip 12 to shape.

According to further embodiments, the method 10 the optional steps of testing and selecting the isolated components 22a and 22b before application 20 on the second substrate 24 exhibit. This will allow only functional components 22a and 22b with the first (target) substrate 16 get connected.

According to further embodiments, the method 10 further steps of generating the components 22a and 22b on a further substrate (not shown) and the singulation of the produced components 22a and 22b exhibit. These components 22a and 22b For example, an integrated circuit, an integrated circuit section, or a micromechanical system (MEM) may be included on the main surface H _22a and H _22b or in a volume of the device 22a or 22b are formed. These two optional steps described will also be prior to application 20 the isolated components 22a and 22b on the second substrate 24 carried out.

2 shows the second substrate 24 with a variety of arranged on this, isolated components, eg. B. the components 22a and 22b , In this embodiment, the substrate 24 a variety of component alignment marks 32a . 32b and 32c whose positions depend on the predetermined positions of the integrated circuit portions (not shown) on the first (target) substrate. The component alignment marks 32a . 32b and 32c identify the positions of the components 22a respectively. 22b and serve the purpose of a simple and quick arrangement of the separated components 22a and 22b on the second substrate 24 to enable. The component alignment marks 32a . 32b and 32c For example, can be square and so the position of the corners of the individual components 22a respectively. 22b signal. Alternatively, these device alignment marks 32a . 32b and 32c also in the form of one on the second substrate 24 applied lattice, according to which the isolated components 22a respectively. 22b should be arranged. To these component alignment marks 32a . 32b and 32c on the second substrate 24 applies, has the method described above 10 that is, the sub-step of marking the second substrate 24 by means of component alignment marks 32a respectively. 32b before arranging the separated components 22a respectively. 22b on the same up.

According to further embodiments, the second substrate 24 also one or more substrate alignment marks 34a and 34b , z. B. in the form of an arrow or a notch on the edge of the second substrate 24 , corresponding to which the lateral and rotor alignment or arrangement of the first and the second substrate takes place in one of the subsequent steps. Accordingly, first substrate (not shown) is preferably, but not necessarily, labeled with such similar substrate alignment marks so that accurate relative positioning of the first substrate over the second substrate 24 based on the applied substrate alignment marks 34a respectively. 34b is possible. Consequently, the in 1 discussed procedures 10 according to further embodiments also the steps of marking the first and / or the second substrate 24 by means of substrate alignment marks 34a and 34b prior to the step of disposing the first and second substrates.

3 shows a schematic sectional view of the first target substrate 16 as well as the one with the first target substrate 16 to connect component 22a , The target substrate 16 and the device 22a be electrically and / or mechanically by means of one or more inter-chip vias 35 connected. Even if typically several inter-chip vias are formed per component, these are subsequently identified by means of the inter-chip vias 35 explained by way of example.

The first substrate 16 , z. As a silicon substrate with a thickness of 600 microns (350 microns to 800 microns), has a dielectric layer 36 into which one of the integrated circuit sections 18a is embedded. On the dielectric layer 36 is a layer stack 38 which is a copper layer 38a and a selenium layer 38b arranged such that the integrated circuit section 18a is touched directly by the copper layer. In other words, the integrated circuit section is 18a over the layer stack 38 electrically contacted, wherein the layer stack 38 directly as a contact means for electrical and mechanical contacting of the device 22a serves.

The integrated component 22a has a comparatively thin substrate 40 , z. B. a 10 micron thick silicon substrate, with a dielectric layer applied thereto 42 (ILD layer, dielectric interlayer) with a thickness of z. B. 5 to 7 microns. On the dielectric layer 42 is a semiconductor area 44 an integrated circuit or a further integrated circuit section, formed. This semiconductor area 44 is through a passivation layer 46 bounded laterally, the semiconductor region 44 over a metal layer 48 , z. B. aluminum layer, is contactable. The semiconductor area 44 and the contacting metal layer 48 are on the first main surface H _{22a of} the device 22a arranged, which is opposite to the contacting surface K _22a . It should be noted at this point that further layers or further semiconductor regions can also be arranged on the first main surface H _22a . The contacting surface K _22a also has a dielectric layer 50 facing the dielectric layer 42 is comparably thin, as well as one on the dielectric layer 50 applied contact layer 52 on. The contact layer 52 which comprises copper, for example, forms together with the layer stack 38 the inter-chip via 35 which has, for example and a lateral dimension of 4 μm × 4 μm.

This contact layer 52 is preferably after arranging the device 22a applied to the contacting surface K _22a on the carrier substrate. Therefore, the method described above according to another embodiment, the step of thinning the isolated components 22a on, which are arranged on the carrier substrate. By thinning the isolated components 22a Planar contacting surfaces K _{22a are formed} with a constant high layer or a constantly thick substrate 40 formed with a layer thickness of about 10 microns (or 5 to 15 microns), which can be opened from the back for contacting purposes. The substrate opened from the back 40 or the contacting surfaces K _22a with the exposed and conductively filled trenches 54 are then metallized for example by means of copper or titanium-tungsten-nitrogen layer, so that the contact layer 52 on the isolated components 22a and 22b is trained.

To the semiconductor area 44 the integrated circuit 22a to contact on the first main surface H _22a via the contacting surface K _22a , is in the device 22a or through the substrate 40 a ditch 54 brought in. In this respect, the component 22a from the back through the trench 54 opened with conductive material 56 is filled, so that is the conductive material 56 between the contact layer 52 and the metal layer 48 extends. To the conductive material 56 opposite the substrate 40 To isolate, there is an insulation layer 58 on the walls of the ditch 54 ,

Since the ditch 54 8: 1, 10: 1 or even 20: 1, for example, has a relatively high aspect ratio (depth to width), which is particularly dependent on the thickness of the substrate 40 is dependent, this is introduced by means of wet or dry etching, but preferably by means of deep trench etching in the same. The conductive material 56 can then, for example, by CVD (chemical vapor deposition) or Electroplating (galvanic deposition) in the trench 54 deposited, wherein the selected filling method of the conductive material 56 itself and the aspect ratio of the trench 54 is dependent. As a conductive material 56 For example, tungsten can be used, which makes it possible to reduce PN transient effects and thus achieve low contact resistances (eg less than 1.0 Ω or 0.5 Ω). Such backside contact is referred to as W-plug or tungsten contact. Alternatively, other materials such. As copper (Cu) or titanium (TiN), as a conductive material 56 used for the backside contact.

As already mentioned above, the electrical contacting of the device takes place 22a with the integrated circuit section 18a over the layer stack 38 and the contact layer 52 that put together the inter-chip via 35 form. In other words, that means that the semiconductor region 44 on the back K _22a with the circuit section 18a will be contacted. It is noted that the layer stack 38 and the contact layer 52 can be laterally interrupted, so per component 22a simultaneously form several mutually isolated, juxtaposed inter-chip vias. An exemplary method for producing such inter-chip vias or the connection between the component 22a and the target substrate 16 or the integrated circuit section 18a of the target substrate 16 is referred to 4a to 4c explained in more detail.

4a shows two components to be connected together 62a and 62b each having a substrate and a titanium-tungsten nitrogen layer disposed thereon. The titanium-tungsten nitrogen layer is partially structured, so that in each case laterally interrupted contacting surfaces are formed. On top of each of these titanium-tungsten-nitrogen layers is a copper layer 64a and 64b and a selenium layer 66a and 66b applied, which serve in combination as a connecting means. The so-called contacting layers, which each have a copper layer 64a respectively. 64b and a selenium layer 66a respectively. 66b are opposite each other and will, as in the following reference 4b and 4c represented, soldered together.

4b shows the contacted contact layers, which are melted under elevated pressure and elevated temperature. As a result, takes place in the region of the copper layer 64a respectively. 64b a copper diffusion while in the area of directly touching selenium layers 66a and 66b a liquefaction of the same takes place. In this solid-liquid diffusion, a connection of the copper and selenium layers takes place 64a and 66a respectively. 64b and 66b , The solid-liquid diffusion is dependent on the respective temperature and pressure range, which is preferably in the range of 200 ° C to 325 ° C and 3 to 5 bar. This temperature range used depends on the materials used of the components to be connected 62a and 62b since the maximum temperature is determined by individual materials or material pairings. For example, temperature range is limited to a maximum of 450 ° C by an aluminum metallization.

As it is in 4c is due to the increased pressure or the elevated temperature in the region of the selenium layers 66a and 66b a connection area area 68 , z. B. formed by a Cu ₃ Sn solder. This connection area area 68 allows after cooling or solidification of the solder, the electrical and / or the mechanical connection of the two components 62a and 62b ,

Referring to 1 is noted that it has no influence on the described manufacturing process, whether the plurality of components 22a and 22b are the same or different or different-sized, or how many components simultaneously from the carrier substrate 24 on the target substrate 16 be transmitted.

Referring to 1 It should be noted that the method includes further steps of applying a plurality of further separated components to a third substrate (corresponding to step 20 ) and arranging the first and third substrates (see step 26 ). After arranging the first and third substrates, the contacting surfaces of the separated further components are connected to components already contacted or fastened on the first substrate (cf. 28 ) and analogous to the method described above 10 becomes the third (carrier) substrate (see step 30 ) away. In this case, it is advantageous that, by means of this method or by repeating the steps, a stack having a plurality of components in multiple levels can be produced, thus resulting in a 3D integrated chip.

These steps may be arbitrarily repeated according to other embodiments, such that a chip having a plurality of devices fabricated in a plurality of planes may become three-dimensional, wherein alignment errors of the stacked devices are reduced or minimized by the described method.

It is further noted that the integrated circuit sections 18a and 18b either in combination with other integrated circuit sections, the z. B. on the components 22a and 22b integrated, or alone can form an integrated circuit. In this respect, the overall functionality of the chip 12 represented by a large integrated circuit, which consists of the integrated circuit sections 18a and 18b as well as from the connected components 22a and 22b composed. Alternatively, it would be possible for any unit to be a tethered component 22a and an integrated circuit section 18a or a component 22b and a circuit section 18b includes, forms its own chip. Thus, for such an embodiment, the method could include a further step of singulating the individual chips fabricated on the first substrate after removing the second, third or nth carrier substrate. For dicing the chips, for example, laser dicing or a comparable technology could be used.

Referring to 3 is further noted that it is because thinning and metallizing the contacting surfaces K _22a is a so-called back-end process, according to other embodiments, however, other back-end processes, such. For example, chemical etching may be added prior to the step of disposing the first and second substrates. The background to this is that during the application of the plurality of isolated components 22a and 22b an oxide can form on the contacting surfaces K _22a and K _22b , which should be removed again for further processing.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• DE 4433845 A1 [0003]
• DE 4433833 A1 [0003]

Claims (14)

Procedure ( 10 ) for producing a chip ( 12 ), with the following steps: Deploy ( 14 ) of a first substrate ( 16 ) comprising a plurality of integrated circuit sections ( 18a . 18b ) which are arranged at predetermined positions; Application ( 20 ) a plurality of isolated components ( 22a . 22b ) on a second substrate ( 24 ), so that the isolated components ( 22a . 22b ) each having a major surface (H _22a , H _22b ) on the second substrate ( 24 ), wherein the main surface (H _22a , H _22b ) of a contacting surface (K _22a , K _22b ) of the separated components ( 22a . 22b ) is opposite; Arrange ( 26 ) of the first substrate ( 16 ) and the second substrate ( 24 ), so that the contacting surfaces (K _22a , K _22b ) of the separated components ( 22a . 22b ) with the predetermined positions of the integrated circuit sections ( 18a . 18b ) are aligned; Connect ( 28 ) of the contacting surfaces (K _22a , K _22b ) of the separated components ( 22a . 22b ) with the integrated circuit sections ( 18a . 18b ) of the first substrate ( 16 ); and remove ( 30 ) of the second substrate ( 24 ) of the isolated components ( 22a . 22b ). Procedure ( 10 ) according to claim 1, wherein the applying step ( 20 ) of the isolated components ( 22a . 22b ) on the second substrate ( 24 ) a substep of marking the second substrate ( 24 ) by means of component alignment marks ( 32a . 32b . 32c ) corresponding to which the isolated components ( 22a . 22b ) on the second substrate ( 24 ), wherein positions of the component alignment marks ( 32a . 32b . 32c ) on the second substrate ( 24 ) from the predetermined positions of the integrated circuit sections ( 18a . 18b ) are dependent. Procedure ( 10 ) according to one of claims 1 to 2, wherein the method ( 10 ) a further step of marking the first substrate ( 16 ) and / or the second substrate ( 24 ) by means of substrate alignment marks ( 34a . 34b ) corresponding to which the first substrate ( 16 ) and the second substrate ( 24 ) to be ordered. Procedure ( 10 ) according to one of claims 1 to 3, the further steps of generating the components ( 22a . 22b ) on a further substrate and the separation of the produced components ( 22a . 22b ) before application ( 20 ) of the isolated components ( 22a . 22b ) on the second substrate ( 24 ) having. Procedure ( 10 ) according to one of claims 1 to 4, wherein the separated components ( 22a . 22b ) before application to the second substrate ( 24 ) are tested and / or selected. Procedure ( 10 ) according to claim 4 or 5, wherein the isolated components ( 22a . 22b ) similar, different or different sized components ( 22a . 22b ), which are an integrated circuit ( 44 ) and / or a micromechanical system, wherein the integrated circuit ( 44 ) and / or the micromechanical system on the main surface (H _22a , H _22b ) of the device ( 22a . 22b ) or in a volume of the device ( 22a . 22b ) are formed. Procedure ( 10 ) according to claim 6, wherein in producing the components ( 22a . 22b ) one or more with conductive material ( 56 ) filled trenches ( 54 ), from the contacting surfaces (K _22a , K _22b ) into the components ( 22a . 22b ) are generated, so that the integrated circuit ( 44 ) and / or the micromechanical system via the contacting surface (K _22a , K _22b ) are electrically contacted. Procedure ( 10 ) according to one of claims 1 to 7, wherein when connecting ( 28 ) of the contacting surfaces (K _22a , K _22b ) of the separated components ( 22a . 22b ) the integrated circuit sections ( 18a . 18b ) with an integrated circuit ( 44 ) and / or with a micromechanical system of one of the isolated components ( 22a . 22b ) are contacted electrically. Procedure ( 10 ) according to one of claims 1 to 8, wherein the step of connecting ( 28 ) of the contacting surfaces (K _22a , K _22b ) has a sub-step of applying a contact agent ( 52 . 38 . 38a . 38b . 64a . 64b . 66a . 66b ) between the contacting surfaces (K _22a , K _22b ) of the separated components ( 22a . 22b ) and the first substrate ( 16 ) to an electrical and / or mechanical connection ( 35 ). Procedure ( 10 ) according to one of claims 1 to 9, wherein the contacting surfaces (K _22a , K _22b ) of the separated components ( 32a . 22b ) Copper ( 52 . 38a . 64a . 64b ) and / or selenium ( 38b . 66a . 66b ) as a means of contact ( 38 . 38a . 38b . 64a . 64b . 66a . 66b ) exhibit. Procedure ( 10 ) according to one of claims 1 to 10, the further steps of thinning the separated components ( 22a . 22b ) on the second substrate ( 24 ) and / or metallizing the contacting surfaces (K _22a , K _22b ) of the separated components ( 22a . 22b ) after application of the separated components ( 22a . 22b ) on the second substrate ( 24 ) having. Procedure ( 10 ) according to one of claims 1 to 11, wherein the step of connecting ( 28 ) of the contacting surfaces (K _22a , K _22b ) by means of a pressure greater than 1.5 bar and / or by means of a temperature greater than 100 ° C is performed. Procedure ( 10 ) according to one of claims 1 to 12, comprising the further steps of applying a plurality of further separated components to a third substrate, arranging the first substrate ( 16 ) and the third substrate, connecting the contacting surfaces of the further separated components with already on the first substrate ( 16 ) contacted components ( 22a . 22b ) and the removal of the third substrate, so that a stack is formed with a plurality of components in several levels. Procedure ( 10 ) according to one of claims 1 to 13, wherein the integrated circuit sections ( 18a . 18b ) together or individually form an integrated circuit.

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