DE102009057020B4 - Growth substrates for inverted metamorphic multijunction solar cells - Google Patents

Abstract

A method for manufacturing a solar cell, wherein the following is provided: providing a semiconductor carrier (50) made of GaAs or Ge with a prepared connection surface which, by implanting a species in the semiconductor carrier (50), creates a defective layer (51) in the Forms semiconductor carrier (50); providing a carrier substrate (40) with a connection surface; connecting the semiconductor carrier (50) and the carrier substrate (40) by a molecular connection of the prepared connection surfaces of the semiconductor carrier (50) and the carrier substrate (40) ) for producing a composite structure (40, 51, 52); non-destructive separation of the majority (52) of the reusable semiconductor carrier (50) from the composite structure (40, 51, 52) leaving a semiconductor growth substrate (51) made of GaAs or Ge on the support substrate (40); depositing a sequence of layers of semiconductor material including one or more metamorphic buffer layers and a metal sheet icht (129) on top of the sequence of layers to form a solar cell on the semiconductor growth substrate (51), one or more metamorphic buffer layers serving to adapt the different lattice constants of the individual layers of semiconductor material; attaching a surrogate substrate (150) on top of the metal layer and the sequence of layers of semiconductor material to form the solar cell, removing the support substrate (40) and the semiconductor growth substrate (51) and leaving behind the sequence of layers of semiconductor material forming the solar cell.

Description

BACKGROUND OF THE INVENTION

Field of the invention

The present invention relates to the field of semiconductor devices and to manufacturing methods and devices such as multi-junction solar cells based on III-V semiconductor compounds including a metamorphic layer. Such devices are also known as inverted metamorphic multijunction solar cells (solar cells with several pn junctions).

Description of related technology

Solar power from photovoltaic cells, also known as solar cells, were predominantly provided by silicon semiconductor technology. In recent years, however, the manufacture of the III-V compound semiconductor multijunction solar cells for space applications has accelerated the development of this technology, not only for use in space but also for use in terrestrial solar power applications. Compared to silicon, III-V compound semiconductor multijunction devices have greater energy conversion efficiencies and generally have greater radiation resistance, although they tend to be more complex to manufacture. Typical III-V compound semiconductor multijunction solar cells have energy efficiencies that exceed 27%, namely when a sun is illuminated, air mass 0 (AMO) exposure, whereas even the most efficient silicon technologies generally only achieve about 18% efficiency under comparable conditions. With a high solar concentration (for example 500X), III-V compound semiconductor multijunction solar cells in terrestrial applications (with AM1, 5D) have energy efficiencies that exceed 37%. The high conversion efficiency of III-V compound semiconductor multijunction solar cells compared to silicon solar cells is based in part on the ability to achieve spectral splitting of the incident radiation through the use of a large number of photovoltaic zones or regions with different ones Bandgap energies, and summation of the current from each of the zones.

Typical III-V compound semiconductor multijunction solar cells are produced on a semiconductor wafer in vertical multijunction structures. The individual solar cells or wafers are then arranged in horizontal arrangements, the individual solar cells being connected to one another in an electrical series circuit. The shape and structure of an array, as well as the number of cells that the array contains, are determined in part by the desired output voltage and current.

In satellite and other space-related applications, the size, mass and cost of a satellite power system depend on the power and energy conversion efficiency of the solar cells used. In other words, the following applies: The size of the “payload” and the availability of on-board services are proportional to the service group delivered. Thus, as “payloads” become more complicated and use more power, the efficiency and mass of the solar cells, which serve as power conversion devices, become increasingly important to the on-board power systems.

Inverted metamorphic solar cell structures as described in by MW Wanlass et al in Lattice Mismatched Approaches for High Performance, III-V-Photovoltaic-Energy Converters (Conference Proceedings of the 31st IEEE Photovoltaic Specialists Conferences, Jan. 3-7, 2005, IEEE Press, 2005 ) represent an important conceptual point of view for the development of future commercial high efficiency solar cells. The structures described in this reference have a number of practical difficulties related to the appropriate selection of materials and manufacturing steps.

Prior to the present inventions described in this application and related applications as noted above, the materials and manufacturing steps are apparently inadequate in the art for producing a commercially hitting and energy efficient inverted metamorphic multijunction solar cell.

From the US 2006/0 185 582 A1 A method for producing a virtual substrate is known which comprises providing a donor substrate comprising a single crystal donor layer of a first material over a carrier substrate, the first material comprising a ternary, quaternary or penternary semiconductor material or a material that is not available in bulk form comprises bonding the donor substrate to a handle substrate and separating the donor substrate from the handle substrate such that a single crystal film of the first material remains bonded to the handle substrate.

From the EP 1 863 099 A2 discloses a method for forming a multijunction solar cell with the following steps: providing a first substrate made up of GaAs or Ge for the epitaxial growth of the semiconductor material, growing a first solar subcell on the first Substrate with a first bandgap, growing a second solar subcell over the first subcell with a second bandgap that is smaller than the first bandgap, and growing an intermediate grade layer over the second solar subcell and growing a third solar subcell over the intermediate gradation layer with a fourth bandgap , which is smaller than the second band gap such that the third solar sub-cell is lattice mismatched with respect to the second solar sub-cell, the grade intermediate layer being made up of InGaAlAs and having a constant third band gap through its entire thickness which is greater than the second band gap, wherein the InGaAlAs grade intermediate layer reaches a transition of the lattice constants from the second sub-cell to the third sub-cell, and a tunnel diode grown over the second solar sub-cell and a buffer layer of InGaAs grown over the tunnel diode prior to the growth of the gradient intermediate layer are provided.

US 2006/0 112 986 A1 discloses a multijunction solar cell which has an active silicon sub-cell, a first non-silicon sub-cell which is bonded to a first side of the active silicon sub-cell, and a second non-silicon Sub-cell bonded to a second side of the active silicon sub-cell.

From the US 2009/0 229 662 A1 a method for forming a multijunction solar cell is known with the following steps: providing a substrate with an angle of 15 ° from the ( 001 ) Level to ( 111 ) A-plane for epitaxial growth of semiconductor material; Forming a first solar sub-cell on the substrate with a first band gap; Forming a second solar sub-cell over the first solar sub-cell with a second band gap that is smaller than the first band gap; Forming an intermediate grade layer over the second subcell, the intermediate grade layer having a third band gap that is greater than the second band gap; and forming a third solar sub-cell over the grade interlayer with a fourth band gap less than the second band gap such that the third sub-cell has a lattice mismatch with respect to the second sub-cell.

SUMMARY OF THE INVENTION

The present invention relates to a method for manufacturing a solar cell having the features of claim 1. Briefly and generally speaking, the present invention provides a method for manufacturing a solar cell, wherein the following is provided: providing a gallium arsenide carrier with a prepared connection or connection Adhesive surface; Providing a support substrate; Joining or gluing the gallium arsenide support and the support substrate to produce a composite or composite structure; Severing the bulk of the gallium arsenide support from the composite structure, leaving a gallium arsenide substrate on the support substrate; and depositing a sequence of layers of semiconductor material that form a solar cell on the gallium arsenide substrate.

According to a further aspect, the invention provides a method for producing a solar cell, the following being provided: providing a germanium carrier with a produced connection or adhesive surface; Providing a support substrate; Connecting or gluing the germanium carrier and the carrier substrate to produce a composite structure; Separating the bulk of the germanium support from the composite structure; Leaving a germanium substrate on the sapphire substrate and depositing a sequence of layers as semiconductor material to form a solar cell on the germanium substrate.

In another aspect, the invention further provides: sequentially creating a new bonding or adhesive surface on the removed bulk portion of the germanium arsenide or germanium carrier to form a new carrier; Providing a new support substrate; Connecting or gluing the new gallium arsenide or germanium carrier and the new carrier substrate to produce a new composite structure; Severing the bulk of the new gallium arsenide or germanium growth substrate on the new support substrate; and depositing a sequence of layers of semiconductor material to form a solar cell on the new gallium arsenide or germanium growth substrate.

According to a further aspect, the present invention further provides: successive application of a second surrogate substrate on top of the sequence of layers of semiconductor material which form the solar cell; and removing the gallium arsenide or germanium growth substrate.

According to a further aspect, the invention provides the following: The deposition of the sequence of layers of semiconductor material to form a solar cell comprises the formation of a first sub-cell on the growth substrate, this having a first semiconductor material with a first band gap and a first lattice constant; Forming or molding a second sub-cell comprising a second semiconductor material having a second band gap and a second lattice constant, the second band gap being smaller than the first band gap and the second lattice constant being larger than the first lattice constant; Forming or molding a lattice constant transition material positioned between the first sub-cell and the second sub-cell, the lattice constant transition material having a lattice constant that gradually changes from the first lattice constant to the second lattice constant.

• Vorsehen eines Galliumarsenid-Trägers mit einer hergestellten oder vorbereiteten Verbindungs- oder Klebeoberfläche; Vorsehen eines Tragsubstrats;
• Verbinden oder Verkleben des Galliumarsenid-Trägers und des Tragsubstrats zur Erzeugung einer Kompositstruktur; Abtrennen der Masse des Galliumarsenid-Trägers von der Kompositstruktur unter Zurücklassung eines Galliumarsenid-Substrats auf dem Tragsubstrat; Ausbilden oder Formen einer ersten Solarsubzelle mit einem ersten Bandabstand bzw. Bandspalt auf dem Galliumarsenid-Substrat; Formen oder Ausbilden einer zweiten Solarzelle, angeordnet über der ersten Solarzelle mit einem zweiten Bandabstand, der kleiner ist als der-ersten Bandabstand; Ausbilden einer gradierten Zwischenschicht,
• angeordnet über der zweiten Subzelle, und zwar mit einem dritten Bandabstand, der größer ist als der zweite Bandabstand; Formen oder Ausbilden einer dritten Solarsubzelle, angeordnet über der gradierten Zwischenschicht mit einem vierten Bandabstand, der kleiner ist als der zweite Bandabstartd und gitterfehlausgerichtet ist bezüglich der zweiten Subzelle; Formen oder Ausbilden einer vierten solaren Subzelle, angeordnet über der dritten Subzelle mit einem fünften Bandabstand, der kleiner ist als der vierte Bandabstand und gitterangepasst ist bezüglich der erwähnten dritten Subzelle.

According to a further aspect of the invention, a method for producing a solar cell is provided, the following being provided:

• Providing a gallium arsenide carrier with a manufactured or prepared bonding or adhesive surface; Providing a support substrate;
• Connecting or gluing the gallium arsenide carrier and the carrier substrate to produce a composite structure; Severing the bulk of the gallium arsenide support from the composite structure, leaving a gallium arsenide substrate on the support substrate; Forming a first solar subcell having a first band gap on the gallium arsenide substrate; Forming or forming a second solar cell disposed over the first solar cell with a second band gap smaller than the first band gap; Forming a graded intermediate layer,
• disposed over the second sub-cell with a third band gap greater than the second band gap; Forming or forming a third solar sub-cell disposed over the graded intermediate layer with a fourth band gap that is smaller than the second band start and is lattice misaligned with respect to the second sub-cell; Forming or formation of a fourth solar sub-cell, arranged above the third sub-cell with a fifth band gap which is smaller than the fourth band gap and is lattice-matched with respect to the mentioned third sub-cell.

Not all of these aspects or features of the present invention need to be implemented in any embodiment.

Figure list

• 1 eine Querschnittsansicht des Tragsubstrats der vorliegenden Erfindung,
• 1B eine Querschnittsansicht eines Trägersubstrats der vorliegenden Erfindung nach der Oberflächenherstellung oder Vorbereitung;
• 1C eine Querschnittsansicht der Kompositstruktur, die sich durch das Verbinden oder Kleben der Trag- und Trägersubstrate ergibt;
• 1D ein Querschnitt der Kompositstruktur der 1C nach Entfernung der Masse des Trägersubstrats;
• 2A eine perspektivische Ansicht einer vielflächigen (polyhedralen; poliedrisch) Darstellung einer Halbleitergitterstruktur, die die Kristallebenen zeigt;
• 2B eine perspektivische Ansicht des GaAs-Kristallgitters, wobei die Position der Gallium- und Arsenatome gezeigt ist;
• 3A eine perspektivische Ansicht der Ebene P des erfindungsgemäßen Substrats, überlagert über das Kristalldiagramm der 2A;
• 3B eine graphische Darstellung der Oberfläche der Ebene des Substrats, das gemäß der Erfindung verwendet wird;
• 4A eine graphische Darstellung, die den Bandabstand von bestimmten oder gewissen Binärmaterialien und ihre Gitterkonstanten darstellt und einen Bereich von Materialien verwendet bei der invertierten metamorphen Multijunction (IMM)-Solarzelle gemäß dem Stand der Technik;
• 4B eine graphische Darstellung, die den Bandabstand bestimmter Binärmaterialien und ihre Gitterkonstanten zeigt und einen Bereich von Materialien verwendet in einer invertierten metamorphen Multijunction (IMM)-Solarzelle gemäß der Erfindung;
• 5 ein Diagramm, welches den Bereich von Bandabständen verschiedener GalnAlAs-Materialien zeigt, und zwar als Funktion der relativen Konzentration von Al, In und Ga;
• 6 eine graphische Darstellung, die die Ga-Mol-Fraktion zeigt, und zwar abhängig von der AL-zu-In-Molfraktion in GalnAIAs-Materialien, die notwendig sind, um einen konstanten 1,6 eV-Bandabstand zu erhalten;
• 7 eine graphische Darstellung, die die Molfraktion abhängig von der Gitterkonstanten darstellt, und zwar in GalnAIAs-Materialien, die notwendig sind, um einen konstanten 1,5 eV-Bandabstand zu erhalten;
• 8 eine Querschnittsansicht der Solarzelle der Erfindung, und zwar nach der Abscheidung der Halbleiterschichten auf dem Wachstumssubstrat;
• 9 eine Querschnittsansicht der Solarzelle der 8 nach der nächsten Folge von Verarbeitungsschritten;
• 10 eine Querschnittsansicht der Solarzelle der 9 nach der nächsten Folge von Verarbeitungsschritten;
• 11 eine Querschnittsansicht der Solarzelle der 10 nach der nächsten Folge von Verarbeitungsschritten;
• 12 eine Querschnittsansicht der Solarzelle der 11 nach dem nächsten Verarbeitungsschritt, in dem Surrogatsubstrat angebracht wird;
• 13A eine Querschnittsansicht der Solarzelle der 12 nach dem nächsten Verarbeitungsschritt, in dem das ursprüngliche Substrat entfernt wird;
• 13B eine weitere Querschnittsansicht der Solarzelle der 13A mit einer Orientierung, die das Surrogatsubstrat unten oder am Boden der Figur darstellt;
• 14 eine außerordentlich vereinfachte Querschnittsansicht der Solarzelle der 13B;
• 15 eine Querschnittsansicht der Solarzelle der 14 nach dem nächsten Verarbeitungsschritt;
• 16 eine Querschnittsansicht der Solarzelle der 1.5 nach dem nächsten Verarbeitungsschritt, in dem die Gitterlinien über der Kontaktschicht geformt werden;
• 17 eine Querschnittsansicht der Solarzelle der 16 nach dem nächsten Verarbeitungsschritt;
• 18A eine Draufsicht auf einen Wafer, in dem vier Solarzellen hergestellt sind;
• 18B eine Draufsicht von unten eines Wafers der 18A;
• 18C eine Draufsicht von oben auf einen Wafer, in dem zwei Solarzellen hergestellt sind;
• 19 eine Querschnittsansicht der Solarzelle der 17 nach dem nächsten Verarbeitungsschritt;
• 20A eine Querschnittsansicht der Solarzelle der 19 nach dem nächsten Verarbeitungsschritt;
• 20B eine Querschnittsansicht der Solarzelle der 20A nach dem nächsten Verarbeitungsschritt;
• 21 eine Draufsicht auf den Wafer der 20B, wobei die Oberflächenansicht des um die Zelle herum geätzten Grabens gezeigt ist;
• 22A eine Querschnittsansicht der Solarzelle der 20B nach dem nächsten Verarbeitungsschritt in einem ersten Ausführungsbeispiel der Erfindung;
• 22 B eine Querschnittsansicht der Solarzelle der 22A nach dem nächsten Verarbeitungsschritt in einem zweiten Ausführungsbeispiel der Erfindung;
• 22C eine Querschnittsansicht der Solarzelle der 22A nach dem nächsten Verarbeitungsschritt in einem dritten Ausführungsbeispiel der vorliegenden Erfindung, in dem ein Abdeckglas angebracht wird;
• 23 eine Querschnittsansicht der Solarzelle der 22C nach dem nächsten Verarbeitungsschritt in einem dritten Ausführungsbeispiel der Erfindung, in dem das Surrogatsubstrat entfernt ist; und
• 24 ist eine graphische Darstellung des Dotierprofils in einer Basis und angrenzenden Emitterschicht in der metamorphen Solarzelle gemäß der Erfindung.

The invention will be better understood and its meaning can be more fully ascertained by reference to the following detailed description together with the accompanying drawings; in the drawing shows:

• 1 a cross-sectional view of the support substrate of the present invention;
• 1B Fig. 3 is a cross-sectional view of a carrier substrate of the present invention after surface fabrication or preparation;
• 1C a cross-sectional view of the composite structure, which results from the joining or gluing of the support and carrier substrates;
• 1D a cross section of the composite structure of the 1C after removal of the mass of the carrier substrate;
• 2A a perspective view of a polyhedral (polyhedral) representation of a semiconductor lattice structure showing the crystal planes;
• 2 B Fig. 3 is a perspective view of the GaAs crystal lattice showing the position of the gallium and arsenic atoms;
• 3A a perspective view of the plane P of the substrate according to the invention, superimposed on the crystal diagram of FIG 2A ;
• 3B a graphical representation of the surface of the plane of the substrate used in accordance with the invention;
• 4A Fig. 3 is a graph showing the band gap of certain or certain binary materials and their lattice constants and a range of materials used in the inverted metamorphic multijunction (IMM) solar cell according to the prior art;
• 4B Figure 12 is a graph showing the bandgap of certain binary materials and their lattice constants and a range of materials used in an inverted metamorphic multijunction (IMM) solar cell according to the invention;
• 5 a diagram showing the range of bandgaps of various GaInAlAs materials as a function of the relative concentration of Al, In and Ga;
• 6th Figure 8 is a graph showing the Ga mole fraction versus the AL to In mole fraction in GalnAIAs materials necessary to obtain a constant 1.6 eV band gap;
• 7th Figure 8 is a graph showing the mole fraction as a function of the lattice constant in GalnAIAs materials necessary to obtain a constant 1.5 eV band gap;
• 8th Fig. 3 is a cross-sectional view of the solar cell of the invention after the semiconductor layers have been deposited on the growth substrate;
• 9 a cross-sectional view of the solar cell of FIG 8th after the next sequence of processing steps;
• 10 a cross-sectional view of the solar cell of FIG 9 after the next sequence of processing steps;
• 11 a cross-sectional view of the solar cell of FIG 10 after the next sequence of processing steps;
• 12th a cross-sectional view of the solar cell of FIG 11 after the next processing step, in which the surrogate substrate is applied;
• 13A a cross-sectional view of the solar cell of FIG 12th after the next processing step in which the original substrate is removed;
• 13B a further cross-sectional view of the solar cell of FIG 13A with an orientation representing the surrogate substrate at the bottom or bottom of the figure;
• 14th an extremely simplified cross-sectional view of the solar cell of FIG 13B ;
• 15th a cross-sectional view of the solar cell of FIG 14th after the next processing step;
• 16 a cross-sectional view of the solar cell of FIG 1 .5 after the next processing step in which the grid lines are formed over the contact layer;
• 17th a cross-sectional view of the solar cell of FIG 16 after the next processing step;
• 18A a plan view of a wafer in which four solar cells are manufactured;
• 18B a bottom plan view of a wafer of FIG 18A ;
• 18C a top plan view of a wafer in which two solar cells are fabricated;
• 19th a cross-sectional view of the solar cell of FIG 17th after the next processing step;
• 20A a cross-sectional view of the solar cell of FIG 19th after the next processing step;
• 20B a cross-sectional view of the solar cell of FIG 20A after the next processing step;
• 21 a top view of the wafer of the 20B showing the surface view of the trench etched around the cell;
• 22A a cross-sectional view of the solar cell of FIG 20B after the next processing step in a first embodiment of the invention;
• 22 B a cross-sectional view of the solar cell of FIG 22A after the next processing step in a second embodiment of the invention;
• 22C a cross-sectional view of the solar cell of FIG 22A after the next processing step in a third embodiment of the present invention in which a cover glass is attached;
• 23 a cross-sectional view of the solar cell of FIG 22C after the next processing step in a third embodiment of the invention, in which the surrogate substrate is removed; and
• 24 Figure 13 is a graph of the doping profile in a base and adjacent emitter layer in the metamorphic solar cell according to the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Details of the present invention will now be described, including exemplary aspects and embodiments thereof. With reference to the drawings and the following description, it should be noted that the same reference numbers are used to designate the same or functionally similar elements, and the description is intended to describe key features of exemplary embodiments in an extremely simplified schematic manner. In addition, it should be noted that the drawings do not show every feature of the actual embodiment, nor do they show the relative dimensions of the elements shown, which are not shown to scale.

The basic concept of manufacturing an inverted metamorphic multijunction (IMM) solar cell is to grow the subcells of the solar cell on a substrate in a “reversed” sequence. That is, the high bandgap subcells (ie, the subcell with bandgaps in the range of 1.8 to 2.1 eV) that are normally “on top” of the subcells and face solar radiation become epitaxial on a semiconductor growth substrate, such as for example GaAs or Ge, and these subcells are therefore lattice-matched with respect to this substrate. One or more of the middle lower, lower bandgap subcells (i.e., the cells with bandgaps in the 1.2 to 1.8 eV range) can then be grown on the high bandgap subcells.

At least one lower sub-cell is formed over the middle or middle sub-cell such that the at least one lower sub-cell is substantially lattice-matched with respect to the growth substrate and such that at least one lower sub-cell has a third lower band gap (ie a band gap in the range from 0.7 to 1.2 eV). A surrogate substrate or a support substrate is then attached or provided over the "floor" or the substantially lattice-misaligned lower sub-cell, and the growth semiconductor substrate is subsequently removed. (The growth substrate can then be reused for the growth of a second and subsequent solar cells).

The lattice constants and electrical properties of the layers of the semiconductor structure are preferably controlled by specifying or specifying suitable reactor growth temperatures and times and by using appropriate chemical compositions and dopants. The use of a vapor deposition method such as organometallic vapor phase epitaxy (OMVPE = Organo Metallic Vapor Phase Epitaxy), metal organic chemical vapor deposition (MOCVD = Metal Organic Chemical Vapor Deposition), molecular beam epitaxy (MBE = Molecular Beam Epitaxy) or other vapor deposition processes for the reverse growth, it can allow the layers of the monolithic semiconductor structure that make up the cell to be grown to the required thickness, elemental composition, dopant concentration.

A variety of different features of the inverted metamorphic multijunction solar cells are disclosed in the related applications mentioned above. The present invention is directed to an alternative growth and processing technology for the epitaxial fabrication of semiconductor solar cell layers in a multijunction solar cell, and more particularly, the invention is directed to an inverted metamorphic multijunction solar cell. In the preferred of the embodiments to be described, the epitaxial layers of the IMM solar cell are grown on a relatively thin semiconductor structure consisting of a GaAs or Ge growth template (or any other suitable material) attached to a sapphire or sapphire / spinel substrate or carrier is. The sapphire / spinel substrate can be designed or specified and selected so that it has a coefficient of thermal expansion (CTE) that is matched to that of the relative III / V compounds such as GaAs, GalnPa, etc. , these compounds being used in solar cell production.

According to the embodiments described here, the thin gallium arsenide growth template is formed by joining or gluing a gallium arsenide wafer to a sapphire substrate and removing the bulk of the gallium arsenide wafer, which leaves a thin layer of gallium arsenide on the sapphire substrate. The bulk of the gallium arsenide carrier is separated in such a way that it is not destroyed and can be reused to form additional solar cells on other sapphire substrates. Reusing the gallium arsenide carriers in this manner to form additional solar cells significantly reduces the unit cost of gallium arsenide based solar cells.

The IMM cell structure is grown on the above-mentioned growth template by MOCVD or an equivalent growth technology. After the growth, the structure is processed. During processing, release technology is used to remove the sapphire or sapphire / spinel substrate. The sapphire or sapphire / spinel substrate can be reused by attaching another GaAs, Ge (or other) substrate to form an additional solar cell.

The sapphire (or sapphire / spinel) substrate can be released by wet etching or by a layer release process. The wet etch would etch a layer laterally, relieving stress on the growth substrate and the laser recycling process would melt a layer and achieve the same type of release of the growth substrate.

The value of the proposed method is that it eliminates the need to grind and etch the growth template. The main part of the growth template, i.e. the sapphire / spinel substrate or carrier, is now reusable. So much less GaAs or Ge material is required, just enough of a layer to provide a growth template.

A second advantage of this possible solution is that different lattice constants can now be used instead of just GaAs or Ge. If a smaller lattice constant than GaAs (or Ge) can be used, then an upper sub-cell with a higher band gap can now be built into the solar cell, compared to using a GalnP ₂ sub-cell (with a band gap of approximately 1.90 eV) used in currently available IMM solar cell structures.

The 1A-1D are cross-sectional views of a sapphire substrate 40 and a gallium arsenide Carrier 50 during different steps of joining or gluing the carrier 50 with the substrate, the removal of a mass of the carrier 50 after joining or gluing and the formation of a solar cell on the remaining gallium arsenide layer 51 connected to the sapphire substrate 40 . 1A shows the sapphire substrate 40 . 1B shows the gallium arsenide support 50 . The carrier 50 includes the thin gallium arsenide layer 51 adjacent to a mass zone or mass region 52 made of gallium arsenide.

According to one embodiment, the gallium arsenide layer is 51 formed by implanting a species or species, such as hydrogen ions and / or noble gases, into the gallium arsenide carrier 50 to form a defective layer in the gallium arsenide carrier. Any known method of implanting the species, such as hydrogen ions and / or noble gases, into the semiconductor wafer can be used. For example, the gallium arsenide layer 51 in the carrier 50 can be formed in accordance with any of the species or species implantation techniques disclosed in US Pat US 7 288 430 B2 , US 7 235 462 B2 , US 6,946,317 B2 and US 6,794,276 B2 each of these patents is assigned to SOI Tec Silicon on Insulator Technologies and the contents of these patents are incorporated herein by reference in their entirety. The dose and / or the energy of the implanted species or species can be adjusted in such a way that the peak concentration of the implanted species at a certain depth of the wearer 50 is formed, creating the gallium arsenide layer 51 is weakened as a result of ion implantation at or near its depth. The mass zone 52 of the gallium arsenide carrier 50 is not weakened during the implantation process.

In one embodiment, the gallium arsenide carrier 50 a prepared bonding surface that can be roughened prior to bonding to the sapphire substrate 40 , as shown in the exploded view 1B is illustrated. The manufactured or prepared connection surface of the carrier 50 can be roughened using any suitable chemical compound or by a mechanical roughening process. The roughening of the surface of the carrier 50 improves the connection characteristics of the wearer 50 .

1C shows the gallium arsenide support 50 and the sapphire substrate 40 after they are connected to each other. According to one embodiment, the produced connection surface of the gallium arsenide carrier is directly molecularly with a surface of the sapphire substrate 40 connected, for example at elevated temperature and pressure. A thin tie layer between the layer 51 and the sapphire substrate 40 is not shown in the figures in order to simplify the drawings. According to one embodiment, the weakened layer is 51 made of gallium arsenide, formed by implanting the species or species such as hydrogen ions and / or noble gases into the carrier 50 , with the sapphire substrate 40 connected. The crowd 52 of the gallium arsenide carrier 50 is then removed from the composite structure, making the thin layer 51 made of gallium arsenide on the sapphire substrate 40 leaves behind.

In one embodiment, the mass 52 of the gallium arsenide carrier 50 from the sapphire substrate 40 separated by annealing the carrier 50 in a hot environment such as an oven or any rapid thermal tempering device. The effect of tempering temperature and time weakens the wearer 50 on the gallium arsenide layer 50 further, introduced by atomic implantation, which leads to separation. Because of the separation along this region during or after tempering, the thin layer remains 51 made of gallium arsenide with the sapphire substrate, as in 1D shown connected. The separated mass part 52 of the wearer 50 will not be destroyed and can be used again.

According to one embodiment, the thin layer has gallium arsenide 51 connected to the sapphire substrate 40 , a thickness of about 5 microns and the bulk 52 of the wearer 50 , separated from the composite or composite structure, has a thickness of approximately 395 Micrometer. The thin layer 51 made of gallium arsenide bonded to the sapphire substrate 40 , acts as a substrate on which a solar cell can be formed. In one embodiment, the gallium arsenide layer is 51 prepared or smoothed before a solar cell on the layer 51 is formed. The smoothing or surface preparation can be carried out using any suitable technique such as chemical mechanical polishing, etching by a gas cluster, ion beam or etching with reactive ions, HCl smoothing, etc. In the following, the thin GaAs -Layer 51 on the sapphire carrier 40 simply referred to as the "substrate".

As mentioned above, the mass will 52 of the gallium arsenide carrier 50 from the sapphire 40 separated and can be used again. In one embodiment, the mass 52 of the gallium arsenide carrier 50 reused to form a new solar cell on a new substrate (not shown) as described above. That is, a new connection surface is created on the severed bulk part 52 made of gallium arsenide carrier 50 made to form a new gallium arsenide carrier. The new gallium arsenide carrier is bonded to a new sapphire substrate to create a new composite structure or composite structure. The bulk of the new gallium arsenide carrier is separated from the new composite structure - as described above - leaving a new gallium arsenide substrate on top of the new sapphire substrate. A new sequence of layers of semiconductor material can then be deposited on the new gallium arsenide substrate to form a new solar cell.

The gallium arsenide carrier 50 (and also the template's gallium arsenide growth layer 51 ) is preferably a trimmed substrate, as referenced with reference to FIG 2A - 3B is described below. 2A Figure 13 is a perspective view of a multilayer (polyhedral) representation of a semiconductor lattice structure showing crystal planes. The Miller indices are used to identify the planes and the crystal structure is truncated in the figure by a. Cube represented by the ( 001 ) Level above. In the case of a GaAs compound semiconductor, which is the material of interest of the present invention, the crystal structure is known as a zinc mixture structure and is shown in FIG 2 B shown what a combination of two inside each other-. end face-centered cubic sublattices (sub.lattices). The lattice constant (i.e. the distance between the arsenic atoms in the crystal) is 0.565 nm.

2 B Figure 13 is a perspective view of the GaAs crystal lattice showing the position of the gallium arsenic atoms with the corresponding Miller indices identifying the lattice planes.

3A FIG. 13 is a perspective view of the plane P of the substrate surface used in the present invention superimposed on the crystal diagram of FIG 2A . The plane P can be seen pivoted from a point on the ( 001 ) Plane (in this illustration the rear corner of the top surface of the polyhedron) in the direction of the ( 111 ) Level or, more precisely, the ( 111 ) A-plane, where the letter "A" refers to the plane formed by the sublattice of the arsenic atoms. The pivot angle according to the present invention defines the angle of separation of the substrate defined from the ( 001 ) Plane through plane P, and is at least 6 ° and preferably approximately 15 °.

Although the present invention ideally includes a section (offcut) in the ( 111 ) A provides direction, it may happen that during the production and manufacture of the various wafer batches the alignment or cutting process cannot be carried out as precisely or exactly as the present invention specifies, and so the resulting plane P can be somewhat in Direction of neighboring ( 011 ) - or ( 101 ) Planes, as well as in the direction of the ( 111 ) A level. Such deviations, whether they are accidental or due to other mechanical or structural reasons, are considered to be within the scope of the invention.

1. (i) eine benachbarte (111)A-Ebene um mindestens 6° und höchstens 20°;
2. (ii) eine benachbarte (011)-Ebene um mindestens annähernd 1°;
3. (iii) eine benachbarte (101)-Ebene um mindestens annähernd 1°; und
4. (iv) irgendeine Ebene, die in dem Kontinuum von Ebenen liegt zwischen (i) und (ii), (i) und (iii) oder (ii) und (iii), vgl. oben.

Thus, and in its most general form, the present disclosure encompasses by mentioning or citing the "clipping from the ( 001 ) Crystal plane through at least 6 ° to the ( 111 ) A-Plane "the pivoting of the truncated plane P to any of the following planes:

1. (i) an adjacent ( 111 ) A-plane by a minimum of 6 ° and a maximum of 20 °;
2. (ii) an adjacent ( 011 ) -Plane by at least approximately 1 °;
3. (iii) an adjacent ( 101 ) -Plane by at least approximately 1 °; and
4. (iv) any level lying on the continuum of levels between (i) and (ii), (i) and (iii) or (ii) and (iii), see above.

3B Figure 13 is an enlarged perspective view of a cut GaAs substrate showing how the cut results in step-like planar steps extending across the surface of the substrate.

4A Figure 3 is a graphical representation of the band gap of certain binary materials and their lattice constants. The band gap and lattice constants of ternary materials are arranged in the lines that are between typical associated binary materials (such as the ternary material GaAlAs located between the GaAs and AlAs points on the graph, with the band gap of the ternary material between 1.42 eV for GaAs and 2.16 eV for AlAs depends on the relative size of the individual components). Thus, depending on the band gap desired, the material constituents of the growth template and the ternary materials that are lattice-matched to it can be selected in a suitable manner for the construction of new solar cell subcell sequences. Line A in the graph represents one of the material combinations of the band gaps or band gaps and the lattice constants of the ternary materials that can be grown on a gallium arsenide, as is known in the art.

4B is a graph showing the band gap of certain binary materials and their Lattice constants as in 4A Figure 3 illustrates where line B represents one of the material combinations of bandgaps and lattice constants of ternary materials that can be grown on an alternative substrate according to the invention. Thus, depending on the desired band gap, the material components of the growth template and the ternary materials, which can be lattice-matched thereto, can be selected in a suitable manner for the construction of new solar subcell sequences.

5 Figure 13 is a graph showing the range of bandgaps of various GalnAIAs materials as a function of the relative concentration of Al, In and Ga. This graph illustrates how the selection of a constant bandgap sequence of layers of GalnAIAs in the metamorphic layer can be designed by properly selecting the relative concentration of Al, In and Ga to meet different lattice constant requirements for each successive layer. Thus, whether 1.5 eV or 1.1 eV or some other bandgap value is the desired constant bandgap, the graph illustrates a continuous curve for each bandgap, representing incremental changes in component proportions as the lattice constant change, so the layer has the required band gap and lattice constant.

6th Figure 13 is a graph further illustrating the selection of a constant bandgap sequence of layers of GaInAlAs used in the metamorphic layer by representing the Ga mole fraction as a function of the Al-to-In mole fraction in GalnAIAs materials that are necessary to get a constant 1.5 eV band gap.

7th Figure 13 is a graph further illustrating the selection of a constant bandgap sequence of layers of GalnAIAs used in the metamorphic layer, the illustration being made by plotting the molar fraction as a function of the lattice constants in GalnAIAs materials necessary to establish a constant 1.5 eV band gap.

8th Fig. 10 illustrates the multi-junction solar cell according to the present invention after sequentially forming or forming three sub-cells A, B and C on a GaAs growth substrate. In particular, there is a substrate here 101 shown, which is preferably gallium arsenide (GaAs), but can also be germanium (Ge) or another suitable material. For GaAs, the substrate is preferably a 15 ° trimmed substrate, i.e. the surface is 15 ° opposite the ( 100 ) Level to the ( 111 ) A-plane offset as detailed in U.S. Patent Application Serial No. 12 / 047,944 published as US 2009/0 229 662 A1 filed March 13, 2008.

In the case of a Ge substrate, a nucleation layer (not shown) is placed directly on the substrate 111 deposited. Furthermore, there is a buffer layer on the substrate or above the nucleation or nucleation layer (in the case of a Ge substrate) 102 and an etch stop layer 103 still deposited. In the case of a GaAs substrate, this is the buffer layer 102 preferably GaAs. In the case of a Ge substrate, this is the buffer layer 102 preferably InGaAs. A contact layer 104 GaAs then becomes on top of the layer 103 deposited and a window layer 105 AllnP is deposited over the contact layer. The subcell A, consisting of an n + emitter layer 106 and a p-type base layer 107 , then becomes epitaxial on the window layer 105 deposited. The sub-cell A is generally lattice-matched to the growth substrate 101 .

It should be noted that the multijunction solar cell structure could be formed by any suitable combination of Group III-to-V elements listed in the Periodic Table, taking into account the lattice constants and band spacing requirements, Group III including: Boron (B) , Aluminum (Al), gallium (Ga), indium (In) and thallium (T). Group IV includes carbon (C), silicon (Si) and germanium (Ge) and tin (Sn). Group V. includes nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb) and bismuth (Bi).

In the preferred embodiment, the emitter layer is 106 made of In-Ga (Al) P and the base layer 107 is made up of InGa (AI) P. The aluminum or Al term in brackets in the formula mentioned means that Al is an optional component and in this case in an amount of 0% to 30%. The doping profile of the emitter and base layers 106 and 107 according to the present invention is used in conjunction with 23 discussed.

Sub-cell A finally becomes the “upper” sub-cell of the inverted metamorphic structure after completion of the processing steps according to the present invention, which will be described below.

On top of the base layer 107 becomes a BSF or Back Surface Field (BSF) layer 108 (rear surface field layer 108 ), preferably p + AlGaInP, deposited and used to reduce the recombination loss.

The BSF layer 103 drives minority carriers from the zone near the base / BSF interface surface to minimize the effect of recombination loss. In other words: The BSF layer 18th reduces the recombination loss on the back of the solar subcell A and thereby reduces the recombination in the base.

On top of the BSF layer 108 a sequence of heavily doped p-type and n-type layers 109a and 109b, which form a tunnel diode, ie an ohmic circuit element which connects subcell A with subcell B, is deposited. The layer 109a consists preferably of p ++ AlGaAs and the layer 109b is preferably made up of n ++ InGaP.

On top of the tunnel diode layers 109 becomes a window layer 110 deposited, preferably n + InGaP. The window layer used in sub-cell B. 110 works to reduce interface recombination loss. Those skilled in the art will recognize that an additional layer or layers can be added or omitted in the cell structure without departing from the scope of the present invention.

On top of the window layer 110 the layers of subcell B are deposited: the n-type emitter layer 111 and the p-type base layer 112 . These layers are preferably made of InGaP or In _0.015 GaAs (for a Ge substrate or growth template) or of InGaP or GaAs (for a GaAs substrate), although any other materials can be used which meet the requirements for lattice constants and Band gap. Thus, the sub-cell B can be constructed with a GaAs, GaInP, GaInAs, GaAsSb or GaInAsN emitter region or zone and a GaAs, GaInAs, GaAsSb or GaInAsN base zone. The doping profile of the layers 111 and 112 according to the present invention is used in conjunction with 23 discussed.

• Weder der mittlere Subzelle B- oder der untere Subzellen C-Emitter ist absorbierbarer Strahlung ausgesetzt. Die Strahlung wird im Wesentlichen in den Basen der Zellen B und C absorbiert, die schmälere Bandabstände als die Emitter besitzen. Daher sind die Vorteile der Verwendung von HeteroJunction-Subzellen die Folgenden: (i) Kurzes Wellenlängenansprechen für beide Subzellen wird verbessert, und (ii) die Masse der Strahlung wird effektiver absorbiert und in der schmäleren Bandabstandsbasis gesammelt. Dieser Effekt erhöht J_sc.

In the preferred embodiment of the present invention, the center sub cell emitter has a band gap equal to the top sub cell emitter and the bottom sub cell emitter has a band gap greater than the band gap of the base of the center sub cell. Therefore, after the solar cell is manufactured and the operation is implemented:

• Neither the middle sub-cell B or the lower sub-cell C emitter is exposed to absorbable radiation. The radiation is essentially absorbed in the bases of cells B and C, which have narrower band gaps than the emitters. Therefore, the advantages of using HeteroJunction subcells are as follows: (i) Short wavelength response for both subcells is improved, and (ii) the bulk of the radiation is more effectively absorbed and collected in the narrower bandgap basis. This effect increases J _sc .

On top of cell B is a layer of BSF 113 deposited, which performs the same function as the BSF layer 109 . The p ++ / n ++ tunnel diode layers 114a or. 114b are above the BSF layer 113 similar to the layers 109a and 109b are deposited and form an ohmic circuit element to connect the sub-cell B to the sub-cell C. The layers 114a are preferably composed of p ++ AlGaAs and n ++ - InGaP.

A barrier or barrier layer 115 , preferably made up of n-type InGa (Al) P, is over the tunnel diode 114a / 114b deposited to a thickness of approximately 1.0 micrometer. The purpose of this barrier is to prevent threading dislocations from reproducing, either in the opposite direction to the direction of growth in the middle and upper subcells A and B or in the direction of growth in the lower or bottom subcell C, which is described in detail in pending U.S. Patent Application Serial No. 11 / 860,183 published as US 2009/0 078 309 A1 , filed September 24, 2007.

A metamorphic layer (or graded intermediate layer) 116 is above the barrier 115 deposited using a wetting agent or surface treatment agent (surfactant). The layer 116 is preferably a compositionally step-graded series of InGaAlAs layers, preferably with monotonically changing lattice constants, so as to achieve a gradual transition in the lattice constant in the semiconductor structure from subcell B to subcell C, while the occurrence of screw dislocations is minimized. The band gap of the layer 116 is constant over the entire thickness, preferably approximately equal to 1.5 eV, or otherwise consistent with a value slightly larger than the band gap of the middle subcell B. The preferred embodiment of the graded intermediate layer can also be made from (In _x Ga _1-x ) _y Al _1-y As, where x and y are selected such that the band gap of the intermediate layer remains constant at approximately 1.50 eV.

In the wetting agent-assisted growth of the metamorphic layer 116 an appropriate chemical element is introduced into the reactor during the growth of the layer 116 introduced to improve the surface characteristics of the layer. In the preferred embodiment, such an element can be a dopant or a donor atom such as selenium (Se) or tellurium (Te). Small amounts of Se or Te are thus in the metamorphic layer 116 installed and remain in the finished solar cell. Although Se or Te are preferred n-type doping atoms, other non-isoelectronic surfactants can also be used.

Wetting agent-assisted growth results in a much smoother or planar surface. Since the surface topography affects the bulk properties of the semiconductor material as it grows, as the layer gets thicker and thicker, the use of wetting agents can minimize the screw dislocations in the active regions or zones and improve overall solar cell efficiency.

As an alternative to using a non-isoelectronic wetting agent, one can use an isoelectronic wetting agent. The term “isoelectronic” refers to wetting agents such as antimony (Sb) or bismuth (Bi), since such elements have the same number of binding electrons as the P atom of InGaP or the As atom in InGaAlAs in the metamorphic buffer layer. Such Sb or Bi wetting agents are not typically in the metamorphic layer 116 built-in.

In an alternative embodiment, where the solar cell has only two sub-cells and the “middle” cell B is the top or top sub-cell in the final solar cell, with the “top” sub-cell B typically having a band gap of 1.8 to 1.9 eV the band gap of the inner layer would remain constant at 1.9 eV.

In the inverted metamorphic structure described in the Wanlass et al reference noted above, the metamorphic layer consists of nine compositionally graded InGaP steps, each step layer having a thickness of 0.25 micrometers. As a result, each layer in Wanlass et al has a different band gap. In the preferred embodiment of the present invention, the layer is 116 built up or composed of a multiplicity of layers of InGaAlAs, namely with monotonically changing lattice constant, each layer having the same band gap of approximately 1.5 eV.

The advantage of using a constant bandgap material such as InGaAlAs is that the arsenide-based semiconductor material is much easier to process with the usual commercial MOCVD reactors, with the small amount of aluminum increasing the radiolucency of the metamorphic layers ensures.

Although the preferred embodiment of the present invention uses a plurality of layers of InGaAlAs for the metamorphic layer 116 is used, for reasons of manufacturability and radiation transparency, other exemplary embodiments of the present invention can use different material systems in order to achieve a change in the lattice constants from subcell B to subcell C. In this way, Wanlass's system using compositionally graded InGaP is a second embodiment of the present invention. Other embodiments of the present invention may use continuously graded materials as opposed to step graded materials. More generally, the graded intermediate layer can be composed of any of the As-PN-Sb-based III-V compound semiconductors, bearing in mind the constraints of having an "in-plane" lattice parameter that is greater than or equal to that of the second solar cell and less than or equal to that of the third solar cell, with a band gap energy greater than that of the second solar cell.

In another embodiment of the present invention, an optional or optional second barrier layer 117 over the InGaAIAs metamorphic layer 116 be secluded. The second barrier 117 will typically have a different composition than the composition of the barrier layer 115 and performs essentially the same function of preventing the propagation of screw dislocations. In the preferred embodiment, the barrier layer is 117 n + -type GaInP.

A window layer 118 , preferably composed of n + -type GaInP, is then placed over the barrier layer 117 (or directly over layer 116 in the absence of a second barrier layer) deposited. This window layer works to reduce the recombination loss in sub-cell "C". It is clear to the person skilled in the art that additional layers can be added or omitted in this cell structure without departing from the scope of the invention.

On top of the window layer 118 the layers of cell C are deposited: the n + emitter layer 119 and the p-type base layer 120 . These layers are preferably composed of n + -type InGaAs and n + -type InGaAs, respectively, or of n + -type InGaP and p-type InGaAs for heterojunction subcells, although other suitable materials can also be used in accordance with lattice constant and band gap requirements . The doping profile of the layer 119 and 120 will be used in conjunction with 23 discussed.

A BSF layer 121 , preferably composed of P ⁺ GaInP, is then deposited on top of cell C, the BSF layer having the same function as the BSF layers 108 and 113 executes.

Next is a tunnel diode with layers 122 and 123 over the BSF layer 121 deposited similar to the layers 114 , 109 , again forming an ohmic circuit element to connect the subcell C to the subcell D. The p ⁺⁺ layer 122 is preferably made of GalnAsP, * and the n ⁺⁺ 'layer 123 is preferably based on GalnAsP.

In 9 becomes a window layer 125 , preferably consisting of n + -type InGaAIAs, then over the layer 124 deposited (or over a second barrier layer, if one is present, disposed over the layer 124 ). This window layer works to reduce the recombination loss in sub-cell "D". Those skilled in the art will recognize that additional layers can be added or removed from the cell structure without departing from the scope of the present invention.

On top of the window layer 124 the layers of cell D are deposited: the n + emitter layer 125 and the p-type base layer 126. These layers are preferably made of n-type GaInAs and p-type GaInAs, respectively, or of n-type InGaP or p-type InGaAs for a heterojunction subcell, although other suitable materials are consistent with the Lattice constants and the band gap requirements can also be used. The doping profile of the layers 125 and 126 is used in conjunction with the 23 discussed.

Next, as in 10 shown a BSF layer 127 , preferably made up of p + -GalnAsP, then deposited on top of cell D, the BSF layer performing the same function as the BSF layers 108 , 113 and 121 .

Finally, a p ⁺ contact layer 128, preferably composed of p ⁺ -GalnAs, is on top of the BSF layer 127 deposited.

In the next process step, a metal contact layer is used 129 deposited over the p + semiconductor contact layer 128. The metal is preferably the result of metal layers Ti / Au / Ag / Au, although other suitable materials and sequences could be used.

The metal contact materials and layers are also selected in such a way that a planar intermediate layer (interface) results, namely with the semiconductor contact layer underneath, after heat treatment in order to activate the ohmic contact. This is done in such a way that (i) an electrical layer which separates the metal from the semiconductor does not have to be deposited and selectively etched in the metal contact areas; and (ii) the contact layer is specularly reflective over the wavelength range of interest.

12th FIG. 13 is a cross-sectional view of the solar cell of FIG 11 after the next processing step, in which a bonding or adhesive layer 130 over the metal layer 129 is deposited. In one embodiment of the invention, the tie layer is an adhesive, preferably a wafer adhesive (manufactured by Brewer Science, Inc. of Rolla, MO). In other exemplary embodiments of the invention, a solder or a eutectic connecting layer is used 130 as described in U.S. Patent Application Serial No. 12 / 271,127 published as US 2010/0 122 764 A1 , filed on November 14, 2008, or else it will be a link layer 130 used where the surrogate substrate remains as a permanent support component on the finished solar cell.

13A FIG. 13 is a cross-sectional view of the solar cell of FIG 12th after the next processing step in which a surrogate substrate 150 , preferably sapphire, is attached. Alternatively, the surrogate substrate can be GaAs, Ge, or Si or any other suitable material. The surrogate substrate is approximately 40 mils thick and in the embodiments in which the surrogate substrate is to be removed it is perforated with holes approximately 1 mm in diameter and spaced 4 mm apart to facilitate subsequent removal of the adhesive and substrate.

In the next procedural step, as shown in 13A will be the original growth substrate 51 and the carrier 40 removed by local heating with a laser and subsequent etching to remove the layers 51 and 102 .

13B FIG. 13 is a cross-sectional view of the solar cell of FIG 13A , the orientation with the surrogate substrate 150 and the bottom of the figure takes place. Subsequent figures in this application assume this orientation.

14th FIG. 13 is a simplified cross-sectional view of the solar cell of FIG 13B with only a few of the upper layers and lower layers above the surrogate substrate 150 are shown after the removal of the buffer layer 102 .

15th FIG. 13 is a cross-sectional view of the solar cell of FIG 14th after the next Processing step in which the etch stop layer 103 is removed by an HCl / H2 _{o solution.}

16 Fig. 3 is a cross-sectional view of the solar cell 15th after the next series of processing steps in which a photoresist mask (not shown) is placed over the contact layer 104 is arranged around the grid lines or lines 501 to build. As will be described in detail below, the grid lines 501 deposited by evaporation and lithographic patterning and deposition occurs over the contact layer 104 . The mask is then removed to create the finished metal grid lines 501 as shown in the following figures.

The grids 501 are preferably built on Pd / Ge / Ti / Pd / Au or other suitable materials, as detailed in US Patent Application Serial No. 12/218 582 published as US 2010/0 012 175 A1 , filed July 18, 2008. This document is incorporated herein by reference.

17th FIG. 13 is a cross-sectional view of the solar cell of FIG 16 after the next processing step in which the grid lines are used as a mask to make the surface to the window layer 105 etch down using a citric acid / peroxide etch mixture.

18A Fig. 13 is a plan view of a wafer in which four solar cells are implemented. The representation of the four cells is for the purpose of illustration and the present invention is not limited to any particular number of cells per wafer.

There are grid lines in each cell 501 (particularly shown in the cross section in 17th ), an interconnection bus line 502 and a contact terminal 503 . The geometry and the number of grid and bus lines and the contact connection are shown by way of illustration and the invention is not restricted to the exemplary embodiment shown.

18B FIG. 13 is a bottom plan view of the four solar cell wafer of FIG 18A .

18C Figure 13 is a plan view of a wafer in which two solar cells are implemented. The representation of two cells in this figure is for illustrative purposes only.

19th FIG. 13 is a cross-sectional view of the solar cell of FIG 17th after the next process step, in which an anti-reflective (ARC) dielectric coating layer 130 over the entire surface of the "bottom" side of the wafer with the grid lines 501 is upset.

20A FIG. 13 is a cross-sectional view of the solar cell of FIG 19th after the next processing step according to the invention, in the first and second ring channels 510 and 511 or part of the semiconductor structure on the metal layer 129 is etched down using phosphide and arsenide etchants. These channels define a perimeter boundary between the cell and the rest of the wafer, leaving a mesa structure that forms the solar cell. The in 20A The cross-section shown is the one seen from an AA plane according to FIG 21 looks like. In a preferred embodiment, the channel is 510 considerably wider than the canal 511 .

20B FIG. 13 is a cross-sectional view of the solar cell of FIG 20A after the next process step in which the channel 511 exposing the layer to a metal etchant 123 in the canal 511 is removed and the channel 511 its depth is expanded approximately to the upper surface of the bonding or adhesive layer 130 down.

21 FIG. 14 is a top plan view of the wafer of FIG 20A and 20B , being channels 510 and 511 etched around the perimeter of each cell.

22A FIG. 13 shows a cross-sectional view of the solar cell of FIG 20B , after which the individual solar cells (cell 1, cell 2, etc., shown in 21 ) are cut or separated from the wafer, namely the channel 511 leaving a vertical edge 515 that stand out through the surrogate substrate 150 at the location of the canal 511 extends. In this first embodiment of the invention, the surrogate forms the substrate 150 the carrier for the solar cell in applications where a cover glass (for example provided in the third exemplary embodiment, as described below) is not required. In such an embodiment, the electrical contact to the metal contact layer 129 through the canal 510 respectively.

22B FIG. 13 is a cross-sectional view of the solar cell of FIG 22A after the next processing step in a second embodiment of the invention, in which the surrogate substrate 150 suitably on a relatively thin layer 150a is thinned by grinding, lapping or etching. In this embodiment, the thin layer forms 132a the carrier for the solar cell in applications where a cover glass is not required, as is provided for the second embodiment to be described below. In such an embodiment, the electrical contact to the metal contact layer 129 through the canal 510 respectively.

22C FIG. 13 is a cross-sectional view of the solar cell of FIG 22A after the next processing step in a second embodiment of the invention, in which a cover glass 514 at the top of the cell with an adhesive 513 is attached. The cover glass 514 preferably covers the entire canal 510 but does not extend to the perimeter of the cell near the canal 511 . While the use of a cover glass is the preferred embodiment, it is not required for all implementations and additional layers or structures can also be used to provide additional support or environmental protection for the solar cell.

23 FIG. 13 is a cross-sectional view of the solar cell of FIG 22A after the next process step of the present invention, in which the adhesive layer 130 , the surrogate substrate 150 and the peripheral part 512 of the wafer are completely removed, with the break in the zone of the channel 510 takes place what only the solar cell with the cover glass 514 (or other layers or structures) on top and the metal contact layer 129 on the ground, which forms the rear contact of the solar cell. The surrogate substrate 150 is preferably removed using the etchant "Wafer Bond Solvent". As noted above, the surrogate substrate has perforations across its surface that allow the etchant to pass through the surrogate substrate 150 can flow to allow its removal. After removal (lift-off), the surrogate substrate can be used again in subsequent wafer processing operations.

24 Figure 3 is a graphical representation of a doping profile in the emitter and base layers of one or more subcells of the inverted metamorphic multijunction solar cell according to the invention. The various doping profiles that are within the scope of the invention and the advantages of such doping profiles are detailed in pending US patent application Ser. 11/956 069 published as US 2009/0 155 952 A1 , filed December 13, 2007, which is incorporated herein by reference into the disclosure of this application. The doping profiles shown therein are merely illustrative and other more complicated profiles can be used as would be apparent to those skilled in the art without departing from the scope of the invention.

The person skilled in the art recognizes that an additional or additional layers in the cell structure of the 13B can be added or omitted without departing from the scope of the invention.

It will be recognized that any of the elements described above, or two or more together, may find useful application in other types of constructions other than those described above.

Although the preferred embodiment of the present invention uses a vertical stack of four sub-cells, the present invention can also be applied to stacks with fewer or more sub-cells, ie two-junction cells, three-junction cells, five-junction cells, etc. as published in U.S. Patent Application Serial No. 12 / 267,812 as US 2010/0 116 327 A1 , filed November 10, 2008. In the case of four or more junction cells, more than one metamorphic grading layer can also be used, as disclosed in US patent application Ser. No. 12 / 271,192 as published in US Pat US 2010/0 122 724 A1 of November 14, 2008.

In addition, the following applies: Although the present exemplary embodiment is configured with upper and lower electrical contacts, the sub-cells can be contacted in an alternative manner, specifically by means of metal contacts on lateral conductive semiconductor layers between the cells. Such arrangements can be used to achieve 3-port, 4-port, and generally n-port devices. The sub-cells can be connected between circuits using these additional connections in such a way that the available photo-generated current density of each sub-cell can be used in an effective manner, which leads to a high efficiency for the multijunction cell without contradicting the fact that the photo-generated current densities are typically different in the different sub-cells.

As mentioned above, the present invention can use an arrangement of one or more or all of the homojunction cells or sub-cells, ie a cell or sub-cell in which the pn-junction (junction) is formed between a p-type semiconductor and an n -Type semiconductors, where both have the same chemical composition and the same band gap, but differ only in the type of dopant and the types, and one or more heterojunction cells or sub-cells can be provided. The p-type and n-type InGaP subcell A is an example of a homojunction subcell. Alternatively, as specifically disclosed in U.S. Patent Application Serial No. 12 / 023,772 published as US 2009/0 078 310 A1 , filed January 31, 2008, the invention may use one or more or all of the heterojunction cells or sub-cells, that is, a cell or sub-cell in which the pn junction is formed by a p-type semiconductor and an n -Type semiconductors with different chemical compositions of the semiconductor material in the n-type zones and / or different band gap or band gap energies in the p-type zones or regions, in addition to the use of different dopant types and the type of p-type and n-type regions that form the pn junction.

In some cells, a thin so-called intrinsic barrier layer (“intrinsic layer” or i-layer) can be arranged between the emitter layer and the base layer with the same or different composition of both the emitter and base layers. The intrinsic layer suppresses the minority carrier recombination in the space charge zone. The following applies in a similar manner: Either the base layer or the emitter layer can also be doped intrinsically or not intentionally (“NID” = not intentionally doped). part or all of the thickness.

The composition of the window or BSF layers can use other semiconductor compounds, taking into account the requirements for lattice constants and band gap; and these layers can include: AlInP, AlAs, AIP, AlGaInP, AlGaAsP, Al-GaInAs, AlGalnPAs, GaInP, GaInAs, GaInPAs. AlGaAs, AllnAs, AllnPAs, GaAsSb, AlAsSb, GaAlAsSb, AlInSb, GalnSb, AlGaInSb, AlN, GaN, InN, GaInN, AlGaInN, GaInNAs, AlGaInNAs, ZnSSe, CdSSe, and similar materials that fall within the scope of the present invention.

Although the invention has been illustrated and described as being in an inverted metamorphic multijunction solar cell, it is not intended to limit the invention to the details shown, since various modifications and structural changes can be made without departing from the scope of the invention.

Although the description of this invention is primarily focused on solar cells or photovoltaic devices, those skilled in the art will know that other optoelectronic devices may be considered, such as thermophotovoltaic (TPV) cells, photodetectors and light emitting diodes (LEDs) with very similar structure, physical properties and materials how to use photovoltaic devices, with some minor variations in doping and minority carrier lifetime. For example, photodetectors can use the same materials and structures as the photovoltaic devices described above, but possibly using less doping for sensitivity rather than power production. On the other hand, LEDs can also be made with similar structures and materials, but possibly with heavier doping in order to shorten the recombination time, in which way the radiation lifetime to generate light instead of power. is emphasized. The present invention is thus also applicable to photodetectors and LEDs with structures, material compositions and articles of manufacture with improvements as described above for the photovoltaic cells.

Claims (13)

A method of manufacturing a solar cell, wherein the following is provided: Providing a semiconductor carrier (50) made of GaAs or Ge with a prepared connection surface which, by implanting a species into the semiconductor carrier (50), forms a defective layer (51) in the semiconductor carrier (50); Providing a support substrate (40) having an interconnection surface; Connecting the semiconductor carrier (50) and the carrier substrate (40) by a molecular connection of the prepared connection surfaces of the semiconductor carrier (50) and the carrier substrate (40) to produce a composite structure (40, 51, 52); nondestructively separating the majority (52) of the reusable semiconductor carrier (50) from the composite structure (40, 51, 52) leaving a semiconductor growth substrate (51) made of GaAs or Ge on the carrier substrate (40); Deposition of a sequence of layers of semiconductor material including one or more metamorphic buffer layers and a metal layer (129) on top of the sequence of layers to form a solar cell on the semiconductor growth substrate (51), with one or more metamorphic buffer layers to adapt the different lattice constants of the individual layers serve from semiconductor material; Attaching a surrogate substrate (150) on top of the metal layer and the sequence of layers of semiconductor material to form the solar cell, Removing the support substrate (40) and the semiconductor growth substrate (51) and leaving behind the sequence of layers of semiconductor material forming the solar cell. Procedure according to Claim 1 wherein separating the bulk of the semiconductor carrier from the composite structure comprises: implanting a species or species into the semiconductor carrier to form a defective layer in the semiconductor carrier; Connecting the defective layer of the semiconductor carrier directly to the carrier substrate to produce the composite structure; and severing the bulk of the semiconductor carrier from the composite structure, leaving a thin semiconductor growth substrate on the carrier substrate. Procedure according to Claim 2 wherein separating the mass of the semiconductor carrier from the composite structure comprises: annealing the composite structure at an elevated temperature to weaken the semiconductor carrier and the defective layer; and separating the bulk of the semiconductor carrier from the composite structure along the defective layer or during the annealing of the composite structure. Procedure according to Claim 1 wherein the thickness of the semiconductor substrate is approximately 5 micrometers and further wherein the thickness of the bulk of the semiconductor carrier separated from the composite structure is greater than 350 micrometers Procedure according to Claim 1 wherein the connection surface of the semiconductor carrier produced is also roughened, to be precise before the carrier and carrier substrate are connected. Procedure according to Claim 1 further comprising: (i) forming a new bonding surface on the severed bulk portion of the semiconductor carrier to form a new semiconductor carrier; (ii) providing a new support substrate; (iii) joining the new semiconductor carrier and the new carrier substrate to produce a new composite structure; (iv) severing the bulk of the new semiconductor carrier from the new composite structure, leaving a new semiconductor substrate on the new carrier substrate; and (v) depositing a sequence of layers of semiconductor material to form a solar cell on the new semiconductor substrate; and (vi) repeating steps (i) through (v) with the severed bulk portion of the new semiconductor carrier. Procedure according to Claim 1 wherein the carrier substrate is sapphire or sapphire / spinel and wherein the semiconductor carrier is gallium arsenide, which is cut off from the (001) crystal plane by at least 6 ° to the (111) plane. Procedure according to Claim 1 further comprising: placing a second surrogate substrate on top of the sequence of layers of semiconductor material to form a solar cell, and removing the semiconductor growth substrate. Procedure according to Claim 1 wherein the step of depositing a sequence of layers on the gallium arsenide substrate comprises: forming or forming an upper first solar sub-cell having a first band gap on the gallium arsenide substrate; Forming a second central solar cell over the first solar subcell with a second band gap smaller than the first band gap; Forming a graded intermediate layer over said second solar cell; Forming a third solar sub-cell over the graded intermediate layer with a fourth band gap that is smaller and a second band gap such that the third sub-cell is lattice-misaligned with respect to the second sub-cell. Procedure according to Claim 9 wherein the following is further provided: Forming a lower fourth solar sub-cell over the third sub-cell with a fifth band gap smaller than that of the fourth band gap such that the third sub-cell is lattice-matched with respect to the third sub-cell. Procedure according to Claim 9 , wherein the upper sub-cell is made up of InGa (Al) P, the second sub-cell is made up of GaAs, GaInP, GaInAs, GaAsSb or GaInAsN emitter region or zone and a GaAs, GaInAs, GaAsSb or GalnAsN -Base region and where the third sub-cell is made up of a GaInAsP base and an emitter. Procedure according to Claim 10 , whereby the fourth sub-cell consists of GalnAs base and emitter layers. Procedure according to Claim 9 wherein the graded intermediate layer is compositionally graded to cause lattice matching in the second sub-cell on one side, the third sub-cell being located on the other side and consisting of (In _x Ga _1-x ) _y , where Al _1-y As is constructed, namely x and y selected such that the band gap of the intermediate layer is constant across the thickness.

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