DE102009000126B4 - Drift compensation of charge amplifier circuits - Google Patents

Abstract

Transmission gate (100) with an NMOS transistor (110) connected between a signal input and a signal output and a PMOS transistor (120) connected in parallel with the NMOS transistor (110), the NMOS transistor (110) and the PMOS -Transistors (120) each have a source connection, a drain connection, a gate connection and a bulk, the bulk of the NMOS transistor (110) being connected to a first supply voltage source (GND) for a first supply voltage and the bulk of the PMOS transistor (120) are connected to a second supply voltage source (VDD) for a second supply voltage which is higher than the first supply voltage, characterized in that the NMOS transistor (110) has a first channel width (WN) and a first channel length (LN) and the PMOS -Transistor (120) have a second channel width (WP) and a second channel length (LP), a first ratio (WN / LN) of the first channel width (WN) to the first channel length (LN) and a second the ratio (WP / LP) of the second channel width (WP) to the second channel length (LP) are chosen so that a first leakage current (IleckN) from the signal input to the bulk of the NMOS transistor (110) is equal to a second leakage current (IleckP) from Bulk of PMOS transistor (120) to signal input is.

Description

State of the art

The invention relates to a transmission gate with drift compensation, an integrator with such a transmission gate, a pressure sensor with such an integrator and an internal combustion engine with such a pressure sensor.

Sensors can be categorized according to the type of measurement signal they provide. There are, for example, resistive sensors that convert the measured variable into a variable ohmic resistance, or capacitive sensors that generate a charge as a measurement signal. Such a capacitive sensor is represented by piezoceramic or quartz-crystalline pressure sensors, which build up electrical charges depending on the pressure acting on the sensor. Because these charges are only very small, charge amplifier circuits must be used that amplify the measurement signal. In practice, the detour via conversion into an output current is usually taken, with the charges generated by the sensor being detected as current in a specific time unit. In a linearized approach with the current le, the charge Qs generated by the sensor and the time unit Δt: $${\text{l}}_{\text{e}}{\text{= Q}}_{\text{s}}/\Delta \text{t}$$

wobei U_a die Ausgangsspannung und C die Kapazität des Kondensators bedeuten.Since the built-up charges can only produce a very low current, it is necessary under practical conditions to integrate this measuring current over a certain period of time and thus to amplify it. A charge amplifier therefore corresponds to the known integrator circuit with a capacitor in the feedback. The output voltage generated by integration can then be easily evaluated using common methods such as A / D conversion and follows the following regularity (again linearized): $${\text{U}}_{\text{a}}={\text{l}}_{\text{e}}*\Delta \text{t / C}\text{,}$$

where U _{a is} the output voltage and C is the capacitance of the capacitor.

A problem with the integration of the measurement signal is that the circuit elements of the customary integrator circuits themselves generate leakage currents which falsify the measurement signal. If the current generated by the sensor is very small, such falsifications have a greater effect, which undesirably limits the measurement accuracy. In addition, the leakage currents drive the integrator into saturation after a time dependent on the size of the leakage currents and the capacitance of the capacitor, so that the charge already stored on the capacitor has to be neutralized at certain time intervals by short-circuiting the capacitor. This represents e.g. B. for a pressure measurement inside a combustion chamber of an internal combustion engine is a problem, since here the pressure conditions varying during a crankshaft revolution are to be determined by a measurement over the entire period of the movement cycle, but this period is longer than the maximum available with regard to an acceptable error tolerance standing time interval until the capacitor is short-circuited again. Another problem is that the leakage currents increase with increasing temperature, so that they represent an even greater obstacle for measurements of this type, which naturally take place at high temperatures. There is consequently a need for circuit elements which have a particularly low leakage current, and it is the object of the invention to introduce such circuit elements for the purposes indicated.

In the US 2005/0219102 A1 and the US 6,348,831 B1 Transmission gates of an analog switch with NMOS and PNOS are shown, each with different supply voltages at their substrate inputs. The DE 39 05 824 A1 and the US 2005/0 103 977 A1 each show integrators of the prior art.

Disclosure of the invention

In order to achieve the object, a first aspect of the invention introduces a transmission gate according to claim 1.

In CMOS technology, at least one of the two basic transistor types (PMOS or NMOS) is located in a so-called tub. In order for this well to have a defined potential, it is usually short-circuited with the source of the transistor. In the case of a transistor that is not located in a well, the bulk of the transistor is part of the substrate which is usually connected in its entirety to one of the supply voltages.

The invention is based on the knowledge that an output leakage current of a transmission gate can be suppressed at least approximately if the leakage current of the PMOS transistor is as equal as possible to the leakage current of the NMOS transistor. In such a case, the leakage current flowing from the bulk of the PMOS transistor to the source or drain of the PMOS transistor is compensated for by the leakage current from the source or drain of the NMOS transistor to the bulk of the NMOS transistor. From Kirchhoff's first law it follows for the output node of a transmission gate: $$|{}_{\text{leakP}}\text{-}|{}_{\text{leakN}}-|{}_{\text{leaky}}=0$$

It follows from this that in the case of a blocking transmission gate, I _{leakage becomes} zero when I _leakP equals I _leakN . Since I _{leakges makes} an undesirable contribution to the current integrated on the capacitor of the integrator, an optimal drift compensation is given in this case. The invention makes this possible in that, compared to the prior art, the bulks of both the NMOS transistor and the PMOS transistor are connected to the respective supply voltages, so that both transistor types have at least approximately the same leakage currents.

In circuit technology, it is customary to characterize transistors for a given manufacturing process by means of their channel length and channel width or the ratio of these two variables. The inventive transmission gate includes that the channel width and length of the NMOS transistor and PMOS transistor are selected so that a leakage current from the signal input of the transmission gate to the bulk of the NMOS transistor is equal to a leakage current from the bulk of the PMOS transistor to the signal input of the transmission gate is. The ratio of the channel width to the channel length of the PMOS transistor is preferably between two and four times greater than the ratio of the channel width to the channel length of the NMOS transistor.

A second aspect of the invention introduces an integrator with an integrator input and an integrator output which has a first resistor, a first capacitor and a transmission gate. The first resistor is connected between the integrator input and an inverting input of a differential amplifier, the first capacitor is connected between the inverting input of the differential amplifier and an output of the differential amplifier, and the transmission gate is connected between the inverting input and the output of the differential amplifier. The transmission gate is designed to discharge the first capacitor as a function of a control signal. The output of the differential amplifier is connected to the integrator output. The transmission gate is a transmission gate according to the first aspect of the invention.

The integrator according to the invention can advantageously dispense with a separate ESD protection (electrostatic discharge), since the first resistor together with the bulk diodes of the transmission gate already represent an ESD protection. For this purpose, it is necessary to provide appropriate lead diodes on the supply voltages. As a result, ESD protection known in the prior art at the input or at the inputs of the integrator can be dispensed with, which in turn would cause disruptive leakage currents. It has been shown that ESD protection according to the human-body model of over 800 V can be achieved in this way.

A differential variant of the integrator in which the differential amplifier is a double-ended differential amplifier and has a non-inverting input and a second output is particularly preferred. The integrator has a second resistor, a second capacitor and a second transmission gate. The first resistor is between a second integrator input and the non-inverting input of the differential amplifier, the second capacitor between the non-inverting input of the differential amplifier and the second output of the differential amplifier connected to a second integrator output and the second transmission gate between the non-inverting input and the second output of the Differential amplifier switched. The second transmission gate is a transmission gate according to the first aspect of the invention and is designed to discharge the second capacitor as a function of the control signal.

One problem with compensating for leakage currents is that the leakage currents of PMOS and NMOS transistors cannot be matched over the entire temperature and parameter range. So it is e.g. For example, it is conceivable that at a temperature of 130 degrees Celsius both leakage currents cancel each other out completely, but the leakage current of one type of transistor increases faster than that of the other type of transistor as the temperature continues to rise. The differential embodiment of the integrator according to the invention largely overcomes this problem, because the symmetrical structure of each input of the differential amplifier is subjected to the same residual leakage currents. For example, if the leakage current of the PMOS transistor of the transmission gate increases faster, the leakage current of the NMOS transistor of the transmission gate can no longer compensate for it. The transmission gate then outputs a leakage current I _leak1 with the consequences mentioned above. The second transmission gate will, however, behave in the same way and generate a leakage current I _leak2 that is the same _apart from deviations caused by production _tolerances . However, in the case of a monolithic structure in an integrated chip, the deviations due to production tolerances are only in a range of up to about ten percent of the absolute values due to the assumed small distance between the components. This fact is commonly known as “matching”. Since the differential amplifier only amplifies the difference between its input signals, only the Deviations in leakage currents due to incomplete matching. It is therefore possible to reduce the effect of the temperature drift due to the leakage currents of the transistors by an order of magnitude, so that the common mode range of the differential charge amplifier is not exceeded or undershot.

A third aspect of the invention relates to a pressure sensor with a piezoelectric sensor and an integrator connected to the piezoelectric sensor according to the second aspect of the invention.

A fourth aspect of the invention relates to an internal combustion engine with a pressure sensor designed to measure the pressure in a combustion chamber of the internal combustion engine according to the third aspect of the invention.

Figure list

• 1 ein Transmission-Gate gemäß der Erfindung;
• 2 einen Integrator mit einem als Transmission-Gate ausgeführten Schalter; und
• 3 einen differentiellen Integrator.

The invention is explained in more detail below with reference to a few illustrations of exemplary embodiments. Show it:

• 1 a transmission gate according to the invention;
• 2 an integrator with a switch designed as a transmission gate; and
• 3 a differential integrator.

Detailed description of the images

1 shows a transmission gate 100 according to the invention. The transmission gate 100 has two transistors connected in parallel 110 , 120 on, one of which is an NMOS transistor 110 and one a PMOS transistor 120 is. The transistors 110 , 120 are controlled by a control signal ST, being at the gate of the PMOS transistor 120 the logical inverse IST of the control signal ST is applied. The NMOS transistor 110 has source and drain, which - as is usual with an n-channel transistor - are constructed as n-doped regions. Since the n-channel when the NMOS transistor is switched on 110 is formed in a p-doped bulk, the semiconductor structure below the gate oxide can be configured as two diodes connected in the opposite direction 111 , 112 be understood. The bulk of the NMOS transistor 110 is switched to the low supply voltage, in the example shown to the ground voltage GND. The diodes 111 , 112 are therefore always switched in the reverse direction under normal operating conditions. In this case, however, a current can flow through the diodes 111 , 112 flow caused by the spontaneous generation and recombination of charge carrier pairs in the pn junction of the diodes 111 , 112 due to the effects of heat. This leakage current I _leakN is for the diode in the figure 111 represented by a power source. The amount of leakage current is negative in the example shown. Corresponding relationships also apply to the diode due to the symmetry of the arrangement 112 .

The PMOS transistor 120 has one opposite the NMOS transistor 110 inverted structure, that is, source and drain are formed here by p-doped regions, while the bulk is n-doped. For this reason, the pn junctions between the source and drain on the one hand and the bulk on the other hand are compared to the diodes 111 , 112 Diodes switched in the opposite direction 121 , 122 shown. The bulk of the PMOS transistor 120 is connected to the highest supply voltage VDD to ensure that the pn junctions of the PMOS transistor 120 cannot be switched through. Again, however, there is a leakage current in the reverse direction of the diodes due to the effect of temperature 121 , 122 which one for the diode 121 is shown as a current source of a leakage current I _leakP . As the transistors 110 , 120 are connected in parallel, the leakage currents I _leakN and I _{leakP add up} at the input of the transmission gate 100 to a total current I _leakage , where the following applies if the signs are _observed : $${\text{l}}_{\text{leaky}}={\text{l}}_{\text{leakP}}-{\text{l}}_{\text{leakN}}$$

In conventional CMOS technology, the transistors of one of the two transistor types, n-channel transistor or p-channel transistor, are located in a so-called tub, while the other transistor type is arranged freely in the substrate. Alternatively, it is also possible for the transistors of both transistor types to be built in wells. Wells and substrates are placed at a defined potential to avoid uncontrolled collection and injection of charge carriers. In the case of the substrate, this is usually done by metallizing the back of the substrate and applying the corresponding supply voltage via this metallization (in the case of the n-channel transistor GND, in the case of the p-channel transistor VDD). In the case of a transistor located in a well, however, the well is usually short-circuited with the source region, so that the well can never have a potential that could switch through the pn junction between well and source. However, the invention deviates from this rule and also applies the trough to the corresponding supply voltage, again in the case of a p-channel transistor to the positive supply voltage VDD or in the case of an n-channel transistor to the negative supply voltage GND. This unusual circuit _measure ensures that the leakage currents I _leakP and I _{leakN are generated} under conditions that are as identical as possible and are therefore largely the same in terms of amount. The connection of the tub according to the invention with a supply voltage is unusual, among other things, because it requires an additional line from the supply voltage to the transistor, while the source and bulk can be short-circuited directly on the transistor. As already described, the leakage currents of both transistors 110 , 120 be adjusted to each other by appropriate dimensioning of the respective transistor lengths and widths. Experience has shown that this is possible if the ratio of transistor width to transistor length of the PMOS transistor 120 between two and four times as large as the ratio of transistor width to transistor length of the NMOS transistor 110 is.

2 shows an integrator 200 with a switch designed as a transmission gate according to the invention 210 . The desk 210 is the capacitor 220 of the integrator 200 connected in parallel and serves to power the capacitor 220 short-circuit at times determined by the control signal and thereby discharge. This is done for the integrator 200 to initialize for a new measurement cycle and the temperature drift caused and on the capacitor 220 equalize leakage currents stored as charge. The integrator 200 has a differential amplifier 230 on, between its inverting input and its output the capacitor 220 is switched. The non-inverting input of the differential amplifier 230 is connected to ground. Between them as a piezo crystal 250 executed sensor and the inverting input of the differential amplifier 230 is a resistance 240 switched.

The mutual compensation of the leakage currents in the switch designed as a transmission gate 210 is not completely possible for all temperatures, taking into account the manufacturing tolerances. In the 2 Shown embodiment of the integrator 200 therefore has the disadvantage that, at least under certain operating conditions, a leakage current I _leak remains from the switch 210 to the inverting input of the differential amplifier 230 reaches and falsifies the measurement. In a particularly preferred embodiment, the integrator is therefore designed differentially. 3 shows such a differential integrator connected as a pressure sensor 300 , which is a double-ended differential amplifier 330 is built around, so a differential amplifier with differential output. The differential integrator 300 is constructed symmetrically. There is a capacitor between each of the two outputs of the differential output and the associated input 320 , 321 switched, which preferably have identical capacities. Each of the capacitors 320 , 321 is a switch designed as a transmission gate according to the invention 310 , 311 connected in parallel, which in turn serve the capacitors 320 , 321 initialize at regular intervals for the measurement. A sensor designed as a piezo crystal 350 is about one resistor each 340 , 341 between the inverting and non-inverting inputs of the differential amplifier 330 switched.

The symmetrical circuit structure offers the advantage that any remaining leakage currents I _leakage1 and I _{leakage2 of} the switch 310 , 311 to the respective inputs of the differential amplifier 330 reach. Since a differential amplifier naturally only amplifies the difference between the two voltages applied to its inputs, both the non-inverting and the inverting input of the differential amplifier have an effect 330 Similar interference signals that are present do not affect the voltage between the two outputs of the differential output of the differential amplifier 330 out. Are the respective leakage currents I _leak1 and I _{leak2 the} same - due to the identical structure of the switches 310 , 311 is largely assumed - they compensate each other. The differential integrator 300 can, under realistic operating conditions, _reduce the effective fault current, which in this embodiment is calculated as the difference between the leakage currents I _leak1 and I _leak2 , by another order of magnitude.

It follows with a tolerable drift voltage ΔU _out of 1 mV after 240 ms with an integration capacity of 750 pF for the tolerable leakage current requirement: $$\begin{array}{c}{}_{{\text{l}}_{\text{leaks1}}-{\text{l}}_{\text{leaks2}}\le 750\text{pF * 1 mV / 240 ms}}\\ {\Delta }_{\text{llick}}\le 3.125\text{pA}\end{array}$$

The applied 240 ms correspond to two crankshaft revolutions at an engine speed of approx. 500 revolutions per minute.

Such a low leakage current can definitely be achieved in an integrated circuit due to the double compensation of the leakage currents that occur, even for measurements at high temperatures. The invention therefore allows, for example, the measurement of the internal pressure of a combustion chamber of an internal combustion engine over a full crankshaft revolution.

Claims (7)

Transmission gate (100) with an NMOS transistor (110) connected between a signal input and a signal output and a PMOS transistor (120) connected in parallel with the NMOS transistor (110), the NMOS transistor (110) and the PMOS -Transistor (120) each one Have a source connection, a drain connection, a gate connection and a bulk, the bulk of the NMOS transistor (110) being connected to a first supply voltage source (GND) for a first supply voltage and the bulk of the PMOS transistor (120) being connected to a second supply voltage source (VDD) for a second supply voltage which is higher than the first supply voltage, characterized in that the NMOS transistor (110) has a first channel width (W _N ) and a first channel length (L _N ) and the PMOS transistor (120) a second channel width (W _P ) and a second channel length (L _P ), a first ratio (W _N / L _N ) of the first channel width (W _N ) to the first channel length (L _N ) and a second ratio (W _P / L _P ) of the second channel width (W _P ) to the second channel length (L _P ) are chosen so that a first leakage current (I _leakN ) from the signal input to the bulk of the NMOS transistor (110) is equal to a second leakage current (I _leakP ) from Bulk des PMOS transistor (120) for signal input. Transmission gate (100) Claim 1 , characterized in that the second ratio (W _P / L _P ) is between two and four times greater than the first ratio (W _N / L _N ). Integrator (200, 300) with an integrator input and an integrator output, with a first resistor (240, 341) connected between the integrator input and an inverting input of a differential amplifier (230, 330), a first capacitor (220, 321), which is connected between the inverting input of the differential amplifier (230, 330) and an output of the differential amplifier (230, 330), and a transmission gate (100, 210, 311) which is connected between the inverting input and the output of the differential amplifier (230 , 330) is connected and designed to discharge the first capacitor (220, 321) as a function of a control signal, the output of the differential amplifier (230, 330) being connected to the integrator output, characterized in that the transmission gate (100 , 210, 311) is a transmission gate (100, 210, 311) according to one of the preceding claims. Integrator (200, 300) Claim 3 , characterized by a Zener diode whose anode is connected to the first supply voltage source (GND) and whose cathode is connected to the second supply voltage source (VDD). Integrator (300) according to one of the Claims 3 or 4th , characterized in that the differential amplifier (330) is a double-ended differential amplifier (330) and additionally has a non-inverting input and a second output, the integrator (300) having a second resistor (340) connected between a second integrator input and the non-inverting input of the differential amplifier (330) is connected, a second capacitor (320) which is connected between the non-inverting input of the differential amplifier (330) and the second output of the differential amplifier (330) connected to a second integrator output, and a second transmission Gate (310) after one of the Claims 1 to 3 that is connected between the non-inverting input and the second output of the differential amplifier (330) and is designed to discharge the second capacitor (320) as a function of the control signal. Pressure sensor with a piezoelectric, piezoceramic or quartz crystalline sensor (250, 350) and an integrator (200, 300) connected to the piezoelectric, piezoceramic or quartz crystalline sensor (250, 350) according to one of the Claims 3 to 5 . Internal combustion engine with a pressure sensor designed for measuring the pressure in a combustion chamber of the internal combustion engine Claim 6 .

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