DE102007004284B4 - Semiconductor power module - Google Patents

Semiconductor power module Download PDF

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Publication number
DE102007004284B4
DE102007004284B4 DE102007004284A DE102007004284A DE102007004284B4 DE 102007004284 B4 DE102007004284 B4 DE 102007004284B4 DE 102007004284 A DE102007004284 A DE 102007004284A DE 102007004284 A DE102007004284 A DE 102007004284A DE 102007004284 B4 DE102007004284 B4 DE 102007004284B4
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Prior art keywords
semiconductor
parylene
coating
power module
substrate
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DE102007004284A
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German (de)
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DE102007004284A1 (en
Inventor
Dipl.-Chem. Dr.rer.nat. Mengel Manfred
Dipl.-Chem. Dr.rer.nat. Mahler Joachim
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

Halbleiterleistungsmodul (14) mit folgenden Merkmalen: – einem Leistungssubstrat (15); – mindestens einem auf dem Leistungssubstrat (15) angeordneten Leistungshalbleiterchip (16); – mindestens einem Treiberchip (18) mit einer aktiven Vorderseite (24), der mit seiner Rückseite (19) auf das Leistungssubstrat (15) montiert ist, wobei der Treiberchip (18) auf seiner Rückseite (19) und auf seinen Randseiten (7) eine Parylen-Beschichtung (2) zur elektrischen Isolation gegenüber dem Leistungssubstrat (15) aufweist, wobei die Parylen-Beschichtung (2) eine Schichtdicke d aufweist mit 500 nm ≤ d ≤ 5 μm.Semiconductor power module (14) comprising: - a power substrate (15); - At least one on the power substrate (15) arranged power semiconductor chip (16); At least one driver chip (18) having an active front side (24) which is mounted with its rear side (19) on the power substrate (15), wherein the driver chip (18) on its rear side (19) and on its edge sides (7) a parylene coating (2) for electrical insulation with respect to the power substrate (15), wherein the parylene coating (2) has a layer thickness d with 500 nm ≤ d ≤ 5 microns.

Description

Die Erfindung betrifft ein Leistungshalbleitermodul mit einem Leistungshalbleiterchip und einen Logikhalbleiterchip.The invention relates to a power semiconductor module having a power semiconductor chip and a logic semiconductor chip.

Halbleiterchips, die als Logikhalbleiterchips zusammen mit einem Leistungshalbleiterchip auf einem elektrisch leitenden Substrat wie beispielsweise einem Leadframe angeordnet sind, müssen gegen das Substrat elektrisch isoliert sein. Üblicherweise wird dazu ein elektrisch isolierender Klebstoff eingesetzt, mit dem der Halbleiterchip mit seiner Rückseite auf das Substrat geklebt wird.Semiconductor chips, which are arranged as logic semiconductor chips together with a power semiconductor chip on an electrically conductive substrate such as a leadframe, must be electrically insulated from the substrate. Usually, an electrically insulating adhesive is used with which the semiconductor chip is glued with its back to the substrate.

In der Druckschrift US 2005/0085008 A1 wird ein sehr dünner Wafer, der eine verbesserte Festigkeit aufweist, offenbart. Eine zähe Schicht Armierungsgewebe ist auf einer Rückseite des Wafers aufgelegt, ohne diese Seite zuvor durch herkömmliches Polieren oder Plasmaätzen zu behandeln.In the publication US 2005/0085008 A1 For example, a very thin wafer having improved strength is disclosed. A tough layer of reinforcing fabric is placed on a back side of the wafer without previously treating this side by conventional polishing or plasma etching.

In der Druckschrift US 2005/0227415 A1 ist eine Halbleiter-Komponente offenbart, die eine verdünnte Halbleiterscheibe mit Polymerschutzschichten auf bis zu sechs Oberflächen aufweist. Die Komponente schließt außerdem Kontakthöcker auf dem Chip ein, die auf einer Seite des Schaltkreises in einer Polymerschicht eingebettet sind und ferner Anschlusskontakte auf den Kontakthöckern in einer kompakten Anordnung auf einer Fläche.In the publication US 2005/0227415 A1 discloses a semiconductor device having a thinned wafer with polymer protective layers on up to six surfaces. The component also includes on-chip bumps embedded in a polymer layer on one side of the circuit, and further contacts on the bumps in a compact arrangement on a surface.

In der Druckschrift US 5 965 947 A wird ein Halbleitergehäuse beschrieben, das eine Vielzahl von Halbeiterchips unterschiedlicher Art enthält, wobei einige Chips mit der Chipverbindungsfläche durch ein leitfähiges Klebemittel verbunden sind und andere Chips durch ein nichtleitendes Klebemittel, das stark isolierende Perlen enthält, mit der Chipverbindungsfläche verbunden sind.In the publication US Pat. No. 5,965,947 For example, a semiconductor package including a plurality of semiconductor chips of various kinds, wherein some chips are connected to the chip bonding surface by a conductive adhesive, and other chips are connected to the chip bonding surface by a non-conductive adhesive containing highly insulating beads.

Nachteilig ist dabei, dass das elektrische Isolationsvermögen von Klebstoffen, insbesondere wenn sie gute Wärmeleitungseigenschaften aufweisen sollen, sehr begrenzt ist. Zudem kann bereits ein leichtes Verkippen des Halbleiterchips dazu führen, dass ein elektrischer Kontakt zwischen der Chiprückseite und dem Substrat hergestellt wird. Daher erfordert der Einsatz einer Klebstoffschicht als elektrische Isolation große Präzision beim Aufbringen des Halbleiterchips.The disadvantage here is that the electrical insulation capacity of adhesives, especially if they are to have good heat conduction properties, is very limited. In addition, even a slight tilting of the semiconductor chip can lead to an electrical contact between the chip back side and the substrate being produced. Therefore, the use of an adhesive layer as electrical insulation requires great precision in the application of the semiconductor chip.

Aufgabe der Erfindung ist es daher, ein Leistungshalbleitermodul anzugeben, bei dem ein Logikhalbleiterchip auch beim Auftreten sehr hoher Spannungen elektrisch gegen das Substrat isoliert ist.The object of the invention is therefore to provide a power semiconductor module in which a logic semiconductor chip is electrically isolated from the substrate even when very high voltages occur.

Erfindungsgemäß wird diese Aufgabe mit dem Gegenstand des unabhängigen Patentanspruchs gelöst. Vorteilhafte Weiterbildungen der Erfindung sind Gegenstand der abhängigen Patentansprüche.According to the invention, this object is achieved with the subject matter of the independent patent claim. Advantageous developments of the invention are the subject of the dependent claims.

Ein nicht erfindungsgemäßes Verfahren zur Herstellung von Halbleiterchips weist zumindest folgende Schritte auf: ein Halbleiterwafer mit in Zeilen und Spalten angeordneten Halbleiterchippositionen wird bereitgestellt, wobei der Halbleiterwafer auf seiner Vorderseite Vorderseiten von Halbleiterchips mit integrierten Schaltungen aufweist. Die Rückseite des Halbleiterwafers wird mit einer Parylen aufweisenden Beschichtung überzogen und beschichtet. Anschließend wird der Halbleiterwafer in Halbleiterchips vereinzelt, auf deren Rückseiten die Parylen aufweisende Beschichtung angeordnet ist.A method not according to the invention for producing semiconductor chips has at least the following steps: a semiconductor wafer with semiconductor chip positions arranged in rows and columns is provided, wherein the semiconductor wafer has front sides of semiconductor chips with integrated circuits on its front side. The back side of the semiconductor wafer is coated and coated with a parylene-containing coating. Subsequently, the semiconductor wafer is separated into semiconductor chips, on the back sides of which the parylene-containing coating is arranged.

In einer alternativen Ausgestaltung des nicht erfindungsgemäßen Verfahrens wird der bereitgestellte Halbleiterwafer zuerst auf eine Sägefolie aufgebracht und in Halbleiterchips vereinzelt und anschließend werden die Rückseiten der vereinzelten Halbleiterchips mit der Parylen aufweisenden Beschichtung beschichtet. Die beschichteten Halbleiterchips können danach von der Sägefolie abgenommen werden.In an alternative embodiment of the method not according to the invention, the semiconductor wafer provided is first applied to a sawing foil and separated into semiconductor chips, and then the rear sides of the singulated semiconductor chips are coated with the coating having parylene. The coated semiconductor chips can then be removed from the sawing foil.

Bei dieser Ausgestaltung des Verfahrens können zusätzlich zu den Rückseiten der Halbleiterchips auch ihre Randseiten mit der Parylen aufweisenden Beschichtung versehen werden, so dass die Durchschlagsfestigkeit der Halbleiterchips zusätzlich erhöht wird.In this embodiment of the method, in addition to the rear sides of the semiconductor chips, their edge sides can also be provided with the coating having parylene, so that the dielectric strength of the semiconductor chips is additionally increased.

Dazu wird die Sägefolie vorteilhafterweise vor dem Beschichten gedehnt, so dass Zwischenräume zwischen den Halbleiterchips gebildet werden und die Randseiten der Halbleiterchips frei liegen. Sind die während des Sägens durch den Materialabtrag entstehenden Zwischenräume breit genug, ist das Dehnen der Sägefolie nicht erforderlich.For this purpose, the sawing film is advantageously stretched before coating, so that gaps are formed between the semiconductor chips and the edge sides of the semiconductor chips are exposed. If the gaps created during sawing by the removal of material are wide enough, it is not necessary to stretch the sawing foil.

Es ist eine Überlegung, dass die elektrische Isolation des Halbleiterchips besonders einfach dadurch erreicht werden kann, dass die Rückseite des Halbleiterchips gleich bei seiner Herstellung mit einer elektrischen Isolationsschicht versehen wird. Auf diese Weise wird ausgeschlossen, dass ein Verkippen des Halbleiterchips bei seiner Montage zur Herstellung eines elektrischen Kontakts mit dem Substrat führt. Besondere Präzision beim Aufbringen des Halbleiterchips auf das Substrat ist somit nicht erforderlich, da die elektrische Isolation auch bei einem verkippten Chip noch vorhanden ist.It is a consideration that the electrical isolation of the semiconductor chip can be achieved particularly simply by providing the rear side of the semiconductor chip with an electrical insulation layer as soon as it is produced. In this way, it is precluded that tilting of the semiconductor chip during its mounting leads to the production of an electrical contact with the substrate. Special precision in the application of the semiconductor chip to the substrate is thus not required, since the electrical insulation is still present even with a tilted chip.

Für eine besonders gute elektrische Isolation der Chiprückseite sollten zumindest folgende Bedingungen erfüllt sein: Zum einen sollte das Material, das zur Isolation verwendet wird, eine besonders hohe Durchschlagsfestigkeit aufweisen. Zum andern sollte es mit einer konstanten Dicke in einem einfachen technischen Prozess auf die Rückseite des Halbleiterchips aufbringbar sein. Außerdem ist eine hohe Temperaturbeständigkeit des Isolationsmaterials wünschenswert.For a particularly good electrical insulation of the back of the chip, at least the following conditions should be satisfied: Firstly, the material used for insulation should have a particularly high dielectric strength. On the other hand it should be with a constant thickness in one simple technical process on the back of the semiconductor chip be applied. In addition, a high temperature resistance of the insulating material is desirable.

Parylene erfüllen diese Bedingungen und sind deshalb besonders gut als Isolationsmaterialien geeignet. Sie weisen eine hohe elektrische Isolationsfestigkeit auf, beispielsweise hat eine Schicht von 1 μm Dicke eine elektrische Durchschlagsfestigkeit von 500 V. Zudem nimmt Parylen nur sehr wenig Feuchte auf und ist verhältnismäßig elastisch, so dass es thermomechanische Spannungen zwischen Halbleiterchip und Substrat abpuffern kann. Parylene weisen zudem oft geringe thermische Ausdehnungskoeffizienten von weniger als 50 ppm/K, eine hohe thermische Stabilität und eine hohe chemische Resistenz auf.Parylene meet these conditions and are therefore particularly well suited as insulation materials. They have a high electrical insulation strength, for example, a layer of 1 micron thickness has an electrical breakdown strength of 500 V. In addition, parylene absorbs very little moisture and is relatively elastic, so that it can buffer thermo-mechanical stresses between the semiconductor chip and substrate. In addition, parylene often has low thermal expansion coefficients of less than 50 ppm / K, high thermal stability and high chemical resistance.

Wird die Beschichtung vor dem Sägeprozess zum Auftrennen des Halbleiterwafers aufgebracht, so schützt sie den Wafer während des Sägeprozesses und vermindert das Ausbrechen von Halbleitermaterial an den Kanten, das sogenannte Chipping. Die Beschichtung stellt somit auch eine mechanische Schutzschicht für den Halbleiterwafer bzw. die Halbleiterchips dar. Sie kann darüber hinaus aufgrund ihrer Isolationseigenschaften als ESD(electrostatic discharge)-Schutzschicht dienen und elektrostatische Aufladungen des Halbleiterwafers und der Halbleiterchips während der Prozessierung verhindern.If the coating is applied before the sawing process for separating the semiconductor wafer, it protects the wafer during the sawing process and reduces the breaking away of semiconductor material at the edges, the so-called chipping. The coating thus also represents a mechanical protective layer for the semiconductor wafer or the semiconductor chips. It can also serve as an ESD (electrostatic discharge) protective layer due to its insulating properties and prevent electrostatic charges of the semiconductor wafer and the semiconductor chips during processing.

Die Beschichtung wird vorteilhafterweise mittels Gasphasenpolymerisation durchgeführt mit den folgenden Schritten: Zunächst wird das Dimer der Verbindung verdampft. Die Darstellung des Dimers erfolgt beispielsweise durch dehydrierende pyrolytische Dimerisierung von p-Xylol und anschließendem Abschrecken in flüssigem p-Xylol. Man erhält auf diese Weise [2,2]-p-Cyclophan. Bei der anschließenden Pyrolyse des Dimers spaltet das Dimer in zwei bivalente radikale Monomere wie p-Xylen. Bei der Abscheidung der in der Gasphase vorliegenden Monomere auf den zu beschichtenden Oberflächen findet bei der Abkühlung die Polymerisation statt.The coating is advantageously carried out by gas-phase polymerization with the following steps: First, the dimer of the compound is evaporated. The representation of the dimer takes place for example by dehydrating pyrolytic dimerization of p-xylene and subsequent quenching in liquid p-xylene. This gives [2,2] -p-cyclophane. In the subsequent pyrolysis of the dimer, the dimer cleaves into two bivalent radical monomers such as p-xylene. During the deposition of the monomers present in the gas phase on the surfaces to be coated, the polymerization takes place on cooling.

Durch diesen Prozess lässt sich eine sehr reine Parylen-Beschichtung abscheiden. Die Beschichtung kann somit, abgesehen von unvermeidlichen Verunreinigungen, vollständig oder nahezu vollständig aus Parylen bestehen.This process makes it possible to deposit a very pure parylene coating. Thus, apart from unavoidable impurities, the coating can be wholly or almost entirely parylene.

Die Verdampfung wird vorteilhafterweise bei einer Temperatur von 160°C bis 180°C und einem Druck von 1–2 mbar durchgeführt wird.The evaporation is advantageously carried out at a temperature of 160 ° C to 180 ° C and a pressure of 1-2 mbar.

Die Pyrolyse wird vorteilhafterweise bei einer Temperatur von 660°C bis 690°C und einem Druck von 0,5–1 mbar durchgeführt.The pyrolysis is advantageously carried out at a temperature of 660 ° C to 690 ° C and a pressure of 0.5-1 mbar.

Die Polymerisation findet vorteilhafterweise bei einer Temperatur von weniger als 35°C und einem Druck von 0,1–0,2 mbar statt.The polymerization takes place advantageously at a temperature of less than 35 ° C and a pressure of 0.1-0.2 mbar.

In einer Variante wird vor dem Aufbringen der Parylen aufweisenden Beschichtung mindestens eine Metallschicht auf die Rückseite des Halbleiterwafers oder der Halbleiterchips aufgebracht. Die Metallschichten können dabei Aluminium und/oder Titan und/oder Nickel aufweisen.In a variant, at least one metal layer is applied to the back side of the semiconductor wafer or the semiconductor chips before the application of the parylene-containing coating. The metal layers may have aluminum and / or titanium and / or nickel.

Ein erfindungsgemäßes Halbleiterleistungsmodul weist folgende Merkmale auf: ein Leistungssubstrat, mindestens ein auf dem Leistungssubstrat angeordneten Leistungshalbleiterchip und mindestens einem Logikhalbleiter- oder Treiberchip mit einer aktiven Vorderseite, der mit seiner Rückseite auf das Leistungssubstrat montiert ist, wobei der Logikhalbleiterchip auf seiner Rückseite eine Parylen aufweisende Beschichtung aufweist.A semiconductor power module according to the invention has the following features: a power substrate, at least one power semiconductor chip arranged on the power substrate and at least one active semiconductor chip with an active front side mounted on the power substrate, the logic semiconductor chip having a parylene coating on its back side having.

Das Halbleiterbauteil hat den Vorteil, dass die Rückseite des Logikhalbleiterchips durch die Parylen aufweisende Beschichtung besonders gut elektrisch isoliert ist. Zudem ist die Isolation intrinsisch, das heißt die Beschichtung ist Teil der Chiprückseite und somit nicht von der Art der Montage abhängig oder durch ein Verkippen des Halbleiterchips gefährdet.The semiconductor device has the advantage that the back side of the logic semiconductor chip is particularly well electrically insulated by the coating comprising parylene. In addition, the insulation is intrinsic, that is, the coating is part of the back of the chip and thus not dependent on the type of mounting or endangered by tilting of the semiconductor chip.

Die Parylen aufweisende Beschichtung weist eine Schichtdicke d auf mit 500 nm ≤ d ≤ 5 μm.The parylene-containing coating has a layer thickness d of 500 nm ≦ d ≦ 5 μm.

Für die Parylen aufweisende Beschichtung kann Parylen C, Parylen N oder Parylen D vorgesehen sein. Dabei wird zweckmäßigerweise dasjenige Polymer gewählt, dessen Eigenschaften den Erfordernissen am besten entsprechen. So weist Parylen C einen Schmelzpunkt von 290°C auf und ist sehr widerstandsfähig gegen Wasser und Chemikalien. Parylen N weist einen Schmelzpunkt von 420°C und eine besonders hohe dielektrische Durchschlagsfestigkeit von 7 kV/mm auf. Parylen D hat einen Schmelzpunkt von 380°C und bewahrt seine Festigkeit und seine elektrischen Eigenschaften auch bei hohen Temperaturen.Parylene C, parylene N or parylene D may be provided for the parylene coating. In this case, the polymer is suitably chosen whose properties best meet the requirements. For example, parylene C has a melting point of 290 ° C and is highly resistant to water and chemicals. Parylene N has a melting point of 420 ° C and a particularly high dielectric strength of 7 kV / mm. Parylen D has a melting point of 380 ° C and retains its strength and electrical properties even at high temperatures.

Als Leistungssubstrat ist typischerweise ein Leadframe vorgesehen. Es sind jedoch auch andere Substrate denkbar.The power substrate is typically a leadframe. However, other substrates are conceivable.

Der Logikhalbleiterchip weist auch auf seinen Seitenflächen die Parylen aufweisende Beschichtung auf. Durch das Aufbringen der Beschichtung nicht nur auf den Chiprückseiten, sondern auch auf den Randseiten oder zumindest auf Teilen der Randseiten wie beispielsweise einem unteren Abschnitt der Randseiten ist der Logikhalbleiterchip besonders gut elektrisch gegen das Substrat isoliert. Auch ein Verkippen des Halbleiterchips beim Aufbringen auf das Substrat führt nicht zur Herstellung eines elektrischen Kontakts.The logic semiconductor chip also has on its side surfaces the parylene-containing coating. By applying the coating not only on the chip back sides, but also on the edge sides or at least on parts of the edge sides such as a lower portion of the edge sides of the logic semiconductor chip is particularly well electrically isolated from the substrate. Also, a tilting of the semiconductor chip when applied to the Substrate does not lead to the production of an electrical contact.

In einem Ausführungsbeispiel ist mindestens eine Metallschicht zwischen der Rückseite des Logikhalbleiterchips und der Parylen aufweisenden Beschichtung angeordnet, die beispielsweise Aluminium und/oder Titan und/oder Nickel aufweisen kann.In one embodiment, at least one metal layer is disposed between the back side of the logic semiconductor chip and the parylene-containing coating, which may comprise, for example, aluminum and / or titanium and / or nickel.

Der Logikhalbleiterchip ist vorteilhafterweise mit seiner mit der Parylen aufweisenden Beschichtung versehenen Rückseite über eine Klebstoffschicht mit dem Leistungssubstrat verbunden. Durch Aufkleben kann der Logikhalbleiterchip besonders einfach und dauerhaft mit dem Substrat verbunden sein. Für eine bessere thermische Leitfähigkeit kann die Klebstoffschicht elektrisch leitfähige Partikel aufweisen.The logic semiconductor chip is advantageously connected to its back side provided with the parylene coating via an adhesive layer to the power substrate. By gluing the logic semiconductor chip can be particularly easily and permanently connected to the substrate. For better thermal conductivity, the adhesive layer may comprise electrically conductive particles.

Das nicht erfindungsgemäße Verfahren eignet sich besonders gut zum Aufbringen einer isolierenden Beschichtung auf die Rückseite der Halbleiterchips bereits auf Waferebene. Ein Halbleiterwafer mit einer Vielzahl von in Zeilen und Spalten angeordneten Halbleiterchippositionen weist auf seiner Vorderseite Vorderseiten von Halbleiterchips mit integrierten Schaltungen auf. Auf der Rückseite des Halbleiterwafers ist eine Parylen aufweisende Beschichtung angeordnet.The non-inventive method is particularly well suited for applying an insulating coating on the back of the semiconductor chips already at the wafer level. A semiconductor wafer having a plurality of semiconductor chip positions arranged in rows and columns has on its front side front sides of semiconductor chips with integrated circuits. On the back of the semiconductor wafer, a parylene-containing coating is arranged.

Auch eine oder mehrere Metallschichten zwischen der Rückseite des Halbleiterwafers und der Parylen aufweisenden Beschichtung können bereits auf Waferebene aufgebracht sein und beispielsweise Aluminium und/oder Titan und/oder Nickel aufweisen.Also, one or more metal layers between the back side of the semiconductor wafer and the parylene-containing coating can already be applied at the wafer level and comprise, for example, aluminum and / or titanium and / or nickel.

Ausführungsbeispiele der Erfindung werden im folgenden anhand der beigefügten Figuren näher erläutert.Embodiments of the invention are explained below with reference to the accompanying figures.

1 zeigt schematisch einen Querschnitt durch einen nicht erfindungsgemäßen Halbleiterwafer; 1 schematically shows a cross section through a non-inventive semiconductor wafer;

2 zeigt schematisch einen Querschnitt durch eine alternative Ausgestaltung eines nicht erfindungsgemäßen Halbleiterwafers; 2 shows schematically a cross section through an alternative embodiment of a non-inventive semiconductor wafer;

3 zeigt schematisch einen Querschnitt durch einen in Halbleiterchips aufgetrennten Halbleiterwafer vor einem Abnehmen der beschichteten Halbleiterchips von einer Sägefolie und 3 shows schematically a cross section through a semiconductor wafer separated into semiconductor chips before a removal of the coated semiconductor chips from a sawing foil and

4 zeigt schematisch einen Ausschnitt aus einem nicht erfindungsgemäßen Leistungshalbleitermodul. 4 schematically shows a section of a non-inventive power semiconductor module.

Gleiche Teile sind in allen Figuren mit den gleichen Bezugszeichen versehen.The same parts are provided in all figures with the same reference numerals.

Der Halbleiterwafer 1 gemäß 1 weist eine Vorderseite 3 und eine Rückseite 4 auf. Auf der Vorderseite 3 sind nicht gezeigte Vorderseiten von Halbleiterchips mit integrierten Schaltungen angeordnet. Die Rückseite 4 ist passiv, die weist keine integrierten Schaltungen auf.The semiconductor wafer 1 according to 1 has a front 3 and a back 4 on. On the front side 3 not shown front sides of semiconductor chips are arranged with integrated circuits. The backside 4 is passive, which has no integrated circuits.

Auf der Rückseite 4 des Halbleiterwafers 1 ist eine Parylen aufweisende Beschichtung 2 angeordnet. Die Beschichtung besteht bis auf herstellungsbedingte Verunreinigungen aus Parylen und weist eine Dicke d auf, für die 500 nm ≤ d ≤ 5 μm gilt. Die Beschichtung 2 ist elektrisch isolierend und weist auch bei hohen Spannungen im Bereich von mehreren hundert Volt oder einigen Kilovolt eine ausreichende Durchschlagsfestigkeit auf.On the back side 4 of the semiconductor wafer 1 is a parylene-containing coating 2 arranged. The coating consists of parylene except for production-related impurities and has a thickness d for which 500 nm ≤ d ≤ 5 μm applies. The coating 2 is electrically insulating and has sufficient dielectric strength even at high voltages in the range of several hundred volts or several kilovolts.

2 zeigt eine alternative Ausgestaltung des Wafers 1. Bei dieser Ausgestaltung sind zwischen der Rückseite 4 des Wafers 1 und der Beschichtung 2 eine Metallschicht 5 und eine weitere Metallschicht 6 angeordnet. 2 shows an alternative embodiment of the wafer 1 , In this embodiment, between the back 4 of the wafer 1 and the coating 2 a metal layer 5 and another metal layer 6 arranged.

Zur Herstellung der Beschichtung 2 wird in dieser Ausgestaltung die Gasphasenpolymerisation angewendet, mit der sich auf verhältnismäßig einfache Weise besonders reine und gleichmäßige Beschichtungen erzeugen lassen. Dazu wird der Halbleiterwafer 1 so in eine Vakuumkammer eingebracht, dass seine Vorderseite 3, die die integrierten Schaltungen aufweist, abgedeckt ist, während seine zu beschichtende Rückseite 4 bzw. die Oberflächen von auf der Rückseite 4 angeordneten Metallschichten 5 und 6 freiliegen.For the production of the coating 2 In this embodiment, the gas phase polymerization is applied, which can be produced in a relatively simple manner, particularly pure and uniform coatings. For this purpose, the semiconductor wafer 1 so placed in a vacuum chamber that its front 3 that has the integrated circuits covered while its back side to be coated 4 or the surfaces of on the back 4 arranged metal layers 5 and 6 exposed.

Der Halbleiterwafer 1 wird nach der Beschichtung in Halbleiterchips vereinzelt. Erfindungsgemäß werden zusätzlich zu der Rückseite 4 des Halbleiterwafers 1 auch die Randseiten der Halbleiterchips beschichtet. Dies ist in 3 dargestellt.The semiconductor wafer 1 is separated after coating in semiconductor chips. According to the invention, in addition to the back 4 of the semiconductor wafer 1 also coated the edge sides of the semiconductor chips. This is in 3 shown.

Dazu wird der Halbleiterwafer 1 mit seiner Vorderseite 3 auf die Oberseite 10 einer Sägefolie 9 aufgebracht und in Halbleiterchips 8 vereinzelt. Durch das Auftrennen des Halbleiterwafers 1 in Halbleiterchips 8 entstehen Zwischenräume 11 zwischen den Halbleiterchips 8, die Sägespuren. Somit liegen die Randseiten 7 der Halbleiterchips 8 frei.For this purpose, the semiconductor wafer 1 with his front 3 on top 10 a sawing foil 9 applied and in semiconductor chips 8th sporadically. By separating the semiconductor wafer 1 in semiconductor chips 8th arise gaps 11 between the semiconductor chips 8th , the saw marks. Thus, the margins are 7 the semiconductor chips 8th free.

Der in Halbleiterchips 8 vereinzelte Halbleiterwafer 1 kann nun mit der Beschichtung 2 versehen werden. Dabei verbleiben die Halbleiterchips 8 mit ihren Vorderseiten 12 auf der Oberseite 10 der Sägefolie 9. Die Vorderseiten 12 der Halbleiterchips 8 sind somit geschützt und werden von der Beschichtung 2 freigehalten.The in semiconductor chips 8th isolated semiconductor wafers 1 can now with the coating 2 be provided. In this case, the semiconductor chips remain 8th with their fronts 12 on the top 10 the sawing foil 9 , The fronts 12 the semiconductor chips 8th are thus protected and protected by the coating 2 kept free.

Bei der Gasphasenpolymerisation erfolgt eine Beschichtung nahezu aller freiliegenden Oberflächen in der Vakuumkammer. Somit werden auch die freiliegenden Randseiten 7 mit der Beschichtung 2 versehen. Da das Parylen zumindest als Monomer zunächst in der Gasphase vorliegt, kann es leicht in die Zwischenräume 11 eindringen und setzt sich auf den Randseiten 7 prinzipiell mit der gleichen Dicke d ab wie auf den Rückseiten 13 der Halbleiterchips 8.In gas phase polymerization, coating of almost all exposed surfaces in the vacuum chamber occurs. Thus also the exposed edge sides become 7 with the coating 2 Mistake. Since the parylene, at least as a monomer, is initially in the gas phase, it can easily enter the interstices 11 penetrate and sit on the edge sides 7 in principle with the same thickness d from as on the backs 13 the semiconductor chips 8th ,

Falls nach dem Auftrennen des Halbleiterwafers 1 in Halbleiterchips 8 die Zwischenräume 11 noch nicht groß genug sind, kann die Sägefolie 9 gedehnt werden, um sie zu vergrößern.If after the separation of the semiconductor wafer 1 in semiconductor chips 8th the gaps 11 not big enough, the sawing foil can 9 be stretched to enlarge them.

Nach dem Beschichten der Halbleiterchips können diese von der Sägefolie 9 abgenommen werden. Sie weisen nun eine Beschichtung 2 sowohl auf ihrer Rückseite 13 als auch auf ihren Randseiten 7 auf und sind somit besonders gut elektrisch isoliert.After the semiconductor chips have been coated, they can be removed from the sawing foil 9 be removed. You now have a coating 2 both on her back 13 as well as on their margins 7 on and are thus particularly well electrically isolated.

Das nicht erfindungsgemäße Leistungshalbleitermodul 14 gemäß 4 ist nur schematisch in einem Ausschnitt gezeigt. Das Leistungshalbleitermodul kann beispielsweise eine Brücken- oder Halbbrückenschaltung mit Leistungshalbleiterchips aufweisen. Details der Schaltung sind hier nicht von Interesse und daher nicht dargestellt. In der gezeigten Variante sind auf einem Leistungssubstrat 15 ein erster Leistungstransistor 16 und ein zweiter Leistungstransistor 17 angeordnet. Zur Ansteuerung der Leistungstransistoren ist ein Treiberchip 18 vorgesehen, der ebenfalls auf dem Leistungssubstrat 15 angeordnet ist.The non-inventive power semiconductor module 14 according to 4 is shown only schematically in a section. The power semiconductor module can, for example, have a bridge or half-bridge circuit with power semiconductor chips. Details of the circuit are not of interest here and therefore not shown. In the variant shown are on a power substrate 15 a first power transistor 16 and a second power transistor 17 arranged. To control the power transistors is a driver chip 18 provided, which is also on the power substrate 15 is arranged.

Der Treiberchip 18 weist auf seiner Vorderseite 24 Kontaktflächen 21 auf, die mit den Gateanschlüssen 22 der Leistungstransistoren über Verbindungselemente 23 wie Bonddrähte verbunden sind.The driver chip 18 points to its front 24 contact surfaces 21 on that with the gate connections 22 the power transistors via connecting elements 23 how bonding wires are connected.

Der Treiberchip 18 muss gegen das Leistungssubstrat 15 elektrisch isoliert werden. Er weist dazu auf seiner Rückseite 19 eine Parylenbeschichtung 2 auf. Die Fixierung des Treiberchips 18 auf dem Leistungssubstrat 15 kann beispielsweise über eine nicht gezeigte Klebstoffschicht erfolgen. In dieser Variante ist die Parylenbeschichtung 2 lediglich auf die Rückseite 19 des Treiberchips 18 aufgebracht. Erfindungsgemäß ist sie jedoch zusätzlich auch auf seinen Randseiten 7 angeordnet.The driver chip 18 must be against the power substrate 15 be electrically isolated. He points to this on his back 19 a parylene coating 2 on. The fixation of the driver chip 18 on the power substrate 15 can be done for example via an adhesive layer, not shown. In this variant is the parylene coating 2 only on the back 19 of the driver chip 18 applied. However, according to the invention, it is additionally also on its edge sides 7 arranged.

BezugszeichenlisteLIST OF REFERENCE NUMBERS

11
HalbleiterwaferSemiconductor wafer
22
Beschichtungcoating
33
Vorderseite des HalbleiterwafersFront side of the semiconductor wafer
44
Rückseite des HalbleiterwafersRear side of the semiconductor wafer
55
Metallschichtmetal layer
66
weitere Metallschichtanother metal layer
77
Randseiteedge side
88th
HalbleiterchipSemiconductor chip
99
Sägefoliesawing film
1010
Oberseite der SägefolieTop of the sawing foil
1111
Zwischenraumgap
1212
Vorderseite der HalbleiterchipsFront side of the semiconductor chips
1313
Rückseite der HalbleiterchipsRear side of the semiconductor chips
1414
LeistungshalbleitermodulThe power semiconductor module
1515
Leistungssubstratpower substrate
1616
erster Leistungstransistorfirst power transistor
1717
zweiter Leistungstransistorsecond power transistor
1818
Treiberchipdriver chip
1919
Rückseite des TreiberchipsRear of the driver chip
2020
Oberseite des LeistungssubstratsTop of the power substrate
2121
Kontaktflächecontact area
2222
Gateanschlussgate terminal
2323
Verbindungselementconnecting element
2424
Vorderseite des TreiberchipsFront side of the driver chip
dd
Dickethickness

Claims (10)

Halbleiterleistungsmodul (14) mit folgenden Merkmalen: – einem Leistungssubstrat (15); – mindestens einem auf dem Leistungssubstrat (15) angeordneten Leistungshalbleiterchip (16); – mindestens einem Treiberchip (18) mit einer aktiven Vorderseite (24), der mit seiner Rückseite (19) auf das Leistungssubstrat (15) montiert ist, wobei der Treiberchip (18) auf seiner Rückseite (19) und auf seinen Randseiten (7) eine Parylen-Beschichtung (2) zur elektrischen Isolation gegenüber dem Leistungssubstrat (15) aufweist, wobei die Parylen-Beschichtung (2) eine Schichtdicke d aufweist mit 500 nm ≤ d ≤ 5 μm.Semiconductor power module ( 14 ) having the following characteristics: - a performance substrate ( 15 ); At least one on the power substrate ( 15 ) arranged power semiconductor chip ( 16 ); - at least one driver chip ( 18 ) with an active front side ( 24 ), with its back ( 19 ) on the performance substrate ( 15 ), whereby the driver chip ( 18 ) on its back ( 19 ) and on its margins ( 7 ) a parylene coating ( 2 ) for electrical isolation from the power substrate ( 15 ), wherein the parylene coating ( 2 ) has a layer thickness d with 500 nm ≤ d ≤ 5 microns. Halbleiterleistungsmodul (14) nach Anspruch 1, wobei für die Parylen-Beschichtung (2) Parylen C vorgesehen ist.Semiconductor power module ( 14 ) according to claim 1, wherein for the parylene coating ( 2 ) Parylene C is provided. Halbleiterleistungsmodul (14) nach Anspruch 1, wobei für die Parylen-Beschichtung (2) Parylen N vorgesehen ist.Semiconductor power module ( 14 ) according to claim 1, wherein for the parylene coating ( 2 ) Parylene N is provided. Halbleiterleistungsmodul (14) nach Anspruch 1, wobei für die Parylen-Beschichtung (2) Parylen D vorgesehen ist.Semiconductor power module ( 14 ) according to claim 1, wherein for the parylene coating ( 2 ) Parylen D is provided. Halbleiterleistungsmodul (14) nach einem der Ansprüche 1 bis 4, wobei als Leistungssubstrat (15) ein Leadframe vorgesehen ist.Semiconductor power module ( 14 ) according to one of claims 1 to 4, wherein as a power substrate ( 15 ) a leadframe is provided. Halbleiterleistungsmodul (14) nach einem der Ansprüche 1 bis 5, wobei mindestens eine Metallschicht (5, 6) zwischen der Rückseite (19) des Treiberchips (18) und der Parylen-Beschichtung (2) angeordnet ist.Semiconductor power module ( 14 ) according to one of claims 1 to 5, wherein at least one metal layer ( 5 . 6 ) between the back ( 19 ) of the driver chip ( 18 ) and the parylene coating ( 2 ) is arranged. Halbleiterleistungsmodul (14) nach Anspruch 6, wobei die Metallschichten (5, 6) Aluminium und/oder Titan und/oder Nickel aufweisen.Semiconductor power module ( 14 ) according to claim 6, wherein the metal layers ( 5 . 6 ) Aluminum and / or titanium and / or nickel. Halbleiterleistungsmodul (14) nach einem der Ansprüche 1 bis 7, wobei der Treiberchip (18) mit seiner mit der Parylen-Beschichtung (2) versehenen Rückseite (19) über eine Klebstoffschicht mit dem Leistungssubstrat (15) verbunden ist. Semiconductor power module ( 14 ) according to one of claims 1 to 7, wherein the driver chip ( 18 ) with its with the parylene coating ( 2 ) provided back ( 19 ) via an adhesive layer to the power substrate ( 15 ) connected is. Halbleiterleistungsmodul (14) nach Anspruch 8, wobei die Klebstoffschicht elektrisch leitfähige Partikel aufweist.Semiconductor power module ( 14 ) according to claim 8, wherein the adhesive layer comprises electrically conductive particles. Halbleiterleistungsmodul (14) nach einem der Ansprüche 1 bis 9, wobei die Parylen-Beschichtung (2) vollständig aus Parylen besteht.Semiconductor power module ( 14 ) according to any one of claims 1 to 9, wherein the parylene coating ( 2 ) consists entirely of parylene.
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US5965947A (en) * 1996-08-20 1999-10-12 Samsung Electronics Co., Ltd. Structure of a semiconductor package including chips bonded to die bonding pad with conductive adhesive and chips bonded with non-conductive adhesive containing insulating beads
US20050085008A1 (en) * 2003-10-21 2005-04-21 Derderian James M. Process for strengthening semiconductor substrates following thinning
US20050206010A1 (en) * 2004-03-18 2005-09-22 Noquil Jonathan A Multi-flip chip on lead frame on over molded IC package and method of assembly
US20050227415A1 (en) * 2002-03-06 2005-10-13 Farnworth Warren M Method for fabricating encapsulated semiconductor components

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Publication number Priority date Publication date Assignee Title
US5965947A (en) * 1996-08-20 1999-10-12 Samsung Electronics Co., Ltd. Structure of a semiconductor package including chips bonded to die bonding pad with conductive adhesive and chips bonded with non-conductive adhesive containing insulating beads
US20050227415A1 (en) * 2002-03-06 2005-10-13 Farnworth Warren M Method for fabricating encapsulated semiconductor components
US20050085008A1 (en) * 2003-10-21 2005-04-21 Derderian James M. Process for strengthening semiconductor substrates following thinning
US20050206010A1 (en) * 2004-03-18 2005-09-22 Noquil Jonathan A Multi-flip chip on lead frame on over molded IC package and method of assembly

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