DE102005054081B3 - Data word set outputting unit for e.g. real time system, has address indicator, which is replaced in phase B, in such a manner that indicator is replaced for all age groups that are sequentially processed in phase A - Google Patents

Abstract

The outputting unit has an indicator register unit (ZRE) for outputting a sequentially processed data word, during phase A. A temporary storage unit (ETS) stores the data word under a common ETS-memory address, in such a manner that ETS address indicator indicates the memory address, under which a next data word, which belongs to same age group, is stored. The address indicator is replaced in phase B, in such a manner that the indicator is replaced for all age groups that are sequentially processed in the phase A. The register unit outputs the number of highest age group, during the phase A.

Description

The here described circuit concept of a unit for almost instantaneous, sorted by age group output previously sequentially supplied data word sets is part of a real-time system for safety-critical applications and thus the technical field safety-oriented programmable Assign electronic systems (PES).

Lots Real-time applications can not be done during operation or only interrupt at short notice with unreasonably high effort. As an example here called the control electronics of an aircraft, only on the ground can be switched off. falls in a redundant configuration of PES units during an uninterruptible phase of operation a single unit so adversely affects the associated one Reducing the redundancy the security of the whole system. The Fixing such a failure during operation is however problematic because PESe not easily replaced or new can be started. So can even quickly remediable causes of failure or short-term faults, which put a PES in a faulty state, to a significant longer ongoing impairment to lead the safety. This problem is becoming increasingly important as with growing Integration density the sensitivity of semiconductor devices across from temporarily interferences, such as As electromagnetic waves or alpha particles increases.

This Security issue is often countered by the number used redundant PES units chosen so high Will that be the probability with which within an uninterruptible Operating phase so many units fail, that the operation is not can be maintained below the tolerable marginal risk lies. To the number of this to reduce necessary PESe to a justifiable measure will be their internal processing structures also redundantly designed and so the probability of complete failure of a single PES unit minimized. However, system availability can also be increased by: the PES units of a redundant configuration are designed to that due to transient disturbances in a faulty state PES can be restarted without real-time operation for interrupting to have to. This approach - below with renewed operation during operation - covers all by temporary disorders caused failure modes and allows the replacement of defective PES units at runtime.

The here presented circuit concept, which is almost instantaneous, sorted by age group output previously sequentially supplied data word sets serves, was for a special safety-related PES architecture to support the Newly installed during operation. To the meaning and to illustrate the function of the circuit concept are described in This section below describes how to rebuild real-time systems explained related problems, describes the special features of the associated PES architecture and the process of reassignment explained.

1.1 new in the current Real-time operating

• • durch Vergleich der eigenen Verarbeitungsergebnisse mit denen der redundanten PES-Einheiten Verarbeitungsfehler zu erkennen,
• • im Falle eines Verarbeitungsfehlers aus dem laufenden Betrieb der redundanten Konfiguration auszutreten,
• • nach einem Neustart den internen Zustand der redundanten Einheiten zur Laufzeit zu kopieren, und
• • zu einem Zeitpunkt, an dem Zustandsäquivalenz vorliegt, wieder in den laufenden Betrieb der redundanten Konfiguration einzutreten.

Restarting during operation requires a redundant configuration of several PES units. Every PES unit must be able to

• • detect processing errors by comparing their own processing results with those of the redundant PES units;
• • in the event of a processing error, withdraw from the ongoing operation of the redundant configuration,
• • after a restart, copy the internal state of the redundant units at runtime, and
• • At a time when state equivalency exists, re-enter into the ongoing operation of the redundant configuration.

The Problematic is that while a PES its internal State on the running PES units equalizes, the latter theirs Change state continuously. In many IT systems, such as Hard disk RAIDs, this is a problem the continuous change of state already solved, while during the copy process additional information about current state changes transferred to the replaced component become. RAID controllers use z. For example, the pauses between disk accesses, to copy the data of a replaced hard disk in the background; continuous state changes while of the copying process are considered, by passing writes directly to the replaced hard drive become.

Classification of State Changes in Real-Time Systems: Unfortunately, copying the internal system state at run-time is much more complex in real-time, computationally-oriented computing systems, as they must be able to respond to many, almost simultaneous events. Relative to the trigger, the state changes occurring in the case of computer-aided real-time systems can be taken into account during the copying process must be divided into two categories: program-controlled state changes (PZen) and event-driven state changes (EZen). In order to clarify that the internal state of a PES is determined essentially by the data stored in the memory modules, the term 'data change' is also used below as an alternative to 'state change'.

To count the PZen all data changes that the application software during their execution causes. The associated data volume can be slightly limiting, for example by B. in a given time interval a maximum of a certain number of write memory accesses is allowed. Appropriate compiler directives are easy to implement. The limit to a value that is a continuous transmission the data changes to redundant units, restricts Although the computing power is strong, with modern transmission media are however Computing achievable, the many highly critical Applications are sufficient.

The By contrast, data volumes associated with eCs can not be compared so easy to a maximum Limit value. Since digital systems always work discretely, can several events occur almost simultaneously. In addition, a can single internal or external event - compared to program-controlled Case - one relatively large Number of data changes within a very short time. For example, by a single event basically all computing processes of the application software be activated simultaneously. Will in this case for everyone Arithmetic process stored the activation time, so is one size Number of data changes within a short time Time before. A limitation on the frequency of Write access would here severely limit the minimum achievable response time. The Ability to immediate transmission All information associated with the EZs therefore requires either one for safety-relevant Components unrealistically high bandwidth or limits the achievable computing power to an inadequate level. Therefore must be in one Real-time PES, which is both a practical computing power delivers as well as shortest To guarantee reaction times, a more complex procedure be used to change the internal state of another real-time PES with minimal transmission costs to copy at runtime.

consideration the age of a state information: Upon closer examination of the by EZen evoked data modifications shows that many Data words in approximate be changed at regular intervals. This is u. a. Remember that computing processes of real-time technical applications often called periodically. But also computing processes that be started by external events of a technical process, are very often in approximately equidistant intervals executed. The frequency of changes but can be very different. This characteristic Can be used to transfer costs to minimize or at the same transmission bandwidth better real-time properties (eg higher computing power, shorter guaranteed Response times etc.).

If a data word is changed several times while the state of a PES is being copied, only the last change that occurred during the copying process is of importance. For this reason, it makes sense to organize the transmission of the system state in discrete transmission cycles and to transmit a fixed number n over _Dew oldest data words in each cycle. This means that the state change _{information associated} with a changed data word - consisting of the new value and the address of the data word - are only transmitted if there are fewer than n _overDW data words with older values. This method, in which the oldest data words are transmitted first, reduces the transmission overhead because the number of repeated transmissions of frequently changed data words is reduced.

This 'age-sensitive' transmission technique can be implemented by assigning to each data word whose content can be changed by EZen an age variable indicating the age of the stored information. Each time the value of a data word is changed, the associated age variable is reset to zero. As long as the data word is not changed, the associated age variable is incremented at cyclic intervals. The data words with the oldest stored information thus have the highest age values. In each transmission _cycle , the address and the value of each n _OverDW oldest data words are transmitted. The associated age variables are set to a value that indicates that the associated data word has already been transmitted (eg the maximum representable numerical value). The copying process is completed as soon as the age variables of all data words have this value.

The maximum duration of the copying process depends on the number n _{OverDW of} the 'oldest' data words transmitted in a transmission _cycle and the frequency of data word changes or EZen and PZen. The frequency of Ezen and can PZen from the execution characteristics of the computing processes, inter alia, the maximum execution time t _MaxAusf, the maximum response time t _MAXANT and the minimum activation period t include _MinAkt which eclip be directed. Thus, the maximum duration is determinable.

The circuit concept described here of a unit for virtually delay-free, age-group-sorted output of previously sequentially supplied data word _sets enables particularly efficient determination of the state change _information associated with the n _overDW oldest data words. It is part of a special PES architecture, which is particularly suitable for safety-critical applications and will be explained in the next section.

1.2 Structure and operation of the PES

In This section outlines the key features of the PES architecture described, for the circuit concept presented here was developed.

Computing process processing without asynchronous interruptions: The PES architecture is based on the described below concept of computational processing without asynchronous interruptions.

at This concept is process execution and Administration strictly separated. Process execution (PA) counts exclusively the Processing of application-specific program codes; the process management (PV) is responsible for Process administration and processor allocation.

The Time is divided into discrete, equally long processing intervals, which determine the periodic, synchronous working clock of the PA and the PV. The processing intervals are synchronized with the international one Time standard UTC, i. the processing intervals of redundant PES units begin and end at the same UTC synchronous times.

• • Jeder Prozessabschnitt kann vollständig innerhalb eines Verarbeitungsintervalles ausgeführt werden.
• • Die Ausführung eines Prozessabschnittes ist nicht unterbrechbar.
• • Prozessabschnitte tauschen Daten über den Datenspeicher aus; der Inhalt der Prozessorregister geht am Ende eines Verarbeitungsintervalls verloren.
• • Jeder Prozessabschnitt besitzt einen Identifikator.
• • Die Abschnitte eines Prozesses müssen nicht in einer fest vorgegebenen Reihenfolge ausgeführt werden. Für jeden Prozess speichert die PV einen Abschnittszeiger, der den als nächsten auszuführenden Prozessabschnitt identifiziert.

Processes are composed of a number of process sections that have the following properties:

• • Each process section can be executed completely within one processing interval.
• • The execution of a process section can not be interrupted.
• • Process sections exchange data via the data memory; the contents of the processor registers are lost at the end of a processing interval.
• • Each process section has an identifier.
• • The sections of a process do not have to be executed in a fixed order. For each process, the PV stores a section pointer that identifies the process section to be executed next.

At the beginning of each processing interval, the PV outputs the identifier of the next process section to be executed. This identifier corresponds to the stored section pointer of the process to be executed according to the processor allocation algorithm. The PA reads the identifier and executes the associated section. At the end of the processing interval, when the section has been completed, the PA passes an identifier to the PV. This identifier, which identifies the next section of the process just executed, is stored by the PV as a new section pointer. The flowchart in 1 illustrates this way of working.

If the executed one Section was the last one, i. the associated process has been completely processed the PA signals this to the PV (eg by handover the identifier value 'nil'). In this case the PV causes a state transition, so that the process no longer works in the state 'activated'. simultaneously becomes the end of processing in the determination of the identifier of the next Processing interval to be executed process section considered.

These Operation comes without special synchronization mechanisms, such as z. Semaphore, because every process during a processing interval uninterruptible, exclusive access to the processor has. processes can through the data store communicate with each other without writing the messages To be exposed to interruptions. Mutually exclusive Access to system components can be easily done with the help of variables be implemented in the data store. Similarly, alternating Accesses of several processes can be realized; this is only the program-controlled suspension and continuation of processes necessary. The dispensability of special synchronization mechanisms simplified essential to this PES concept.

Executability of application programs: The mode of operation presented here does not limit the field of application as much as the purely cyclic PES, which due to their particularly simple temporal behavior are still used today in highly safety-critical applications. Without the use of asynchronous interrupts, any program flow paths dependent on the external processes are enabled. As with other computational-oriented real-time systems, this capability requires process-driven program flows, application programs check for timely executability.

This problem has already been solved. The feasibility analysis is simplified if the possibilities of formal verification methods are taken into account when selecting the process state model used for the internal processing of the PV. A model which is particularly suitable for the process _processing concept described here is based on three execution _properties : maximum execution time t _MaxAusf , maximum response time t _MaxAnt and minimum activation period t _MinAct . These parameters allow specifying the time conditions of each hybrid process set consisting of periodic and sporadic computational processes. 2 illustrates the model. It is different from others by the state suppressed.

The minimum activation period corresponds to the minimum amount of time between two process activations; it limits the maximum processor load indirectly. Only a process known in the state can be activated. If the processing of a process is completed before the time t _{MinAkt has expired} , this process is transferred to the state suppressed. Only after expiry of t _MinAkt he is put back into the state known, whereby a re-activation is possible. The suspended state is for synchronization purposes.

All State transitions are under the control of PV. Will the processing of a process completed, so will the transition stop automatically initiated. The transitions will be suspended and continued while performed by the PV, can but only be initiated by an application program. Because the Application programs are run at uninterruptible intervals, find state transitions only held at the end of an interval. Accordingly, a through a process section caused suspension only towards the end of the triggering Interval effective. A process can only suspend itself, but continuing of all other processes. In conjunction with the Periodic operation is thus the realization of predecessor successor relations possible, what for. To implement alternate resource access is absolutely necessary.

It is recommended to implement the state model in the PV so that only one instance can exist for each process at any time. This increases compliance with the IEC 61508 standard, which prohibits the dynamic instantiation of objects in highly safety-related applications (Part 3, Table B1). Considering the restriction to a process _instance , the execution _parameters t _MaxAusf , t _MaxAnt, and t _{MinAct allow} the formal proof of the executability of a set of processes or application programs. Appropriate evidence is described in numerous publications.

implementation the process management: The implementation of the PV is the following procedure. The concept is based on two physically separate units. The process execution unit (PAE) leads the Process sections of the application programs. It essentially consists from a processor without interruption work. The process management unit (PVE), which serves for the process administration and the to be executed Process sections determined by a digital rear derailleur realized.

• • Die Aktivierungsbedingungen eines Prozesses können sowohl auf Zeitplänen basieren als auch asynchrone Meldungssignale mit einbeziehen. Es empfiehlt sich, Aktivierungspläne gemäß dem Verarbeitungskonzept der Echtzeitprogrammiersprache PEARL90 [DIN 66253-2] zu verwenden, da diese besonders allgemein gefasst sind und den Anforderung von Echtzeitsystemen bestens gerecht werden. Sie erlauben, periodische Prozessaktivierungen innerhalb gegebener Zeitfenster direkt zu spezifizieren. Die Syntax eines solchen Aktivierungsplans lautet: AT {clock-expression | [asynchronous-event-expression] + duration1} EVERY duration2 DURING duration3 ACTIVATE name-des-rechenprozesses
• • Die Ausführungseigenschaften umfassen die Parameter t_MaxAusf, t_MaxAnt und t_MinAkt des Prozesszustandsmodells.
• • Die Zustandsinformationen beschreiben den aktuellen Zustand eines Prozesses eindeutig. Hierzu gehört unter anderem der Zeitpunkt der letzten Aktivierung, anhand dessen – in Kombination mit der Ausführungseigenschaft t_MaxAnt – der nächste Fertigstellungstermin bestimmt werden kann. Der den als nächsten auszuführenden Abschnitt eines Prozesses identifizierende Abschnittszeiger gehört ebenfalls zu den Zustandsinformationen.

An integral part of PVE is the process list. In the process list, a parameter set consisting of activation conditions, execution properties and status information is stored for each computing process.

• • The activation conditions of a process can be based on schedules as well as include asynchronous message signals. It is advisable to use activation plans in accordance with the processing concept of the real-time programming language PEARL90 [DIN 66253-2], as these are particularly general and well suited to the requirements of real-time systems. They allow to specify periodic process activations directly within given time windows. The syntax of such an activation plan is: AT {clock-expression | [asynchronous-event-expression] + duration1} EVERY duration2 DURING duration3 ACTIVATE name-of-process
• • The execution _properties include the parameters t _MaxOff , t _MaxAnt and t _{MinAct of} the process state model.
• • The state information clearly describes the current state of a process. Among other things, this includes the time of the last activation, on the basis of which - in combination with the execution _property t _MaxAnt - the next completion date can be determined. The section pointer identifying the next portion of a process to be executed also belongs to the state information.

All computational processes of an application must already be entered in the process list during the configuration of the system; Dynamic instantiation of processes (or objects) is in accordance with the requirements of IEC 61508 for applications of the safety requirement class SIL 4 not allowed. Only the activation conditions of a process can be changed programmatically.

The realization of the PVE is based on a combination of sequential and parallel processing. The algorithms can be structured so that all operations related to a single process are performed in parallel, while the entire process set is processed sequentially. 3 illustrates this way of working. It shows the main components of PVE: process parameter management (PPV) and process state control (PZS).

• 1. Zunächst greift die PPV auf die Prozessliste zu und überträgt die Prozessparameter in dafür vorgesehene Eingangsregister der PZS.
• 2. Dann verarbeitet die PZS die Prozessparameter mit Hilfe einer kombinatorischen Logikschaltung innerhalb eines Taktzyklusses.
• 3. Abschließend liest die PPV die aktualisierten Prozessparameter von der PZS ein und speichert diese in der Prozessliste.

During Sequential Process Administration (SPA), a three-phase process is executed for each process:

• 1. First, the PPV accesses the process list and transfers the process parameters to dedicated input registers of the PZS.
• 2. Then the PZS processes the process parameters using a combinatorial logic circuit within one clock cycle.
• 3. Finally, the PPV reads in the updated process parameters from the PZS and saves them in the process list.

• 1. Überprüfung der Aktivierungsbedingungen,
• 2. Koordinierung von Prozesszustandsübergängen,
• 3. Generierung der aktualisierten Prozessparameter,
• 4. Berechnung der geforderten Antwortzeiten,
• 5. Bestimmung der Prozesse mit der nächsten und der übernächsten Antwortzeit,
• 6. Ausgabe des Identifikators des als nächsten auszuführenden Prozessabschnittes.

The competence of PZS extends to the following tasks:

• 1. checking the activation conditions,
• 2. coordination of process state transitions,
• 3. generation of updated process parameters,
• 4. calculation of the required response times,
• 5. determination of the processes with the next and the next but one response time,
• 6. Output of the identifier of the next process section to be executed.

The first four tasks can for every process carried out separately become. this makes possible their simultaneous processing by a purely combinational digital circuit. The fifth Task requires the response times of all enabled processes to to compare. This is done sequentially with the iterations of the three-phase process made after each iteration the identifiers and required completion dates of the two most urgent processing processes are cached. It will thus not just the process with the next Response time, but also determined with the next but one response time. This is necessary because the SPA is performed while the PAE is a process section performs. Thus it can happen that the processing of the process, the from the SPA as the next completion date is identified, completed in the current processing interval is, i. the PAE led while the SPA is the last part of the process. In this case, since the process with the next but one response time has already been determined, directly, i. without renewing the SPA, the identifier of the next one Processing interval to be executed Section are issued.

1.3 new in the current business

Around To be able to reactivate on the fly, was the previous one Section 1.2 describes the PES architecture around the concept of serial data streams (SDSe) extended. In a redundant configuration of multiple PESs there Each PES issues an SDS, which continuously checks the internal processing is described and forwarded to all redundant PESe. One restarted PES can be done by observing the SDSe of redundant PESe adjust its condition at runtime and get in the running Engage operation. The SDSs are organized in transmission cycles, corresponding to the processing intervals, commence accordingly and end the transmission cycles in sync with the international time standard UTC, as well like the processing intervals.

• • den Inhalt des RAM-Speichers der PAE,
• • den Inhalt der in der PVE gespeicherten Prozessliste,
• • den Inhalt des Registers, in dem der Identifikator des auszuführenden Prozessabschnitts abgelegt ist, und
• • den Inhalt des Registers, in dem der Identifikator des nächsten Prozessabschnitts des zuletzt ausgeführten Rechenprozesses abgelegt ist,

bestimmt. Letzterer wurde gegen Ende des vorangegangenen Intervalls von der PAE an die PVE übergeben. Unter der Voraussetzung, dass ein neu gestartetes PES nur zu Beginn eines Verarbeitungsintervalls in den laufenden Betrieb einer redundanten Konfiguration einsteigen darf und die beiden aufgelisteten Prozessabschnittsidentifikatoren, die nur wenige Datenbits umfassen, am Ende eines jeden Übertragungszyklusses übertragen werden, müssen beim Kopieren des internen Zustandes zur Laufzeit nur der RAM-Speicher der PAE und die Prozessliste der PVE berücksichtigt werden. Die strikte Trennung von Rechenprozessausführung und Rechenprozessverwaltung erleichtert dabei die unterschiedliche Handhabung von programmgesteuerten und ereignisgesteuerten Zustandsänderungen (PZen und EZen), die bereits in Abschnitt 1.1 beschrieben wurde.At the beginning of each processing interval, the state of a PES is completely through

• The contents of the RAM memory of the PAE,
• • the contents of the process list stored in the PVE,
• • the content of the register in which the identifier of the process section to be executed is stored, and
• The content of the register in which the identifier of the next process section of the last executed computation process is stored,

certainly. The latter was handed over to the PVE by the PAE towards the end of the previous interval. Assuming that a restarted PES is allowed to enter the ongoing operation of a redundant configuration only at the beginning of a processing interval and the two listed process section identifiers, which comprise only a few bits of data, are transmitted at the end of each transfer cycle, when copying the internal state to Running only the RAM memory of the PAE and the process list of the PVE be considered. The strict separation of computational process execution and computational process management facilitates the different handling of program-controlled and event-controlled state changes (PZen and EZen), which were already described in section 1.1.

4 illustrates the data transfer via SDS by comparing the context of the data transferred in a cycle in relation to the acti vities of PVE and PAE. The figure shows that one transmission cycle corresponds to one processing interval. As mentioned above, at the end of each cycle, both the identifier of the process section to be executed and the identifier of the next process section of the last executed computing process are transmitted. In addition, at the end of each cycle, a re-entry bit is transmitted; a set re-entry bit is hereinafter referred to as a re-entry signal. Out 4 It can be seen that only part of the actual cycle time can be used to execute a process section, ie the actual execution of the application software.

Copying the RAM memory of the PAE via SDS: The changes made to the application data by the PAE, hereafter referred to as Application Data Modifications (ADM), are always program-controlled (PZ). Therefore, the data volume associated with ADM can be easily limited to a value transferable in the transfer cycle by limiting the number of write accesses allowed in a process section. As in 4 The transmission of the current ADM (or associated state change information) may begin only after the processing of the process section has been completed. (Earlier transmission immediately following the occurrence of the memory accesses is theoretically possible, but results in a more complex temporal behavior and is therefore unsuitable for safety-related systems, which would disproportionately increase the effort of a formal verification - and thus also of a safety certification.).

The The compiler can limit the number of write accesses during the automatic classification of the program code into process sections make. To increase processing efficiency, we recommend for Data that during the execution a process section must be cached only briefly, i. which are no longer relevant after the end of the process section, a special storage area. This memory area of the PAE memory is for the restart does not matter, which is why write accesses to this disregarded can stay. In the following text is with 'PAE memory' or 'data storage' exclusively the Memory area meant for the reissuing is relevant.

In order to completely transfer the data memory of the PAE within a predetermined period of time via SDS, in addition the data words must be transmitted which are not changed within the specified period of time. For this purpose, the entire content of the PAE memory is transmitted in fragmented form via SDS. In each transmission cycle, an SDS transmits a portion of the PAE memory; the entire memory contents are transferred within a fixed number of consecutive cycles. The transmission of a PAE memory section can, as in 4 shown to be performed directly at the beginning of the transfer cycle, in parallel to the PV process performed by Sequential Process Administration (SPA).

So that the SDSe of redundant units are identical, the respectively transmitted PAE memory section is selected in relation to the international time standard UTC. This means that the fragmented transmission of the PAE memory begins with the first segment at UTC synchronous times. These UTC synchronous times occur at equidistant intervals, z. At the beginning of each UTC second. In the following descriptions, n _{cyclesUTC denotes} the number of transmission _cycles between two of these times, and n _parts n the number of data words comprising a portion transferred in one cycle. Ideally, the size of the PAE memory is tuned to n _{cycles UTC} and n _patch size such that the number of data words of the PAE memory corresponds to the multiplication n _cyclesUTC * n _{patch size g} .

Copy PVE process list via SDS: The frequency of changes the parameters of the calculation processes stored in the process list of the PVE - below associated with computational parameter paramifications (RPMs) - depends on the frequency of computing process state changes which is ultimately limited by the execution properties of all computational processes is. RPM can be both programmatic and around event-driven state changes (ie PZen or EZen), which is why the methods described in section 1.1 technology based on the age of the stored values to reduce the transmission costs is used.

The process list of the PVE is organized in data words. Each data word of the process list is assigned a variable which indicates the age of the stored information. The age variables can only take integer values greater than or equal to '0'; the maximum representable numerical value is hereinafter referred to as AV _max . If a data word is changed, the associated age variable is set to the value '0'. As long as an age variable is less than (AV _max - 1), it is incremented by one at the beginning of each processing interval. Thus, the age variables with the highest values (except AV _max ) identify the 'oldest' data words of the process list. The amount of data to be transferred is now limited by a constant number n _U in each transmission cycle _eberDw oldest PVE data words are transmitted and the associated age variables are set to AV _max . If all age variables have the value AV _max , all current RPMs have been transmitted and a reentry signal is transmitted via SDS.

As in 4 shown, the transmission of the oldest RPM, or the associated state change information, can only begin after the conclusion of the SPA, since the data words of the process list can still change during the SPA. The period of time δ _V indicates the time required after the conclusion of the SPA to determine the oldest data words before the transmission can begin.

The transfer All PVE data words are achieved by all age variables Assigned the value '0' at UTC synchronous times becomes. The reference to the international time standard UTC is necessary so that the SDSe of redundant PESs are identical. Regarding one preferably low implementation effort, it is particularly cheap, the same UTC synchronous times to use the fragmented transmission of the PAE memory begins with the first section.

process of re-instalation: in regular operation a redundant configuration of PES units, each PES checks its own processing, by having its own SDS with those of the redundant units compares. A PES considers its own internal processing as faulty once its own SDS by majority vote derived SDS deviates. If a processing error is detected, then occurs the faulty PES from the operation of the redundant configuration and initiates its own reboot. From now on, the SDS is this PES until re-entry into redundant operation as faulty (or invalid) marked.

After the restart of a PES unit, which can be caused not only by detecting a processing error but also by replacing a PES unit, the process of restarting during operation starts. The newly started PES evaluates the SDS of the redundant PESe in order to adjust its internal state. The reassignment process can be divided into two phases, referred to below as Phase I and II. 5 illustrates this.

Phase I begins with the first processing interval after restarting a PES. The phase lasts exactly n _cycleUTC transfer _cycles , ie as many transfer _{cycles as are required in the case of fragmented} transfer of the PAE memory for the complete transfer of the memory contents. Upon completion of Phase I, the ongoing transmission of the current ADM allows to obtain state equality of the PAE memory towards the end of each transmission cycle.

phase II continues until the PVE is also at the end of a processing interval Equality of state achieved. This is the case if at least since the reboot one of the UTC synchronous times, which includes all age variables the value '0' is assigned, has occurred and the sending PESe all current RPMs via Transfer SDS have, over what informs a special reentry signal (The reentry signal is sent by the reentry bit, which is at the end of a every SDS transfer cycle is sent, is set). Occurs a reentry signal within Phase II, the system state alignment is complete, and the restarted PES can begin at the beginning of the next processing interval re-enter the operation of the redundant configuration. Only on condition that at least one of the UTC synchronous Time points to which all age variables are assigned the value '0' since the reboot occurred, guaranteed the appearance of the reentry signal that the contents of the process list Completely was adjusted.

at The system described in section 1.2 is already being used during the SPA a process section executed. Although the arithmetic process carried out in parallel with the SPA can do the same Change the contents of the process list, The changes however, will be first cached in special registers and only in the following Processing interval inserted in the process list. These program-controlled modifications of the process list must be considered become; either by additional effort in determining the oldest RPMs or by only sending out the reentry signal, if the just performed Process section neither suspends a computational process nor the continuation of a suspended computation process still causes execution parameters of Arithmetic processes changed Has.

Optimization of efficiency: The performance data relevant for real-time systems, which can be achieved with the described procedure for re-instalation during operation, are of crucial importance. In addition to the available computing power, this also includes the minimum achievable response time. These performance data not only depend on the available transmission bandwidth, but also on the duration of a transmission cycle and the timescale used to transmit a PAE memory patch, transmit the current ADM and Transmission of the oldest RPMs can be used. The minimum achievable response time depends directly on the cycle time of the system. Therefore, the shortest possible cycle time is desirable.

• • dem Zeitanteil t_SPA zur Durchführung der sequenziellen Prozessadministration,
• • dem Zeitanteil δ_V zur Bestimmung der ältesten RPMen,
• • dem Zeitanteil t_RPM zur Übertragung der ältesten RPMen,
• • dem Zeitanteil t_ADM zur Übertragung der aktuellen ADM,
• • dem Zeitanteil t_IDW zur Übertragung der Identifikatoren des auszuführenden Prozessabschnitts und des nächsten Prozessabschnitts des zuletzt ausgeführten Rechenprozesses sowie des Wiedereinstiegsbits, und aus
• • der Toleranzpause t_Tol

zusammen. Die Toleranzpause t_Tol dient zur Berücksichtigung von Synchronisationsdifferenzen zwischen redundanten PESen. Sie gewährleistet, dass das PES, dessen interne Uhr dem internationalen Zeitstandard UTC am meisten nacheilt, die Übertragung der Prozessidentifikatoren abgeschlossen hat, bevor das PES, dessen interne Uhr dem Zeitstandard am stärksten voreilt, einen neuen Übertragungszyklus beginnt. Um die Toleranzpause t_Tol zu verkürzen, müssen die Synchronisationsgenauigkeiten der internen Uhren der PES erhöht werden.How out 4 As can be seen, this sets itself off

• The time share t _SPA for carrying out the sequential process administration,
• The time fraction δ _V for determining the oldest RPMs,
• The time component t _RPM for transmission of the oldest RPMs,
• The time share t _ADM for transmitting the current ADM,
• The time share t _IDW for transmitting the identifiers of the process section to be executed and the next process section of the last executed computing process and the re-entry bit, and off
• • the tolerance break t _Tol

together. The tolerance interval t _Tol serves to take account of synchronization differences between redundant PESs. It ensures that the PES, whose internal clock lags most at the international time standard UTC, has completed the transmission of the process identifiers before the PES, whose internal clock is most advanced to the time standard, begins a new transmission cycle. In order to shorten the tolerance interval t _Tol , the synchronization accuracies of the internal clocks of the PES must be increased.

In contrast, t _IDW can only be shortened by a higher bandwidth. Since the process section identifiers comprise only a few bits of data, t _{IDW is} negligibly short compared to t _SPA and t _ADM .

t _ADM depends on both the transmission bandwidth and the number of write accesses to the PAE memory allowed in a process section. This number must be logically related to the number of processor instructions that can be executed in a process section. This means that the finer the granularity of the application software subdivided in process sections, ie the shorter the process sections, the lower the number of write accesses permitted in one cycle - and thus the ADM to be transmitted - can be omitted. However, this statement only applies in a first approximation. The longer the process sections, the fewer intermediate results must be placed in the regular PAE memory, since more calculations can be completed completely in one section. Too fine a granularity therefore increases the PAE memory area, which must be taken into account when re-installing during operation, and thus increases the overall transmission costs. With a constant transmission bandwidth, this means that a shortening of the process sections can result in a disproportionately higher number of process sections. That is, a calculation process that was originally divided into 50 sections could be divided into substantially more than 100 sections if the section size was halved. Therefore, when choosing the granularity of the application software, a compromise between the highest possible computing power and the shortest possible cycle time can be found.

The duration t _RPM depends on the number n over _{Dew of} oldest data words of the process list transferred in one cycle. Although this number is freely selectable in principle, it specifies the maximum frequency with which changes to the data stored in the process list may occur so that the occurrence of the situation in which the sending PESs have transmitted all current RPMs via SDS is guaranteed. Thus, the number n over _DW must be _calculated on the basis of the desired performance data of the PES, such. As maximum number of managed computing processes or minimum required response time can be set. However, due to the age-oriented transmission technique, only the (average) frequency of RPM transmissions is critical, not the number n over _{DW of} the RPMs transmitted in one cycle. This means that if the cycle time is halved, then the number n over _DW can also be halved approximately.

The duration t _{PAE slice} depends on the size of the PAE memory _slice transferred in one cycle. This can in principle be reduced down to a single PAE data bit per cycle. This would only increase the duration of Phase I of the relaunch. Since the transmission of the oldest RPMs can only be started after the completion of the SPA, the size of a segment can be chosen such that t _{PAE part} = t _SPA + δ _V.

It can be seen from the above considerations that by minimizing the time components t _SPA , δ _V , t _IDW and t _Tol both the cycle time can be reduced and the computing power of the real-time system can be optimized. The t _Tol tolerance break can only be shortened by equipping the PESs with more accurate UTC synchronized clocks. The time t _IDW , which is required to transmit the identifiers of the process section to be executed and the next process section of the last executed computing process, can only be shortened by a higher bandwidth of the transmission medium. In order to shorten the sequential process administration, ie to minimize t _SPA , a special circuit concept has already been developed. This is referred to as a unit for managing real-time processes without asynchronous sub refractions'.

Further optimizing the performance characteristics of the real-time system is possible by speeding up the determination of the oldest data words, ie by minimizing δ _V.

2 problem

• • die n_UeberDW ältesten Datenwörter der Prozessliste nahezu verzögerungsfrei (d.h. δ_V ≈ 0) bestimmt,
• • sich mit dem in Abschnitt 1.2 beschriebenen Konzept eines sicherheitsgerichteten Echtzeit-PESs effizient vereinen lässt, und
• • mit einem akzeptablen Aufwand realisiert werden kann.

Ideally, the oldest data words of the process list can be accessed immediately after completing the Sequential Process Administration (SPA), ie the first subsequent clock cycle. For this, δ _V = 0 would have to be. However, this delay-free determination of the oldest data words is problematic because changes to the data words in the process list can be made until the end of the SPA. So far, there is no satisfactory concept which

• • the n _overDW oldest data words of the process list are determined almost instantaneously (ie δ _V ≈ 0),
• • Can be efficiently combined with the concept of a safety-oriented real-time PES described in Section 1.2, and
• • can be realized with an acceptable cost.

3 solution

task The present invention is to already have a lot of data words while their sequential deployment by age group and thus already two clock cycles after the provision of the last one Data word whose sequential output sorted by age group to enable. The data words are each paired with a data word assigned to you Age value and synchronous to a clock T provided.

The invention solves the problem described in section 2 by a circuit concept with the features listed in the claims 1 to 3. This circuit concept allows the operation described in the following sections 3.1 and 3.2 and thus provides an acceptable optimum from the achieved delay δ _V and equipment expense.

3.1 Management of age variables

As part of the SPA, the PVE reads all the data words in the process list one after the other, sorted according to computational processes, and sends them to process state control (PZS). The PZS uses the parameter sets of the individual computation processes supplied in this way to determine a new parameter set for each computation process with the aid of a logic circuit. This is then stored again in the process list. 6 illustrates this. In the left part of the figure the PVE is simplified. The controller generates both the control signals and address values necessary for reading the data words from the process list and those subsequently necessary to store the updated data words in the process list. For clarity, in 6 only the control signals that are necessary for understanding.

Hereinafter, the data words of the process list (PL) will be referred to as PL data word; the address under which a PL data word is stored in the PL is called the PL address. The PL stores a parameter set consisting of n _PS PL data words for each of the n _RP- managed computing processes. Accordingly, exactly n _DW = n _RP * n _PS PL data words are stored in the PL.

– 1 annehmen.The management of the age variable is determined by that in the right part of 6 integrated circuit concept integrated. The core of the age variable management unit (EVA) is the age variable memory S _A , which has two separate access interfaces. The address space of this memory block corresponds to that of the memory blocks used to store the PL. For each PL data word, S _A stores an age variable with the word width W _AV , under the associated PL address. Accordingly, the age variables can only be integer positive values in the range 0 to AV _max =

- accept 1.

The control unit transmits only n _PS PL data words to the input register of the PZS before the first updated PL data word is read out again from the output register of the PZS. For this reason, the PL data words transferred to the PZS always hurry in front of the _PS read out of the PZS. This fact is taken into account by the FIFO memory structure S _FIFO , so that value changes of the PL data words can be detected by a simple comparison. The FIFO memory structure S _FIFO has n _PS memory stages. Each time the control unit causes the transmission of a PL data word to the PZS, the transmitted PL data word is also stored in S _FIFO . Each time the control unit initiates the transmission of an updated PL data word from the PZS to the PL, one of the PL data words stored in S _{FIFO is} read out. The thus outputted from S _FIFO PL data word is associated with the PL data word that has just been stored in the PL, ie, the two PL data words belong to one and the same parameter of a Recheuprozesses. Thus it can be determined by a simple comparison logic V ₁ , whether the parameter has been changed. If a change is detected, then the 2-to-1 multiplexer M ₁ is controlled so that it forwards the age value '0', which is constant at its input 1. Otherwise, the multiplexer M ₁ forwards the age value applied to input 0. The multiplexer M ₁ forwards the constant age value '0' applied to input 1 also in the case that the current processing interval is the first one after one of the UTC synchronous times at which the age variables of all PL data words of the process list are set to '0'. should be set. This is caused by an OR gate with two inputs whose output is applied to the control input of the multiplexer M ₁ . At the first input of the OR gate, the output of the comparison logic V _{1 is} connected to the second input a generated by the control unit signal, which assumes the logical value '1' during the first cycle after one of the described UTC synchronous times.

The control unit generated PL address, which is already used to store the PL data words updated by the PZS into the PL, is simultaneously used to read out the age variable associated with the PL data word. The age variable thus read out is fed to a logic circuit L ₁ , which - provided that its value is smaller than (AV _max - 1) - increments by one and forwards it to the input 0 of the 2-to-1 multimplexer M ₁ . Otherwise, ie if the age variable is greater than or equal to (AV _max - 1), L ₁ passes the age variable unchanged to this input of M ₁ . The multiplexer M ₁ optionally passes on the age value output by the logic circuit L ₁ or the constant age value '0'. The output of the multiplexer is connected to the input of the auxiliary register HR ₃ . In addition, the output of the multiplexer M _{1 of} the second access interface of the memory block S _{A is} supplied. As an address value of this access interface is applied by an auxiliary register HR ₁ delayed by half a clock address value, which already serves to read the age variable via the access interface 1.

• • Übertragung der PL-Datenwörter von der PL zum Eingangsregister der PZS Um ein PL-Datenwort von der PL zum Eingangsregister der PZS zu übertragen, gibt das Steuerwerk der PVE zunächst die dem PL-Datenwort zugeordnete PL-Adresse bei einer Taktflanke von T aus. Die PPV nutzt diese PL-Adresse, um auf die PL zuzugreifen, und gibt bei der nächsten Taktflanke von T das zugehörige PL-Datenwort aus. Die PZS nutzt ebenfalls die PL-Adresse, um eine weitere Taktflanke von T später das PL-Datenwort in die zugehörigen Speicherstellen des Eingangsregisters zu übernehmen. Gleichzeitig übernimmt die S_FIFO das PL-Datenwort. Durch die beschriebene Synchronisation anhand der Taktflanken werden Signallaufzeiten berücksichtigt. (Anmerkung: Um mit jedem Taktzyklus ein PL-Datenwort von der PPV an die PZS zu übertragen zu können, wird die PL-Adresse in der PZS für einen halben Taktzyklus zwischengespeichert. Das Steuerwerk braucht beim PL-Datenworttransfer von PPV zu PZS die PL-Adresse somit nur für die Dauer eines Taktzyklusses auszugeben.) Nachdem der Parametersatz eines Rechenprozesses vollständig an das Eingangsregister der PZS übergeben worden ist, bestimmt die PZS den aktualisierten Parametersatz des Rechenprozesses und legt diesen im Ausgangsregister ab. Dies geschieht innerhalb eines Taktzyklusses, so dass nach einer Verzögerung von nur einem Taktzyklus mit der Übertragung des Parametersatzes des nächsten Rechenprozesses begonnen werden kann. Um die Dauer der SPA zu reduzieren, wird das Eingangsregister der PZS bereits mit dem Parametersatz des nächsten Rechenprozesses geladen, während die aktualisierten PL-Datenwörter des vorigen Rechenprozesses aus dem Ausgangsregister der PZS ausgelesen werden.
• • Übertragung der aktualisierten PL-Datenwörter von dem Ausgangsregister der PZS zur PL Um ein aktualisiertes PL-Datenwort vom Ausgangsregister der PZS zur PL zu übertragen, gibt das Steuerwerk der PVE zunächst die dem PL-Datenwort zugeordnete PL-Adresse bei einer Taktflanke von T aus. Diese Taktflanke wird nachfolgend mit T_Fl.a bezeichnet. Die PZS nutzt diese PL-Adresse, um die entsprechenden Datenbits des Ausgangsregisters zu adressieren, und gibt bei der nächsten Taktflanke T_Fl.b das zugehörige PL-Datenwort aus. Die PPV nutzt ebenfalls die PL-Adresse, um eine weitere Taktflanke später (T_Fl.c) schließlich das aktualisierte PL-Datenwort in der zugeordneten Speicherstelle der PL abzulegen. (Anmerkung: Um mit jedem Taktzyklus ein PL-Datenwort von der PZS an die PPV übertragen zu können, wird die PL-Adresse in der PPV für einen halben Taktzyklus zwischengespeichert. Das Steuerwerk braucht beim PL-Datenworttransfer von PZS zu PPV die PL-Adresse somit nur für die Dauer eines Taktzyklusses auszugeben.)

The circuit concept of the EVA is able to determine the current age value of a PL data word during the SPA with a delay of only half a clock cycle. All circuit components of the PVE and the EVA use a common clock signal T. In order to explain the temporal interaction of PVE and EVA, the loading of the input registers and the readout of the output registers of the PZS will first be examined in detail.

• • Transmission of the PL data words from the PL to the input register of the PZS In order to transmit a PL data word from the PL to the input register of the PZS, the control unit of the PVE first outputs the PL address associated with the PL data word at a clock edge of T. The PPV uses this PL address to access the PL and, at the next clock edge of T, outputs the associated PL data word. The PZS also uses the PL address to take a further clock edge of T later the PL data word into the associated memory locations of the input register. At the same time, the S _FIFO takes over the PL data word. Due to the described synchronization based on the clock edges signal propagation times are taken into account. (Note: In order to be able to transfer a PL data word from the PPV to the PZS with each clock cycle, the PL address is temporarily stored in the PZS for half a clock cycle. Thus, the address is only output for the duration of one clock cycle.) After the parameter set of a computation process has been completely transferred to the input register of the PZS, the PZS determines the updated parameter set of the computation process and stores it in the output register. This is done within a clock cycle, so that after a delay of only one clock cycle with the transmission of the parameter set of the next computational process can be started. To reduce the duration of the SPA, the input register of the PZS is already loaded with the parameter set of the next computation process, while the updated PL data words of the previous computation process are read from the output register of the PZS.
• • Transmission of the updated PL data words from the output register of the PZS to the PL In order to transmit an updated PL data word from the output register of the PZS to the PL, the control unit of the PVE first outputs the PL address associated with the PL data word at a clock edge of T. , This clock edge is referred to below as T _Fl.a. The PZS uses this PL address to address the corresponding data bits of the output register and _outputs the associated PL data word at the next clock edge T _Fl.b. The PPV also uses the PL address to eventually place the updated PL data word in the associated memory location of PL one more clock edge later (T _Fl.c ). (Note: In order to be able to transfer a PL data word from the PZS to the PPV with each clock cycle, the PL address in the PPV is buffered for half a clock cycle.The control unit needs the PL address during PL data word transfer from PZS to PPV thus only for the duration of one clock cycle.)

• • Die PL-Adresse wird zur Adressierung des Altersvariablenspeichers S_A verwendet, welcher bei der folgenden Taktflanke T_Fl.b die zugehörige Altersvariable ausgibt.
• • Gleichzeitig wird durch die Taktflanke T_Fl.b die temporäre Speicherung der PL-Adresse in dem Hilfsregister HR₁ veranlasst.
• • Darüber hinaus gibt die FIFO-Speicherstruktur S_FIFO bei der Taktflanke T_Fl.b einen der gespeicherten Werte aus.
• • Anhand des von S_A ausgegebenen Alterswertes, des von S_FIFO ausgegebenen PL-Datenwortes und des vom Ausgangsregister der PZS (ebenfalls bei der Taktflanke T_Fl.b) ausgegebenen PL-Datenwortes bestimmen die Vergleichslogik V₁, die Logikschaltung L₁ und der Multiplexer M₁ einen neuen Alterswert.
• • Dieser wird nun bei der folgenden Taktflanke T_Fl.c in S_A gespeichert, und zwar unter der Adresse, aus der zuvor die ursprüngliche Altersvariable ausgelesen wurde. Hierzu dient die in HR₁ zwischengespeicherte PL-Adresse.
• • Darüber hinaus übernehmen die Hilfsregister HR₃ und HR₂ bei der Taktflanke T_Fl.c den neuen Alterswert bzw. das zugehörige ETS-Datenwort, welches aus den aneinandergefügten Datenbits des PL-Datenwortes und dessen PL-Adresse besteht.

Each time the PVE control unit sends a new PL address to transfer the PL data words updated by the PZS to the PL at the _Clock edge T _Fl.a , the following processing is initiated in the EVA:

• • The PL address is used to address the age variable memory S _A , which _outputs the associated age variable at the following clock edge T _Fl.b.
• At the same time, the temporary storage of the PL address in the auxiliary register HR _{1 is} initiated by the clock edge T _Fl.b.
• In addition, the FIFO memory structure S _{FIFO outputs} one of the stored values at the clock edge T _Fl.b.
• On the basis of the age value output by S _A , the PL data word output by S _FIFO and the PL data word output by the output register of the PZS (also at the clock edge T _Fl.b ), the comparison logic V ₁ , the logic circuit L ₁ and the multiplexer determine M ₁ a new age value.
• • This is now stored at the next clock edge T _Fl.c in S _A , and at the address from which the original age variable was previously read out. The PL address cached in HR ₁ is used for this purpose.
• In addition, the auxiliary registers HR ₃ and HR ₂ take over at the clock edge T _Fl.c the new age _value or the associated ETS data word, which consists of the joined data bits of the PL data word and its PL address.

During the SPA, the auxiliary registers HR ₂ and HR ₃ thus provide the sequentially processed ETS data words and the associated age values. The circuit concept described below processes the data provided sequentially and then outputs the supplied ETS data words sorted by age group, one after the other, almost without delay, ie after completion of the SPA.

In the procedure for copying the PL via SDS described in section 1.1, the age variables whose PL data words are inserted in the SDS must be reset to '0'. This is done with the help of the multiplexer M ₂ and M ₃ . First, these - as described so far - forward the PL address delayed by auxiliary register HR ₁ by half a clock or the address value output at the output of multiplexer M ₁ (phase A). One clock cycle after completion of the SPA, however, the multiplexers M ₂ and M ₃ switch over and pass on the 'read PL addresses' passed on by a unit designated by ETS (EAL) or the age value '0' (phase B).

3.2 Sorting by age group and sequential output

This in 7 The circuit diagram shown sorts the provided ETS data words already during the SPA according to the associated age values and allows the sorted by age classes output a few clock cycles after completion of the SPA. The components of the circuit concept include the pointer register unit (ZRE), the temporary storage unit (ETS) and the ETS readout logic (EAL), which cooperate with each other in a two-phase process. The first phase, hereinafter referred to as phase A, starts exactly one clock cycle after the start of a processing interval (or transfer cycle) of the PES, phase B begins one clock cycle after completion of the SPA (cf. 11 ).

– 1). Die Zuordnung eines Alterswertes zu einer Altersklasse ergibt sich aus den W_AK höherwertigen Binärstellen der Altersvariable. Eine Ausnahme bildet der maximal darstellbare Wert AV_max, der keiner Altersklasse zugeordnet ist. Bei der Umwandlung der Alterswerte in Altersklassennummern wird stets ein zusätzliches Informationsbit generiert; handelt es sich bei dem ursprünglichen Alterswert um AV_max, so wird dieses Bit auf logisch '1' gesetzt; bei allen anderen Alterswerten wird ihm der Wert logisch '0' zugewiesen. Das bedeutet, der Wert AV_max wird schaltungstechnisch berücksichtigt, indem jeder Altersklassennummer ein zusätzliches Informationsbit zugeordnet ist, welches bei ungültigen Altersklassennummern den Wert logisch '1' besitzt.In order to minimize the circuit complexity, the permissible value range of the age variables is divided into n _AK age classes. The number of each age group is represented by W _AK binary digits, ie the class of the most recent age values has the number 0, the class of the oldest age values the number (

- 1). The assignment of an age value to an age group results from the W _AK higher-order binary digits of the age variable. An exception is the maximum representable value AV _max , which is not assigned to any age group. When converting the age values into age-class numbers, an additional informational bit is always generated; if the original age value is AV _max , this bit is set to logical '1'; for all other age values, the value is given a logical '0'. This means that the value AV _max is taken into account in terms of circuitry, in that each age class number is assigned an additional information bit which has the value logical '1' for invalid age class numbers.

To facilitate understanding, this information bit is not dealt with separately in the following explanations. Instead, the age class numbers in the following descriptions and figures are interpreted as a two's complement number which includes W _AK + 1 binary digits. The most significant binary position is formed by the information bit described, the other binary points correspond to the W _AK high-order binary digits of the original age variable. The age value AV _max is thus assigned the age class number '-1' as a two's complement number; for all other ages, the decimal value of the associated two's complement number corresponds to the number of the associated age group.

• • Zeiger-Register-Einheit Die ZRE enthält für jede Altersklasse je einen Registersatz. Jeder Registersatz umfasst je ein Register zur Speicherung eines Aktuellen Adresszeigers (AAZ), eines Vorherigen Adresszeigers (VAZ) und eines Informationsbits Altersklasse Aufgetreten (IAA). Darüber hinaus beinhaltet die ZRE einen ETS-Adresszähler (EAZ). Nachfolgend bezeichnet EAZ den Zählerstand. Der AAZ und der VAZ zeigen jeweils auf eine Adresse der ETS. Das IAA zeigt an, ob die dem Registersatz zugeordnete Altersklasse in der zuvor verarbeiteten Sequenz an Altersvariablen aufgetreten ist. Eine aus Multiplexern bestehende, digitale Logikschaltung bestimmt anhand der IAA aller Registersätze für jeden Registersatz die Nummer der nächst niedrigeren Altersklasse (NNA). NNA zeigt auf die nächst niedrigere Altersklasse, die in der zuvor verarbeiteten Sequenz an Altersvariablen aufgetreten ist. Ist keine niedrigere Altersklasse aufgetreten, so besitzt NNA den Wert '–1'. Dementsprechend ist NNA des Registersatzes der niedriegsten Altersklasse stets '–1', da keine niedrigere Altersklasse existiert. Aus Gründen der Übersichtlichkeit wird in den 7 bis 10 die ZRE ohne die binären Register zur Speicherung der IAA dargestellt. Stattdessen zeigen die Abbildungen die anhand der IAA für jeden Registersatz bestimmte Nummer der nächst niedrigeren Altersklasse (NNA). Anhand der IAA aller Registersätze wird zudem die Nummer der höchsten aufgetretenen Alters klasse (HAA) bestimmt. HAA zeigt bei Abschluss der SPA die höchste Altersklasse an, die in der verarbeiteten Sequenz an Altersvariablen auftrat. In den 7 bis 10 ist HAA in der ZRE dargestellt.
• • Einheit zur temporären Speicherung (ETS) Die ETS besteht im wesentlichen aus zwei Speicherbausteinen mit jeweils zwei voneinander unabhängigen Zugriffsschnittstellen. Über eine Zugriffsschnittstelle kann die ZRE schreibend zugreifen, über die andere die EAL lesend. Die ETS speichert jeweils einen ETS-Adresszeiger und ein ETS-Datenwort unter einer gemeinsamen Adresse – bezeichnet mit ETS-Speicheradresse – ab. Die Größe des Adressbereichs der ETS entspricht wenigstens der Größe des Adressbereichs der PL plus der Anzahl an Altersklassen minus eins (n_DW + n_AK – 1).
• • ETS-Ausleselogik (EAL) Die ETS-Ausleselogik liest die in der ETS temporär gespeicherten ETS-Datenworte nach Altersklassen sortiert aus. Die am Ausgang bereit gestellten Daten können direkt in den SDS zur Übertragung der ältesten RPM eingefügt werden.

To describe the operation of the circuit concept comprehensible, the essential characteristics of the above-mentioned circuit components are described below. The structure of the components will be described in detail later in Section 5.1.

• • Pointer register unit The ZRE contains a register file for each age group. Each register set includes one register each for storing a current address pointer (AAZ), a previous address pointer (VAZ), and an age-related occurrence (IAA) information bit. In addition, the ZRE includes an ETS address counter (EAZ). Subsequently, EAZ refers to the meter reading. The AAZ and the VAZ each point to an address of the ETS. The IAA indicates whether the age group associated with the register set has occurred in the previously processed sequence of age variables. A multiplexer digital logic circuit determines the number of the next lower age group (NNA) for each register set based on the IAA of all register sets. NNA points to the next lower age group that occurred in the previously processed sequence of age variables. If no lower age group has occurred, NNA has the value '-1'. Accordingly, NNA of the lowest age register set is always '-1' because there is no lower age group. For the sake of clarity, in the 7 to 10 the ZRE is represented without the binary registers storing the IAA. Instead, the figures show the number of the next lower age group (NNA) determined for each register set by the IAA. Based on the IAA of all register records, the number of the highest age group (HAA) has also been determined. At the conclusion of the SPA, HAA indicates the highest age group that appeared in the processed sequence of age variables. In the 7 to 10 HAA is represented in the ZRE.
• • Temporary Storage Unit (ETS) The ETS consists essentially of two memory modules, each with two independent access interfaces. The ZRE can write access via one access interface, while reading the EAL via the other. The ETS stores in each case an ETS address pointer and an ETS data word at a common address - denoted by ETS memory address. The size of the address range of the ETS corresponds at least to the size of the address range of the PL plus the number of age groups minus one (n _DW + n _AK -1).
• • ETS readout logic (EAL) The ETS readout logic reads the ETS data words temporarily stored in the ETS sorted by age group. The data provided at the output can be inserted directly into the SDS for transmission of the oldest RPM.

Phase A: At the beginning of phase A, ie at the beginning of each processing interval (or transmission interval), the AAZ of each register set of the ZRE is initialized with the number of the age group associated with the register set and the IAAs are reset to logical '0'. The latter results in the value '-1' for both the NAA of each register set and the HAA. At the same time, the EAZ is set to the number of the highest age group incremented by one (n _AK + 1). This situation is in 7 illustrated. In the figure, the contents of all memory elements whose initial values are irrelevant for further processing and therefore are not initialized at the beginning of phase A are indicated by insignificant (unb.). In addition, the figure assumes a simplification of a division into 6 age categories; In terms of circuitry, it is better if the number of age groups is a power of two.

In Phase A, the ZRE and the ETS operate as follows. As in section 3.1, the EVA will always put at their outputs during the SPA the currently processed ETS data word and the associated age value ready. A combinatorial logic circuit determines from the age value immediately the age class number. This age class number serves to select the register set, its current AAZ with the help of a Multiplexer to the output ETS memory address passed becomes. The EAZ is also issued by the ZRE on the Output ETS address pointer.

With the next Clock edge, i. half a clock cycle after the current ETS data word provided by the EVA will be in the selected register set the ZRE the current AAZ as new VAZ and the current EAZ as new AAZ taken over. About that In addition, the IAA will be selected Register set set. Because the registers store AAZ, VAZ and IAA have a delayed output behavior, the changes are however, only another half clock cycle later at their outputs effective. In addition, the EAZ will be incremented by one at this point.

Parallel to this processing, i. also half a clock cycle after the current ETS data word provided by the EVA, the ETS stores at the address to which the ETS memory address issued by the ZRE points, the current ETS data word and the ETS address pointer output by the ZRE.

The 8th and 9 illustrate the operation of ZRE and ETS in phase A by showing the register contents in the stepwise processing of the ETS data word sequence {DW A, DW B, DW C, DW D, DW E, DW F}. In the example, the age sequence of the processed sequence of ETS data words is the sequence and age class sennummer {3, 1, 1, 4, 3, 1}, ie only the age groups 1, 3 and 4 occur. In this case, the NNA of the register set associated with the age group 5, after completion of phase A, points to the age group 4 and the NNA of the register set associated with the age group 4 to the age of 2. After the ETS data word F is processed HAA has the value 4. There are a total of 6 age groups.

Phase B: One clock cycle after the SPA has been completed, ie one clock cycle after the last PL data word has been provided by the EVA, to phase B, where the last ETS address pointers stored in the ETS are replaced. For this purpose, starting with the register set indexed by HAA, all the register sets of the ZRE whose age class has occurred in the previously processed sequence of ETS data words are processed successively in decreasing order. In each case, the memory cell of ETS is addressed with the stored VAZ whose ETS pointer value is replaced by the value of NNA. 10 shows the changes to the ETS pointers that are in the 8th and 9 shown example. In the example, it is assumed that the PL contains only 6 data words in total; In a real technical implementation, the PL stores significantly more data words.

Already one clock cycle after the start of phase B, the EAL can read out the ETS data words stored in the ETS in succession - sorted by age group, starting with the highest (oldest) age group. For this purpose, the EAL accesses the stored data via the respective second access interface of the two memory modules of the ETS. The number of the highest occurring age group (HAA) identifies the address of one of the oldest ETS data words, ie an ETS data word of the highest age group. This address is read out first. The read-out ETS data word, which is composed of a PL data word and its PL address, can be added directly to the SDS. The read ETS address pointer is used to address the next read access to the memory blocks of the ETS. Accordingly, the EAL at the in 10 example shown, the ETS data words in the order D, A, E, B, C, F read and add to the SDS.

In Phase B is replaced by replacing the ETS address pointers in the ETS stored ETS data words almost connected to a chain. The EAL must with the read out of the ETS, however, do not wait for the replacement to complete. Since with the beginning of phase A on with each Taktzylus an ETS address pointer replaced, but the EAL only one clock cycle after the beginning of Phase B begins to read an ETS data word with each clock cycle always ensured any necessary replacement has already been carried out is before the EAL on the associated Address accesses.

4 Achieved benefits

By means of the features set _forth in claims 1 to 3, the invention minimizes the delay δ _V which results in the determination of the n _overDW oldest data words following the SPA in conventional methods before the output sorted by age classes can begin. As discussed in Section 1.3, minimizing δ _V can optimize the performance of the real-time system. The remaining delay δ _V is less than three processing cycles. Since this value - compared to the traditional software-based sorting method - can be regarded as negligible, in the name of the invention, the formulation 'almost delay-free' was chosen.

5 embodiment

in the Below is an embodiment of the Invention closer described.

5.1 Structure of the circuit components

After this in the previous section the operation of the circuit concept is described in detail in this section on the Circuit design of the Pointer Register Unit (ZRE), the unit for temporary storage (ETS) and the ETS readout logic (EAL).

5.1.1 Control signals

To make the following explanations as understandable as possible, some control signals are first explained. The orientations of the control signals mentioned here (logical '1' / '0', positive / negative clock edge) refer to the following descriptions; the circuitry implementation of the control signals can also work inverted. The control signals are usually provided by the control unit of the PVE, but in part also generated by the using circuit parts themselves. 11 illustrates the following descriptions.

All circuit components use the common clock signal T. As the beginning of a clock cycle, the positive clock edge of T is considered. The beginning of a processing interval falls always with a positive clock edge of T together.

The pulse signal S _{Interval start} signals the beginning of a processing _interval (or transmission cycle). How out 11 As can be seen, it is logic '1' in the first clock cycle of a processing interval, otherwise '0'. In contrast, the pulse signal S _{SPAabgeschlossen} signals that the SPA has just been completed. It is logical '1' in the first clock cycle after completion of the SPA. Since the SPA is started at the beginning of a processing interval, the EVA provides the first ETS data word and the corresponding age value after only a few clock cycles. The other ETS data words and age values are output in the following clock cycles. The signal S _{New data word} , which is generated by the control unit of the PVE, signals that a new ETS data word was provided by the EVA at the beginning of the current clock cycle. In the first clock cycle after provision of a new ETS data word, it has the value logical '1', otherwise '0'. As 11 shows, a new ETS data word does not have to be provided with every new clock cycle. The output of a new ETS data word always coincides with a positive clock edge of T.

5.1.2 Pointer Register unit

12 shows the circuitry of the Pointer Register Unit (ZRE). The essential circuit components include the ETS address counter (EAZ), the conversion logic (K ₁ ), the cascaded register sets 0 to (n _AK -1), the output multiplexer (M ₇ ) and the replacement logic (EL).

The ETS address counter: The ETS address counter (EAZ) consists of a common digital counter circuit. The counter has at least as many binary digits that it can represent the numerical range from n _AK to (n _DW + n _AK - 1) dual. If the input signal S beginning of _interval at a negative clock edge of T is logic '1', the counter is set to the value n _AK , regardless of the input signal S _{New data word} . If, on a negative clock edge of T, the S _{new data word} signal is logic '1' and S _{interval start} logic '0', the counter is incremented by one. If the count was changed on a negative clock edge of T, the new counter reading will not be output until the next positive clock edge of T (delayed output behavior).

The output meter reading has the format of an ETS address pointer. An ETS address pointer consists of the actual address value and an information bit which has the value logical '0' only for valid address pointers. An ETS address pointer is valid if the associated address value indicates an existing memory address of the ETS. The address value comprises at least W _EAW = ⌈ log ₂ (n _DW + n _AK -1) ⌉ binary digits. In order to make the explanations as clear as possible, the information bit in the following text is not treated separately. Instead, the ETS address pointers in the following text are construed as a two's complement with W _EAW + 1 binary digits. The most significant binary position is formed by the information bit, the other binary points correspond to the W _EAW higher-order binary digits of the address value, ie the actual address value and the information bit are merged to a two's complement number. Invalid ETS address pointers are thus affected by negative address values, e.g. B. '-1' represented.

The Conversion Logic: The conversion logic (K ₁ ) converts the age values passed from the EVA to the ZRE into age class numbers. As described in section 3.2, the age class numbers are represented by a two's complement number with W _AK + 1 binary digits. When converting the age values 0 to (AV _max - 1), the respective age class number is formed from the W _AK most significant binary digits of the dual coded age value plus a leading binary '0'. The age value AV _max is transferred to the age class number '-1', ie all binary digits of the two's complement number are set to logical '1'.

• • eine Zugriffslogik Z_i,
• • je ein Register zur Speicherung eines Aktuellen Adresszeigers (AAZ_i), eines Vorherigen Adresszeigers (VAZ_i) und eines Informationsbits Altersklasse Aufgetreten (IAA_i)
• • sowie drei Multiplexer M_4.i, M_5.i und M_6.i.

The cascaded register sets: The ZRE has one register set for each of the n _AK age groups. Each register set is assigned an age class number i, where 0 ≤ i ≤ (n _AK -1). In the following text as well as in 12 is written instead of (n _AK - 1) simplified n. The essential components of a register file i belong

• An access logic Z _i ,
• • one register each for storing a current address pointer (AAZ _i ), a previous address pointer (VAZ _i ) and an information bit age group Occurrence (IAA _i )
• • as well as three multiplexers M _4.i , M _5.i and M _6.i.

The access logic Z _i includes a combinatorial logic for checking two age class numbers for equivalence. This logic is supplied both the age class number output by the conversion logic K ₁ and the age class number i of the register set. If equal, the logic outputs the value logical '1'; otherwise, its output signal is logic '0'. This binary signal is logically _ANDed with the signal S _NewDataWord before it is passed to the output of the access logic. The binary output signal of the access logic Z _i is thus only logical '1' if the age value transmitted by the EVA to the ZRE belongs to the age group assigned to the register set and at the same time the pulse signal S _{new data word is} logical '1'.

The registers AAZ _i , VAZ _i and IAA _i each have four inputs and one output with the names data input (DE), data output (DA), store (Sp), default value (VW) and reset (R). If Sp has the value logical '1' during a negative clock edge of T, the register adopts the value applied to DE. If R is set to logical '1' during a negative clock edge of T, the register assumes the value applied to VW in any case, ie even if logic '1' is also applied to Sp. If the register contents of AAZ _i , VAZ _i or IAA _{i are changed} on a negative clock edge of T, the new content will not be output until the next positive clock edge of T at output DA (delayed output behavior).

The register AAZ _i is used to store ETS address pointers and therefore includes W _EAW binary digits (An additional information bit indicating the validity of the ETS address value does not have to be stored since the values transferred are always valid.). At its input VW, the age group number i associated with the register set is connected, and at the input R the signal S _Interval beginning. Accordingly, at the beginning of each processing _interval , all registers AAZ _{i are set} to the respective assigned age class number i. EAZ is present at the input DE and the binary output signal of the access logic Z _{i is} connected to the input Sp. Consequently, at the time of a negative clock edge of T, the register AAZ _i adopts the EAZ, if at this time the age value _transmitted by the EVA to the ZRE belongs to the age group assigned to the register set i and S _{new data word has} the value logical '1'.

The register VAZ _i is also used to store ETS address values and therefore also includes W _EAW binary digits (An additional information bit that indicates the validity of the ETS address value does not have to be stored since the values transferred are always valid.). Since the register contents at the beginning of the interval are irrelevant for further processing, input VW is in 12 For the sake of better clarity, it is not connected and logic '0' is permanently applied to the input R. At the input DE, the output DA of AAZ _{i is applied} and to the input Sp, the binary output signal of the access logic Z _{i is} connected. Consequently, at the time of a negative clock edge of T, register VAZ _i adopts the value output by AAZ _i , if at this time the age value _transmitted by the EVA to the ZRE belongs to the age group associated with register set i and S _{new data word has} the value logical '1' ,

The binary information stored in register IAA _i indicates whether new values have already been stored in the registers AAZ _i and VAZ _i of register set i in the current processing interval since the reset to the default value, ie whether the age group assigned to the register set is in the sequence processed so far has already occurred on ETS file words. To the register input VW is permanent logic '0' applied to the input R signal S is connected _{interval start.} Accordingly, at the beginning of each processing interval, all registers IAA _{i are} reset to logic '0'. Logically '1' is permanently applied to the input DE and the binary output signal of the access logic Z _{i is} connected to the input Sp. Consequently, the register IAA _{i is set} to the logical '1' value at the time of a negative clock edge of T if at this time the age value passed from the EVA to the ZRE belongs to the age group associated with the register set i and S _{new data word} is logical '1 owns.

The 2-to-1 multiplexer M _4.i is controlled so that its input A is forwarded during phase A and its input B during phase B. During phase A, it passes the output DA of AAZ _i to the input I _{i of} the output multiplexer M ₇ , while phase B passes the output DA of VAZ _i .

The output DA of the register IAA _{i is} connected to the control input of the 2-to-1 multiplexer M _6.i of each register set i. If the output DA of IAA _{i is} logic '1', M _{6.i forwards} the age class number associated with the register set in the format of an ETS address _pointer . In the other case, the multiplexer M _{6.i forwards} the signal present at its input 0. _Regarding the register _{sets of} the age groups 1 to (n _AK -1), the output signal of the multiplexer M _4.i-1 , which belongs to the register set with the next lower age class number, is connected to input 0 of the multiplexer M _6.i. With the register set of age group 0, the age class number '-1' in the format of an ETS address pointer is applied to input 0 of the multiplexer M _6.0 . As previously described, this two's complement value indicates an invalid ETS address pointer.

This cascaded interconnection of the multiplexer M _6.i causes each of the input 0 of the multiplexer M _6.i the number of the next lower age group (NNA _i ) is present. NNA _{i of} the register file _i always indicates the next lower age group that has occurred in the previously processed sequence of age values since the beginning of the interval. In addition, this cascaded connection causes the number of the highest age group (HAA) that has occurred at the output of the multiplexer M _{6.n of} the register set of the highest age group (n _AK -1) to be tapped. The HAA is handed over by the ZRE to the EAL. It should be noted that the transferred HAA is only valid after completion of the SPA and therefore only during phase B.

For each register set, the value applied to the input 0 of the multiplexer M _6.i is likewise transferred to one of the two inputs of the multiplexer M _5.i , so that the NNA _i can be forwarded by the multiplexer M _5.i. The 2-to-1 multiplexer M _5.i is controlled so that its input A is forwarded during phase A and its input B during phase B. During phase A, it passes the EAZ to the input II _{i of} the output multiplexer M ₇ , while phase B forwards the number of the NNA.

The output multiplexer: The output multiplexer M ₇ has n _AK + 1 input pairs each consisting of an input I _i and an input II _i . Each input pair is assigned an age class number i, where -1 ≤ i ≤ n = (n _AK -1). The control input has the format of an age class number, ie a number in two's complement representation in the number range -1 ≦ i ≦ n is applied to it. The output multiplexer always forwards the two inputs of the input pair to its two outputs I and II, whose associated age class number corresponds to the value applied to the control input s.

The outputs of the multiplexers M _4.i and M _{5.i are} connected to the _{input pairs} with the age class _numbers 0 to n, in such a way that the output of the multiplexer M _{4.i is} connected to the input I _i of M ₇ and the output of M _{5.i is} connected to the input II _i of M ₇ . At the input II _{-1 of} the output multiplexer M ₇ permanently the value '-1' is applied in the format of an ETS address pointer, which indicates an invalid ETS address value. As in 12 As can be seen, input I _-1 of M _{7 is} also the value '-1' in the format of an ETS address pointer.

To the control input s of the output multiplexer M ₇ , the output of the 2-to-1 multiplexer M _{9 is} connected. This multiplexer is controlled so that during phase A it passes the age class number output by the conversion logic K ₁ and, during phase B, the output DA of the replacement register ER to the control input s of M ₇ .

The Replacement Logic The Replacement Logic (EL) coordinates the replacement of the ETS address pointers described in Section 3.2, effectively connecting the ETS data words stored in the ETS into a chain. The core of the EL is the replacement register ER. During the process of replacing the ETS address pointer read out of the register sets NNA _i are stored in the replacement register ER for one clock cycle.

The Substitution register ER stores age class numbers in the number range -1 ≤ i ≤ n, i. the invalid age class number '-1', recognizable by the logical value '1' of the associated information bit, can also be stored, It has four inputs and an output with the names Data input (DE), Data output (DA), Save (Sp), default value (VW) and reset (R). Owns Sp during one negative clock edge of T the value logical '1', so takes over the register the value attached to DE. Is R during a negative clock edge set to logical '1', so takes over the register in each case, i. even if logically '1' is also applied to Sp, the one adjacent to VW Value. If the register contents on a negative clock edge of T changed, so the new content is not until the next positive clock edge of T output at output DA (delayed output behavior).

At input VW of ER the constant value '-1' (equivalent invalid age class number) is connected, at the input R the signal S _{Interval start} , accordingly at the beginning of each processing _interval in ER the age class number '-1' is stored. The input Sp is constantly set to logic '1'. Thus, ER takes over the value present at the input DE at every negative clock edge of T, provided that at the input R logic '1' is not present at this time as well.

The output DA of ER is connected to one input of the 2-to-1 multiplexer M ₉ . In addition, the output DA is connected to a logic circuit which compares the output value with the age class number provided by the conversion logic K _{1 and} forwards the larger of the two values to the multiplexer M ₈ . M ₈ forwards this value during phase A to the input DE of ER. This wiring ensures that during phase A in ER the number of the highest age group in the previously processed sequence of age values is always stored. In the first clock cycle after the start of Phase B, the _retirement class number output by ER at the output DA corresponds to the HAA present at the output of M _4.n during the entire phase B.

During phase B, the multiplexer M ₉ forwards the ER class retirement age number to the control input of M ₇ . At the same time, the multiplexer M ₈ forwards the NNA _i read out via output II of the output multiplexer M ₇ to the input DE of ER. First, however, the NNA must be converted _i in the format of an age class number (two's with the word width W _AK + 1) because the NNA read out via M ₇ have the format of ETS-address pointers (two's with the word width W _EAW + 1) _i. Through this wiring of M ₉ and M ₁₀ , the NNAs _{i of} all the register sets whose age class in the previously processed sequence become ETS-Da In the first clock cycle after the start of phase B, the NNA of the register record of the highest age group occurring has been output at output II of M ₇ . This is taken over by ER and output in the second clock cycle after the beginning of phase B. Consequently, in this clock cycle at the output II of M _7, the NNA of the register set of the second highest age group occurred. This is in turn taken over by ER and output in the third clock cycle after the beginning of phase B, whereupon at output II of M ₇ the next lower NNA is output. This processing continues until the NNA register set of the lowest encountered age group is output at the output of M II. ₇ Since this value has the value '-1' and the value '-1' is constant at the input II _-1 of M ₇ , the system subsequently stops at the output II of M ₇ when outputting '-1', ie in the replacement register ER henceforth the value '-1' is stored.

While the NNA of the selected register set is output in phase B at the output II of the output multiplexer M ₇ , the stored VAZ of the same register set is always output at output I. The two values output by M ₇ are forwarded to the ETS in order to address with the VAZ the ETS memory cell whose ETS address pointer is replaced by the NNA.

5.1.3 Unit for temporary storage (ETS)

Essentially, the ETS consists of two memory modules S _B and S _C. Both memory modules each have two independent access interfaces. In both memory modules via an interface - hereinafter referred to as interface A - exclusively writing and the other interface - hereinafter referred to as interface B - read only read.

Interface A is in 13 represented with the three inputs DE, Adr and S. If the value logical '1' is present at input S during a negative clock edge of T, then the value present at input DE is stored below the address present at input Adr. Interface B is shown with the output DA and the two inputs Adr and L. If the value logical '1' is present at the input L during a positive clock edge of T, then the value stored below the address present at the input Adr is output at the output DA.

In memory block S _B , the ETS data words transmitted by the EVA are stored. Accordingly, the output of the auxiliary register HR _{2 of} the EVA is connected to its input DE. Memory block S _C stores the ETS address pointers transferred by the ZRE. Accordingly, the output DA of the output multiplexer M _{7 of} the ZRE is connected to its input DA. In the case of both memory components, the ETS memory address transferred from the ZRE is applied to the address input of interface A, ie the input Adr is respectively connected to the output I of the output multiplexer M _{7 of} the ZRE. At the input S of the interface A of the memory module S _B is during phase A, the value of logic '1' and during phase B, the value of logic '0'. At the input S of the interface A of the memory module S _C , the value is logical '1', if the transferred from the ZRE ETS memory address - which has the format of an ETS address pointer - is valid, otherwise the value is logical '0' , This is in 13 represented by a comparison logic that outputs only the value logical '1' when the encoded as a two's complement ETS memory address is greater '-1'.

In the case of both memory modules, input L of interface A has the value logic '1' if the ETS read address applied to input Adr - which has the format of an ETS address pointer - is valid, otherwise the value is logic '0'. Accordingly, as long as the ETS read address provided by the EAL is valid, it is updated every positive clock edge of the value output at the output DA. The value output by memory block S _B is transferred as ETS data word, the value output by memory block S _C is transferred to the EAL as ETS address pointer.

5.1.4 ETS read-out logic (EAL)

The in 13 The structure of the EAL shown is greatly simplified and shows only the components necessary for understanding. In order to add the sequentially read ETS data words, or their constituents PL data word and PL address, as described in section 1.3, to a serial data stream (SDS), a slight additional effort is necessary (inter alia parallel-serial conversion). Since this additional effort is not important for the present patent application, its illustration has been omitted for clarity.

The delay register VR ₁ delays the signal _pulse with which S SPA completes signals completion of the SPA by one clock cycle. With the delayed signal pulse, which begins at the beginning of phase B and ends two clock edges later, the multiplexer M _{11 is} driven. During the pulse, this multiplexer forwards the HAA passed on by the ZRE to the auxiliary register HR ₄ ; in the other case, it forwards the ETS address pointer transferred by the ETS. The auxiliary register HR ₄ , which is designed to store ETS address pointers, takes over with each negative Clock edge of T the applied value and outputs it directly.

Accordingly, at the first negative clock edge after the start of phase B, the register adopts the value of HAA and transfers this to the ETS as a new ETS read address. For all other negative clock edges, HR ₄ adopts the ETS address pointer transferred by the ETS and returns it as a new ETS read address to the ETS.

On in this way, the ETS data words stored in the ETS become Age groups sorted sequentially. The read out ETS data words will be afterwards again divided into PL address and PL data word. The PL addresses, together with the associated PL data words inserted in the SDS will be handed over to the EVA. The EVA uses the PL addresses to return the associated age variables to '0' to put.

5.1.5 Interaction of ZRE, ETS and EAL

In summary The interaction of ZRE, ETS and EAL can be described as follows.

interaction by ZRE and ETS: during Phase A passes the ZRE to the ETS as ETS memory address always the AAZ of the register set, whose age group belongs to that of the EVA provided age value. At the same time, the current meter reading of the EAZ as ETS address pointer. These transfer values are available to disposal, when the EVA on a positive clock edge of T a new ETS data word along with the associated Age value, i. to have to only signal transit times taken into account become. Accordingly, the ETS may already be negative at the next Cycle edge the current ETS data word together with the transferred ETS address pointer at the handed over Save ETS memory address. Take on this negative clock edge the registers of the ZRE indicate the respective values at their inputs and the ETS address counter becomes incremented; the new register contents and the new EAZ counter reading but only at the subsequent positive clock edge output.

During phase B passes the ZRE to the ETS as ETS memory address successively the VAZ all the register records, their age group has occurred in the previously processed sequence of ETS data words is. At the same time, the corresponding NNA is always used as the ETS address pointer handed over to the ETS. With At the beginning of each clock cycle, a new VAZ and its associated NNA are transferred. Accordingly, the ETS can pass on each negative clock edge ETS address pointer under the transferred Save ETS memory address - provided the ETS memory address is valid, i.e. bigger or equals zero. The VAZ is in the order of decreasing age groups output sequentially: in the first clock cycle after the beginning of phase B Both the VAZ and the NNA of the Register set become the highest occurred Age group handed over to the ETS, in the second clock cycle, the VAZ and the NNA of the register set become the second highest occurred Pass age group etc. After the VAZ and NNA of all the records of past age groups have been issued, passes the ZRE constant as ETS memory address the value '-1' to the ETS. This will be the ETS indicated that all necessary substitutions have been made and no further ETS address pointers are stored until the end of phase B. (or replaced).

Interaction of ETS and EAL The EAL already starts to read the ETS data words stored in the ETS half a clock cycle after the start of phase B. At the first negative clock edge after the beginning of phase B, the EAL passes the HAA as ETS read address to the ETS. On the subsequent positive clock edge of T, the ETS outputs the ETS data word stored under this address and the ETS address pointer. At the next negative clock edge of T, the EAL evaluates the transferred ETS data word and returns the ETS address pointer as a new ETS read address to the ETS. This in turn outputs the next ETS data word and the next ETS address pointer on the next positive clock edge of T. This processing, in which a new ETS data word is read out at each positive clock edge of T, is continued until the ETS transfers the value '-1' as an ETS address pointer to the EAL. This invalid ETS address value signals that the last of the ETS data words whose age value is smaller than AV _max has been read out. On the next positive clock edge, the EAL transfers the invalid ETS read address '-1'. Consequently, from then on, no further ETS data word and no further ETS address pointer are read out.

Claims (3)

Circuit technology realized unit for virtually delay-free, sorted by age groups output previously sequentially supplied data word sets, - which an amount of data words, each paired with a data word associated age value - synchronously provided to a clock T, already during the phase of the sequential Provisioning by age sorted and already two clock cycles after the last data word along with the associated age value has provided its age-grouped, sequential output, wherein - the provided data words are hereinafter referred to as ETS data words, - the phase of sequential provision, which begins with the provision of the first ETS data word and one clock cycle after provision of the the last ETS data word ends, hereinafter referred to as phase A, - the subsequent phase, which begins one clock cycle after the last ETS data word has been provided and in which the ETS data words are sorted by age group sequentially, is referred to below as phase B. - the age value assigned to each ETS word is dual-coded and has the decimal range 0 to AV _max , - with the exception of the maximum representable age value AV _max , the value range of the provided age values is divided into n _AK age classes for the purpose of minimizing the circuit complexity, the N each age group is represented by a binary number with W _AK binary digits and the assignment of an age value to an age group results from the W _AK higher-order binary digits of the age value, and - the maximum representable age value AV _{max represents} a special case that is not assigned to any age group and in which the associated ETS data word is not inserted in the sorted by age classes, sequential output sequence, characterized in that a) during phase A, each of the sequentially provided ETS data words together with a respective assigned ETS address pointer, one of - followed by Pointer Register Unit (ZRE) circuit part is stored in a - hereinafter referred to as a temporary storage unit (ETS) - circuit part is stored under a common, transmitted from the ZRE ETS memory address, in such a way that - assigned to an ETS data word ETS address pointer points to the ETS memory address of the ETS at which the next ETS data word belonging to the same age group is stored, and - in each case the decimal value of the address under which the first ETS data word of an age group in the B) During Phase B, for all the age groups that occurred in the amount of age values sequentially processed during Phase A, the ETS address pointers are replaced, along with the most recently processed ETS data word of an age group have been stored under a common address in the ETS, such that - beginning in the first clock cycle of phase B, an ETS address pointer is replaced with each clock cycle until, for each age group, the number of times sequentially processed during phase A Age values occurred, an ETS address pointer was replaced, - the ETS address pointers are sorted by age groups, where the ETS address pointer of the last processed ETS data word of the highest occurring age group is first replaced, and then the respective ETS address pointer of the ETS data word of an age group last stored in the ETS points to the first stored ETS data word of the next lower occurring age class (c) the CEA during phase B issues the number of the highest age group that occurred in the quantity of age values processed sequentially during phase A - hereafter referred to as the highest age group (HAA) -, d) a - hereinafter referred to as ETS Readout logic (EAL) - already in the second clock cycle after the beginning of phase B can begin to read the ETS data words stored in the ETS and ETS address pointers sorted by age groups, starting with an ETS data word of the highest age group such that - in each clock cycle an ETS data word together with the assigned ETS address pointer is read out, - the ETS address pointer read out in one clock cycle is used to address the memory address of the ETS to be read in the next clock cycle, and - the HAA output by the ZRE is extended by binary zeroes, if necessary to adapt the word width - to Addressing of the first to be read memory cell of the ETS is used. Circuit technology realized unit for virtually delay-free, sorted by age groups output previously sequentially supplied data word sets according to claim 1, which has a special, hereinafter referred to with pointer register unit (ZRE) for sorting by age groups, characterized in that a) this derailleur a - hereafter referred to as the ETS address counter (EAZ), which is set at the beginning of phase A to the number of the highest age group incremented by one and at exactly one clock cycle after a new ETS data word has been provided, its output count incremented by one, b) the switching mechanism for each of the n _AK age groups includes a register set, - each register set a dual-coded age class number i is assigned in the value range 0 <i <(n _AK - 1), - each register set i one register for Storage of a current address pointer (A AZ _i ), a Previous Address Pointer (VAZ _i ) and an Information Age Age Group (IAA _i ), and At the beginning of phase A the IAA registers of all register sets are reset to logic '0' and the AAZ registers of all register sets with the number i of the age group associated with the respective register set are initialized, c) the AAZ registers, the VAZ registers and the IAA registers of all register sets have a delayed output behavior, in such a way that the registers can adopt a new value only in the course of a clock cycle, but this newly stored value is output only at the beginning of the next clock cycle, d) each register set i a 2 is assigned to 1-multiplexer _circuit M _4.i, which is controlled by the binary output value of the IAA register such that in the register records of the age groups 1 to (n _AK - 1) - for the output value logical '1' the number i the age group associated with the register set, and - at the output value logical '0', the output value of the 2-to-1 multiplexer _circuit M _{4.i-1 of} the register set d it is forwarded to the next lower age group (i-1) and in the register set of age group 0 - at the output value logical '1' the number of the age group assigned to the register set and - at the output value logical '0' a value is forwarded, which recognizes none e) during Phase A during the first clock cycle after providing a new ETS data word in the register set of the age group belonging to the age value provided at the same time, - the AAZ register accepts the current count of the EAZ, the VAZ register accepts the value currently being output from the AAZ register, and - the IAA register is set to logic '1', but the three registers output the new values at their outputs only at the beginning of the next clock cycle, f) the from the 2-to-1 multiplexer _circuit M _{4.n AK-1} which is assigned to the register set of the highest age class, We passed on g) the derailleur includes a register for storing age class numbers, hereinafter referred to as a replacement register (ER), which is initialized at the beginning of phase A with a value that is not identifiable as a valid age class number and that has a delayed output behavior, such that the register can acquire a new value only in the course of a clock cycle, but this newly stored value is not output until the beginning of the next clock cycle, h) the ER - during phase A always in the first clock cycle, after a new ETS data word has been provided, the number of the age group to which the provided age value belongs, if this age group includes higher age values than the age group indexed by the number currently stored in the ER, or it is the value ni currently stored in the ER In the course of each clock cycle, phase B assumes the value currently transferred as ETS address pointer to the ETS, possibly reduced to the corresponding number of binary digits, if the decimal value of this dual-coded ETS address pointer otherwise, in ER, a value is stored which obviously does not correspond to a valid age class number; i) the values passed from the ZRE to the ETS as the ETS memory address are selected by combinatorial logic such that during phase A - in the case that the currently applied age value is not the maximum age value AV _max , the output value of the AAZ register corresponding to the register record whose associated age group includes the currently attached age value is always output as the ETS memory address , and in the case that the a If the age value in question is the maximum age value ΔV _max , the ETS memory address is a value which is obviously not equal to any existing address of the ETS, and during phase B - if the value output by the ER is a valid one Retirement class number, when ETS memory address is always output the output value of the VAZ register belonging to the register set of the retirement class number issued by the ER and, in the case that the value issued by the ER is not a valid retirement class number, than J) the values passed from the ZRE to the ETS as ETS address pointers are selected by a combinatorial logic, such that during phase A, the value is always output to the ETS memory address Counter reading of the EAZ is output as ETS address pointer and during phase B - in the case that it is because of ER value output by a valid age class number in the range 1 to n _AK -1, when the ETS address pointer is always the output value of the 2-to-1 multiplexer _circuit M _4.i , which is decremented by the register set of 1, from the ER belongs in the case where the value output by the ER is the valid retirement class number 0, a value is output as the ETS address pointer which can not be identified from any existing address of the age group ETS corresponds, and - in the event that the value issued by the ER is not a valid retirement age number, the ETS address pointer is a value that is obviously not equal to an existing ETS address. Circuit technology realized unit for virtually delay-free, sorted by age groups output previously sequentially supplied data word sets according to claims 1 and 2, for temporary storage of the ETS data words a special, hereinafter referred to as a temporary storage unit (ETS) circuit part has, characterized in that a ) the ETS contains two independently writable memory units, each having two independent access interfaces, b) in one memory unit - hereinafter referred to as memory unit S _B - the provided ETS data words are stored and in the other memory unit - subsequently with memory unit S _C designates - the ETS address pointers transferred by the ZRE, c) in each case via one of the two interfaces of the memory units S _B and S _C - hereinafter referred to as interface A - only write and via the respective and e) read-only access is made, d) in both memory modules to the address input of the interface A, the ZRE passed ETS memory address is created, e) during phase A always in the first clock cycle after a new ETS Data word has been made available in memory module S _B this is fed via the interface A ETS data word, f) each time it at the - during a clock cycle constant - from the ZRE to the ETS transferred ETS memory address to A valid address of the ETS is stored in memory module S _C at the interface A during this clock cycle constantly applied ETS address pointer, g) in memory module S _C and the values transmitted by the ZRE as ETS address pointer values are stored, the recognizable no existing Address of the ETS correspond h) in both memory modules to the address input of the interface B d ie the two memory chips are read out at the same time, and j) the ETS address pointers read out of memory module S _C during phase B either in each case to the address of the ETS to be read out next indicates or points to the end of the sorted by age groups sequence of ETS data words by the read value recognizably corresponds to any existing address of the ETS.