DE102004062994A1 - Semiconductor component with semiconductor chip and flip-chip contacts, including flat pattern on reverse side of chip to allow precise orientation of chip with wiring substrate surfaces - Google Patents

Abstract

In a semiconductor (SC) component comprising a housing (1) and an SC chip (2) with flip-chip contacts (3) arranged on its active upper side (4) and located on contact connecting surfaces (5) of the upper side (6) of a wiring substrate (7), the underside (8) of which has external contact surfaces with external contacts (9) of the SC component (10), in electrical contact with surfaces (5), the reverse side (11) of the chip has a flat pattern (12) with boundary edges (13) in a predetermined geometric orientation relative to the arrangement of flip-chip contacts on the active upper side. An independent claim is included for the production of the SC components by: producing an SC wafer with SC chip positions, integrated circuits and contact surfaces for flip-chip contacts (3) in a predetermined arrangement on its active side (4); applying the flat pattern (12) to the reverse side (11) of the wafer in the SC chip positions; applying the flip-chip contacts to the contact surfaces in the SC chip positions; separating the wafer into SC chips (2) with flip-chip contacts; preparing a wiring substrate (7) with SC component positions and appropriately arranged contact connection surfaces (5); applying the chips to the wiring substrate in the SC component positions, while orienting the flip-chip contacts (3) relative to the contact connection surfaces (5) utilizing the flat pattern (12); bonding the flip-chip contacts to the contact connection surfaces; and packing the SC component positions in a plastics housing mass (17), while embedding the SC chips (2).

Description

The The invention relates to a semiconductor device with a semiconductor chip with flip-chip contacts and a method for its manufacture. The flip-chip contacts are for this purpose on the active upper side of the semiconductor chip are arranged and surface mounted on a wiring substrate on respective contact pads of the wiring substrate positioned and over these contact pads electrically connected to the wiring substrate. The flipchip contacts and the corresponding ones Contact pads on the wiring substrate are thus from the semiconductor chip covered, so that the assignment of the flip-chip contacts of the semiconductor chip to the contact pads of the wiring substrate can not be reliably performed unless smooth and exact margins of the semiconductor chip as reference quantities for disposal stand.

aggravating Therefore, sawing techniques affect not completely a semiconductor wafer when singulated to semiconductor chips cut through, but connecting webs of minimum thickness between have the semiconductor chips, which break through when singulated be created so that frayed back margins on the an assignment of the flip-chip contacts to the contact pads not clearly possible is. This is the result of singulating the semiconductor chips from a semiconductor wafer so-called "chipchipping" complicates the assignment process of semiconductor devices with semiconductor chips and flip-chip contacts and increase that Risk of default in the production of such semiconductor devices.

A further uncertainty lies in the sawing process itself. The course the sawing, the over the entire semiconductor wafers are introduced in a lattice structure, can across from the planned offset or oblique have been introduced. Again this error can lead to a complete failure lead individual semiconductor devices.

From the publication US 6,278,293 B1 For example, a method and structure for fabricating semiconductor devices is known, wherein the method includes providing a semiconductor chip and a substrate, and wherein the semiconductor chip and the substrate are aligned with each other. For this purpose, the semiconductor chip has a semiconductor chip marking for aligning on a first side of the semiconductor chip, wherein this marking corresponds to the semiconductor chip contact areas on a second side of the semiconductor chip. The substrate has at least one alignment mark on a first side of the substrate, wherein the alignment mark of the substrate corresponds to substrate contact areas of the first side of the substrate, and wherein the mark on the semiconductor chips additionally has identification information.

This known methods and the known structure have the disadvantage that in addition to the mark on a semiconductor chip also the substrate one Alignment mark outside of the cover area must have by the semiconductor chip to a ensure correct assignment between the semiconductor chip and the substrate. Also offers there is no solution for semiconductor chips with frayed edges on the backs on, but goes from smooth edges of the semiconductor chip.

task The invention is the reliability to increase component production and qualitatively better and more reliable semiconductor devices to create at a reduced cost.

Is solved this object with the subject of the independent claims. Advantageous developments The invention will become apparent from the dependent claims.

According to the invention is a Semiconductor component with a housing and provided with a semiconductor chip, wherein the semiconductor chip has an array of flip-chip contacts on its active top. These flip-chip contacts are on contact pads of the Top of a wiring substrate arranged. The wiring substrate faces on its upper side with contact pads opposite bottom outer contact surfaces with external contacts of the semiconductor device. The external contact surfaces are with the contact pads electrically connected. According to the invention, the back of the semiconductor chip a planar Pattern on whose boundary edges a predetermined geometric assignment to the assignment of the flip-chip contacts on the active top.

This semiconductor device has the advantage that the association between a semiconductor chip with flip-chip contacts and an arrangement of contact pads on the top side of the wiring substrate can be performed with high precision, so that misalignments and manufacturing failures are minimized in this semiconductor device. Another advantage is that the planar pattern on the back of the semiconductor chip avoids aligning the semiconductor chips to the wiring substrate by means of the sawn edges of the semiconductor chips. The alignment can thus be carried out independently of the structure and the accuracy of the edges of the semiconductor chip. Thus, it is also permissible Use semiconductor chips whose edges have a so-called "chip chipping", which arises because of safety reasons, the semiconductor wafer is not completely cut through in its total thickness when singulated to semiconductor chips, but a connecting web of a few microns thickness between the semiconductor chips remains until a singling can be carried out.

By the solution according to the invention is the Disadvantage that now no more smooth edges to adjust for disposal stand, overcome. Instead of the sawn and relatively inaccurate edges now a precise one flat Pattern having defined edge structures, the arrangement the flip-chip contacts on the opposite corresponding active side. Because the flat pattern on the backs the semiconductor chip are arranged, is practically the entire area for the Forming such surface Patterns available. Thus, as a flat Pattern for a square semiconductor chip can also be inserted into a square. The margins this square reflect the edges of the square semiconductor chip and their arrangement corresponds the arrangement of flip-chip contacts, and is independent of the arrangement of the saw marks or from frayed edges of the semiconductor chip.

One further offering flat Pattern is a rectangle for rectangular semiconductor chips. Again, replace the edges of the flat Pattern the non-exact edges of the semiconductor chip and leave an exact positioning and alignment to the contact surfaces of the wiring substrate. It can be helpful if one of the corners of the rectangle or the square slightly bevelled or is phased to the alignment of the semiconductor chip or its Make flip-chip contacts visible and traceable without them they themselves are visible.

Instead of a square can also be a registered flat pattern in the form of a Circle on the back of the semiconductor chip are applied. Such a circle can to illustrate the orientation of the flip-chip contacts on one Side parallel to one of the edges be flattened. This flat Pattern has the advantage that the circular edge is very accurate on the back a semiconductor wafer in the semiconductor chip positions or on a back a semiconductor chip can be applied, whereby the alignment of the semiconductor chip is no longer dependent on the frayed edges.

In a further preferred embodiment the invention has the flat Pattern an oval. This oval is intended for rectangular semiconductor chips, and extends with its longitudinal axis along the long side the semiconductor chips and with its transverse axis it is in direction the transverse side of the semiconductor chip aligned. Again, it is possible to have one Additional marking of the oval to understand the alignment.

A another possibility a flat Applying a pattern is a star on the back of the semiconductor chip photolithographically applied. The multi-beam However, the star should be radially symmetrical to to ensure the reference to the assignment of the flip-chip contacts.

Also a flat Pattern in the form of a sun pattern with corresponding symbolic sunbeams or the replica of a compass rose with the corresponding eight arrows in the different main directions ensures a clear assignment of areal Pattern and its edges to the arrangement of the flip-chip contacts on the opposite active top of the semiconductor device. It can by omitting one of the beams enhances the alignment and mapping even further become.

In Further preferred embodiments of Invention are planar Arrow pattern or a cross provided, wherein the area pattern may also include crossed arrow patterns. With a flat pattern from a cross or from a crossed arrow pattern can the Main orientations of flipchip contacts are marked, again the edges this pattern is a measure of the assignment and alignment of the flip-chip contacts.

One Method for producing a semiconductor device with a housing and with a semiconductor chip having an array of flip-chip contacts on its active top and on its back a flat Pattern whose boundary edges a predetermined geometric assignment to the arrangement of flip-chip contacts on the active top have, has the following method steps.

First, a wafer is manufactured with semiconductor chip positions and with integrated circuits, wherein the integrated circuits are provided with contact surfaces for flip-chip contacts in a predetermined arrangement on the active top of the semiconductor wafer. Flat patterns in the semiconductor chip positions are applied to the back side of the semiconductor wafer, the boundary edges of which have a predetermined geometric assignment of the arrangement of the contact surfaces on the active top side. The application of areal patterns to the back of the semiconductor wafer may be anticipated or even after the structuring of the active top side of the semiconductor wafer in the semiconductor chip positions. Thereafter, flip-chip contacts in the semiconductor chip positions are applied to corresponding contact surfaces. Subsequently, the semiconductor wafer is split into semiconductor chips with flip-chip contacts.

Independent of the production of a suitable semiconductor chip or a plurality of suitable semiconductor chips For example, a wiring substrate may be made. there For example, the wiring substrate may have a plurality of semiconductor device positions. in those contact pads are arranged. The arrangement of the contact pads in the semiconductor device positions corresponds to the arrangement of the flip-chip contacts the semiconductor chips. Be on such a prepared wiring substrate then the semiconductor chips in the semiconductor device positions below Aligning the flip chip contacts of the semiconductor chips to the device the contact pads of the wiring substrate with the help of the flat patterns on the backsides the semiconductor chips applied.

After that can the thus aligned flip-chip contacts of the semiconductor chips the contact pads of the wiring substrate. After bonding will be the semiconductor device positions in a plastic housing composition under Embedding the semiconductor chips packaged. In this case, the semiconductor chips in the semiconductor device positions are provided with individual housing or in a common housing for many Embedded semiconductor chip positions. In the latter case closes separating the wiring substrate with a plurality of semiconductor device positions to individual semiconductor devices. In the other case, the finished semiconductor devices punched out of the wiring substrate become.

This Method has the advantage that with high precision semiconductor chips with Flipchip contacts on a wiring substrate with corresponding Contact pads for the Flipchip contacts can be positioned and bonded without in this positioning the edges and the precision the edges of the semiconductor chip are crucial. Thus, with this method, semiconductor chips precise on the contact pads be applied to the wiring substrate in which the edges frayed are.

To is preferably when dividing the semiconductor wafer into semiconductor chips a sawing technique used, which does not complete the semiconductor wafer along the planned Traces of separation severed, but at the depth of the saw grooves less than the thickness of the semiconductor wafer, so that a few microns thin connecting webs of silicon between the semiconductor chips or the semiconductor chip positions of the semiconductor wafer persist. This sawing technique has the advantage that the saw blades a higher Have life as they are not in an adhesive film or a plastic film or an adhesive mass in the separation of the semiconductor wafer in Must penetrate semiconductor chips. The saw blades become with their sensitive diamond tips thus not plastic or adhesive masses and retain their Sä sharpness for a longer life at.

With a preferred embodiment of the Method, the application of planar patterns by means of photolithography technique. This will be first on the back a photosensitive polyamide layer is applied to the semiconductor wafer, the following is structured by photolithography. This procedure has the advantage that the polyamide layer without much effort after alignment either removed or as an adhesion layer to the Housing plastic compound serve can.

A another possibility a flat Pattern on the back of the semiconductor wafer in each of the semiconductor device positions, is the flat Apply pattern using stencil printing technique. The stencil printing technique requires that in a corresponding template openings are present, through which a structuring by means of a coating agent can be done. In this case, the environment of the flat pattern does not become painted, but the pattern itself receives a varnish layer.

One another possibility a flat Pattern on the back of the semiconductor wafer precisely apply, consists in a jet printing technique analogous to the inkjet printing technique for printing on paper. Again, the jet printing technique is now developed so far that precise margins of the plane Pattern can be formed which in turn is a measure and an assignment to the arrangement of the flip-chip contacts on the opposite side allow the semiconductor chip.

In Another variant of the method, the flip-chip contacts on the semiconductor wafer not before the order NEN of the semiconductor wafer applied in semiconductor chips, but after the separation. For this Variant, it is advantageous that the few micrometers thin connecting webs between the semiconductor chips for it make sure that is accurate Arrangement of flip-chip contacts on the entire surface of the Semiconductor wafer possible is, especially a shift or a twisting of the individual semiconductor chips is excluded due to the connecting a few microns thin webs.

In a further embodiment The invention for separating the semiconductor chips are the above mentioned Connecting webs broken, with irregularly frayed boundary edges of the backs the isolated semiconductor chips arise. This process variant has the advantage that for breaking the connecting webs no special Preparations are to be made but that with the conventional ones Singling devices in which a stylus against the back in each of the semiconductor device positions is already pressed sufficient to the few microns thin webs and thus the cohesion of the already marked Break wafers. The disadvantage of irregular or frayed edges the semiconductor chips, which then no longer for adjusting the semiconductor chips in relation to contact pads of a wiring substrate are suitable, by the inventive flat pattern on the backs of the semiconductor chip compensated.

In summary It should be noted that by the exemplary photomasking according to the invention the wafer backs e.g. with a Photoimid the Diebonder on the basis of this flat pattern can orient. This photomask becomes relative to the active front side aligned. A staggered sawing and / or a backside chipping influenced in the inventions to the invention semiconductor device with the associated Process the recognition and placement accuracy of Diebonders no more.

The The invention will now be described with reference to the accompanying figures.

1 shows a schematic perspective view of a semiconductor device of a first embodiment of the invention;

2 shows a schematic perspective view of a semiconductor device of a second embodiment of the invention;

3 shows a schematic diagram of a portion of a semiconductor wafer from its active top with planned Sägespuren;

4 shows a schematic diagram of the part of the semiconductor wafer of 3 after insertion of saw grooves and formation of frayed edges;

5 shows a schematic cross section through the part of the semiconductor wafer according to 4 along the section line AA in 4 ;

6 shows a schematic diagram of the back of the semiconductor wafer with a first planar pattern in the semiconductor chip positions;

7 shows a schematic diagram of the back of the semiconductor wafer with a second planar pattern in the semiconductor chip positions;

8th shows a schematic diagram of the back of the semiconductor wafer with a third area pattern in the semiconductor chip positions;

9 shows a schematic diagram of the back of the semiconductor wafer with a fourth area pattern in the semiconductor chip positions;

10 shows schematic diagrams of different area patterns on the backs of semiconductor chips.

1 shows a schematic perspective view of a semiconductor device 10 a first embodiment of the invention. To the individual components of the semiconductor device 10 clearly marked, is the case 1 from an opaque plastic housing compound 17 indicated by dashed lines, so that a semiconductor chip 2 becomes visible, which is an array of flip-chip contacts 3 on its active top 4 having. The flipchip contacts 3 are on contact pads 5 the top 6 a wiring substrate 7 arranged.

The wiring substrate 7 points to its top 6 opposite bottom 8th External contact surfaces with external contacts 9 of the semiconductor device 10 on. The external contacts 9 are not shown outer contact surfaces and not shown through contacts with the contact pads 5 electrically connected. This shows the back 11 of the semiconductor device 2 frayed boundary edges 21 on.

These frayed boundary edges 21 can be used to align the semiconductor chip 2 with its flip-chip contacts 3 on the contact pads 5 do not contribute. Rather, there is a risk that the semiconductor device 10 Malfunctions shows.

On the back side 11 of the semiconductor chip 2 is a flat pattern 12 from an arrow 33 attached, the arrow 33 and especially the margins 34 . 35 and 36 of the arrow 33 the arrangement of the flip-chip contacts 3 on the active top 4 of the semiconductor device 10 correspond, so from the top without direct view of the external contacts 9 the semiconductor chip 2 on the wiring substrate 7 can be aligned and fixed. In this case, an electrical path from the contact surfaces of the semiconductor chip 2 via the flipchip contacts 3 of the semiconductor chip 2 and the contact pads 5 of the wiring substrate 7 and further via a wiring structure to vias through the wiring substrate 7 and finally to external contact surfaces, with external contacts 9 of the semiconductor device 10 are occupied, produced. Here are the external contacts 9 of the semiconductor device about an order of magnitude larger than the flip-chip contacts of the semiconductor chip. The wiring structure ensures that from the flipchip contacts 3 of a few micrometers in diameter, a printed circuit network is going out, the flip-chip contacts 3 with the external contacts 9 over the wiring substrate 7 combines.

2 shows a schematic perspective view of a semiconductor device 20 a second embodiment of the invention. Components with the same functions as in 1 are countersigned with the same reference signs and not discussed separately.

A difference from the first embodiment of the invention according to 1 is that as a flat pattern 12 a cross 28 was chosen. To indicate a preferred direction is a crossbar with a tip 30 Mistake. With the help of the tip 30 can be a 180 ° commutation of the flip-chip contacts 3 or of the semiconductor chip 2 be avoided. The association between the cross 28 and the flip-chip contacts 3 via limiting margins 13 of the cross 28 , The flipchip contacts 3 stand with the external contacts 9 electrically connected via corresponding vias.

3 shows a schematic diagram of a part of a semiconductor wafer 14 from his active top 4 out. This part of the semiconductor wafer 14 includes four integrated circuits 16 passing along separation marks 18 when singulating the semiconductor wafer 14 to individual semiconductor chips 2 can be separated. Each of these integrated circuits 16 is in a semiconductor chip position 15 arranged, wherein the semiconductor chip positions 15 in lines 37 and columns 38 on the semiconductor wafer 14 are arranged.

4 shows a schematic diagram of a portion of the semiconductor wafer 14 of the 3 after insertion of saw grooves 31 and forming frayed edges 21 , These frayed edges 21 arise after sawing the semiconductor wafer 14 by breaking connecting webs that are only a few microns thick. By a slight bending of the semiconductor wafer can already the frayed edges by breaking the connecting webs 19 arise.

5 shows a schematic cross section through the part of the semiconductor wafer 14 according to 4 along the section AA. When sawing is the semiconductor wafer 14 on an adhesive film or a sawing foil 32 arranged, which fixes the semiconductor wafer on a saw table. When sawing, the thickness d of the semiconductor wafer becomes 14 not completely in the separation marks 18 but it will be Sägenuten 31 introduced at a depth t, which is less than the thickness d of the semiconductor wafer 14 , There are connecting bridges 19 of semiconductor material that are a few microns thick and break apart at the slightest stress. This load can be done when lifting the film from the saw table, the film is easily bent or this burden can also when lifting individual semiconductor chips 2 from the sawing foil 32 occur.

6 shows a schematic diagram of the back of the semiconductor wafer 14 with a first flat pattern 12 , the smooth boundary edges 13 having, this first planar pattern 12 squares 22 represents for example square semiconductor chips. One of the corners of each of the squares 22 shows a phase 39 to facilitate alignment of the semiconductor chip.

7 shows a schematic diagram of the back of the semiconductor wafer 14 with a second flat pattern 12 in the semiconductor chip positions 15 , This flat pattern 12 with its edge sides 13 represents a rectangle 23 and is for semiconductor chips 2 with a rectangular areal extension of advantage. Again, one of the corners is one phase 39 provided to align the semiconductor chips 2 to facilitate.

8th shows a schematic diagram of the back of the semiconductor wafer 14 with a third flat pattern 12 in the semiconductor chip positions 15 , The flat pattern 12 is an oval in this embodiment of the invention 24 wherein an edge region is flattened to restore alignment of the semiconductor chip 2 to facilitate.

9 shows a schematic diagram of the back of the semiconductor wafer 14 with a fourth flat pattern 12 in the semiconductor chip positions 15 , where the area pattern 12 a circle 25 which is flattened on one side to the orientation of the semiconductor chip 2 to facilitate.

10 shows schematic diagrams of different areal patterns 12 on the backs 11 of semiconductor chips 2 , It shows 1 (a) a sun pattern 27 or a pattern of a compass rose with a radiate wreath 40 from several rays 41 where one of the rays 41 is dimmed to the orientation of the semiconductor chip 2 to facilitate. The 10 (b) shows a cross 28 from arrows 33 , a crossed arrow pattern 29 forms, with an arrowhead 30 differs from the other three arrowheads, so that an alignment of the semiconductor chip is also possible here. Finally shows 10 (c) one simple cross 28 with a single arrowhead 30 as it is in 2 in perspective view on the back 11 a semiconductor chip 2 you can see. With 10 (d) becomes a star 26 as a flat pattern 12 shown. This four-pointed star 26 has a cut off point 30 on to the orientation of the semiconductor chip 2 to facilitate.

Claims (18)

Semiconductor component with a housing ( 1 ) and with a semiconductor chip ( 2 ) comprising an array of flip-chip contacts ( 3 ) on its active upper side ( 4 ), wherein the flip-chip contacts ( 3 ) on contact pads ( 5 ) of the top side ( 6 ) of a wiring substrate ( 7 ) arranged on its top ( 6 ) opposite underside ( 8th ) External contact surfaces with external contacts ( 9 ) of the semiconductor device ( 10 ), which with the contact pads ( 5 ) are electrically connected, the back ( 11 ) of the semiconductor chip ( 2 ) a planar pattern ( 12 ) whose boundary edges ( 13 ) has a predetermined geometric assignment to the arrangement of the flip-chip contacts ( 3 ) on the active top side ( 4 ) exhibit. Semiconductor component according to Claim 1, characterized in that the planar pattern ( 12 ) a square ( 22 ). Semiconductor component according to Claim 1, characterized in that the planar pattern ( 12 ) a rectangle ( 23 ). Semiconductor component according to Claim 1, characterized in that the planar pattern ( 12 ) a circle ( 25 ). Semiconductor component according to Claim 1, characterized in that the planar pattern ( 12 ) an oval ( 24 ). Semiconductor component according to Claim 1, characterized in that the planar pattern ( 12 ) a star ( 26 ). Semiconductor component according to Claim 1, characterized in that the planar pattern ( 12 ) a sun pattern ( 27 ). Semiconductor component according to Claim 1, characterized in that the planar pattern ( 12 ) a cross ( 28 ). Semiconductor component according to Claim 1, characterized in that the planar pattern ( 12 ) a flat arrow ( 33 ). Semiconductor component according to Claim 1, characterized in that the planar pattern ( 12 ) a crossed arrow pattern ( 29 ). Method for producing a semiconductor component ( 10 ) with a housing ( 1 ) and with a semiconductor chip ( 2 ) comprising an array of flip-chip contacts ( 3 ) on its active upper side ( 4 ), and on its rear side ( 11 ) a planar pattern ( 12 ) whose boundary edges ( 13 ) has a predetermined geometric assignment to the arrangement of the flip-chip contacts ( 3 ) on the active top side ( 4 ), the method comprising the following steps: - producing a semiconductor wafer ( 14 ) with semiconductor chip positions ( 15 ) and with integrated circuits ( 16 ) and with contact surfaces for flip-chip contacts ( 3 ) in a predetermined arrangement on its active upper side ( 4 ), - application of areal patterns ( 12 ) on the back ( 11 ) of the semiconductor wafer ( 14 ) in the semiconductor chip positions ( 15 ) whose boundary edges ( 13 ) a predetermined geometric assignment to the arrangement of the contact surfaces on the active upper side ( 4 ), - application of flip-chip contacts ( 3 ) on contact surfaces in the semiconductor chip positions ( 15 ); Separating the semiconductor wafer ( 14 ) in semiconductor chips ( 2 ) with flip-chip contacts ( 3 ); Manufacture of a wiring substrate ( 7 ) with semiconductor device positions and contact pads ( 5 ), whose arrangement in the semiconductor component positions of the arrangement of the flip-chip contacts ( 3 ) of the semiconductor chips ( 2 ) corresponds; - Application of semiconductor chips ( 2 ) on the wiring substrate ( 7 ) in the semiconductor device positions, aligning the flip-chip contacts ( 3 ) of the semiconductor chips ( 2 ) to the arrangement of the contact pads ( 5 ) of the wiring substrate ( 7 ) with the help of the flat pattern ( 12 ) on the backsides ( 11 ) of the semiconductor chips ( 2 ); Bonding the flip-chip contacts ( 3 ) of the semiconductor chips ( 2 ) on the contact pads ( 5 ); Packaging the semiconductor device positions in a plastic housing composition ( 17 ) with embedding of the semiconductor chips ( 2 ). Method according to claim 11, characterized in that the application of two-dimensional patterns ( 12 ) is done by photolithography technique. A method according to claim 11 or claim 12, characterized in that for the application of planar patterns ( 12 ) first on the back of the semiconductor wafer ( 14 ) is applied a photosensitive polyamide layer, which is then patterned by photolithography technique. A method according to claim 11, characterized in that the application of flat Inspect ( 12 ) by means of stencil printing technology. Method according to claim 11, characterized in that the application of two-dimensional patterns ( 12 ) takes place by means of jet printing technology. Method according to one of claims 11 to 15, characterized in that the flip-chip contacts ( 3 ) on individual semiconductor chips ( 2 ) after a separation of the semiconductor wafer ( 14 ) are applied. Method according to one of claims 11 to 16, characterized in that the separation of the semiconductor wafer ( 14 ) in semiconductor chips ( 2 ) by sawing along separation tracks ( 18 ) between the semiconductor chip positions in such a way that the sawing depth (t) is smaller by a few micrometers than the thickness (d) of the semiconductor wafer ( 14 ). Method according to one of claims 11 to 17, characterized in that when singulating the semiconductor chips ( 2 ) Connecting bridges ( 19 ) of a few micrometers thickness between the semiconductor chip positions ( 15 ) are broken, with irregular frayed boundary edges ( 21 ) of the backsides ( 11 ) of the isolated semiconductor chips ( 2 ) arise.