DE10147138B4 - Method for integrating imperfect semiconductor memory devices in data processing devices - Google Patents

Abstract

Method for integrating at least one imperfect semiconductor memory device (1) with functional (14) and faulty (15) memory cells into a data processing device (2), wherein the semiconductor memory device (1) is assigned a working address area (5) in which
the functional memory cells (14) are sorted by a programmable address decoder (23) in the semiconductor memory device (1) such that at least one consistently error-free address area (17) and at least one error address area (10) are formed in the working address area (5);
an information about the error address area (10) is stored in a fault memory (7);
a command processing unit (8) of the data processing device (2) has a pipeline structure (11) and an address processing unit (12) and by the address processing unit (12) before accessing an address in the work address area (5) in one through the pipeline structure (11) access control address (13) contained access address (20) is checked to see whether the access address (20) in the error address area (10); and
in the presence of such access, the access address (20) is recoded into a spare address (21) before the control command ...

Description

The The invention relates to a method for integrating at least one featured and defective memory cells (hereinafter imperfect) Semiconductor memory device in a data processing device, and a semiconductor memory device for use in a such procedures.

at the production today more common Semiconductor memory devices carry the large number of individual memory cells in the semiconductor memory device in conjunction with a demanding manufacturing process too high yield losses.

The Yield losses today with various redundancy concepts encountered with those to the outside an error-free semiconductor memory device is emulated, such as by redundant memory cells, which are optically or electrically programmable connection devices (fuses, antifuses) faulty Replace memory cells.

Redundancy concepts, which are based on optically programmable connection means are previously only usable at wafer level. The effect remains on the Replacement at wafer level of identifiable defective memory cells limited.

redundancy concepts With electrically programmable connection devices is an increased production costs contrary if, for example, manufacturing steps outside or in addition to a standard manufacturing process of the semiconductor memory device necessary.

The common Redundancy concepts are always limited in their effect, since in the semiconductor memory device only limited space for redundant Memory cells and for connection required to activate the redundant memory cells and logic facilities available stands. They are not enough if the number of faulty memory cells is very big or the faulty memory cells occur in unfavorably bundled groupings.

moreover increases as the use of redundancy structures increases Probability that they themselves have errors.

All in all the effect of previous redundancy concepts remains limited. she increase the manufacturing yield is insufficient, although the absolute number defective memory cells in relation to the total number of in the semiconductor memory device located memory cells low is.

A continued increasing integration with a further increase in total number of memory cells per semiconductor memory device and increasingly more complex manufacturing processes allow a further decrease in production yield to the outside expect error-free semiconductor memory devices.

at the production to the outside fall without error semiconductor memory devices fall in big Number of nearly perfect (hereinafter imperfect) semiconductor memory devices with one in proportion to the total number of memory cells very small number of faulty, irreparable memory cells. Because common data processing devices, the semiconductor memory devices use, so far always error-free Semiconductor memory devices are such imperfect semiconductor memory devices currently unusable.

From the US 4,939,694 a memory system is known in which, with the aid of an error correction unit in the operation of a data processing device, each memory access is checked for its validity and corrected if necessary. Using an address interpreter, access to memory cells identified as permanently faulty is prevented by recoding a memory access to an address of a memory cell identified as defective to the address of a functional memory cell. The address interpreter uses a substitute address table for each memory access.

According to one in the US 5,835,430 described method, the address range of an electrically programmable semiconductor memory element is divided into blocks and associated with each block status information within the semiconductor device. The status information is sorted within a table in such a way that a contiguous, continuously addressable, error-free memory area results to the outside.

The US 6,163,490 refers to a semiconductor memory device or to a memory module in which address sections with such addresses, which are assigned to defective memory cells, are recoded to the end of the address area. An imperfect semiconductor memory device has a contiguous address area of error-free memory cells as a consequence and acts to the outside like a faultless perfect semiconductor memory device or a faultless memory module with a reduced address area.

It is therefore an object of the invention to provide a method, with the semiconductor memory devices, the faulty and non-functional memory cells completely he have settable memory cells, can be integrated into data processing devices. It is also an object of the invention to provide an arrangement on a semiconductor memory device by means of which the semiconductor memory device can be improved for such a method.

These Task is in a method of the type mentioned by solved specified in claim 1 features. A semiconductor memory device, which allows such a procedure is specified in claim 4. Advantageous developments The invention will become apparent from the dependent claims.

At the inventive method for the integration of faulty semiconductor memory devices in data processing devices are thus in the semiconductor memory devices, each of which is assigned a work address area, addresses faulty memory cells determined and as error addresses in a non-volatile one Error memory stored.

Then be the semiconductor memory devices and the fault memory in the Data processing device installed. The data processing device reads out the error addresses from the error memory. Subsequently is before each access of the data processing device in the Work address area of the semiconductor memory device by a Sequence control in the data processing device checked if a Access to one of the error addresses is imminent. Is such a Access before, he is suitably to a replacement address recoded before the actual memory access occurs. The recoding from impending access to error addresses to substitute addresses can in the data processing device via various mechanisms done, about one Fail-Table or via interrupt.

It is exploited that common Data processing devices Command processing units with Have pipeline structures.

there is in the pipeline structure of the command processing unit Data processing device a group of consecutive Control commands, which is currently at a head of the pipeline standing control command executed and the next in the pipeline control commands already one Preprocessing be subjected, such as by a branch processing unit (BPU).

In similar Way are according to the method of the invention Parts of the control commands, the addresses in the work address area the semiconductor memory device by an address processing unit checked and edited within the command processing unit.

there can the exam for example for all Error addresses simultaneously with parallel switched comparator devices be done, the comparison register before with the error addresses getting charged.

With increasing number of faulty memory cells increases at this Realization of the effort for the exam an address from the command processing unit against all error addresses.

In Advantageously, the effort at this point, so the Number of comparisons, limited, within the working address range of the semiconductor memory device at least one throughout error-free (in the following linearized) address range and outside the error-free address areas at least one error address area is created.

ever after arrangement of the semiconductor memory devices (serial or parallel) is then for a semiconductor memory device or a group of semiconductor memory devices Only at best a comparison process necessary to check whether the Address of the memory access inside or outside an error address area the semiconductor memory device is located. A distance (offset) of the address access to a lowermost address of an error address range the semiconductor memory device can then be used as a pointer in a Replacement storage space serving elsewhere depending on from a total error address area in the data processing apparatus reserved for this purpose.

are the semiconductor memory devices DRAMs (dynamic random access memories) and arranged on memory modules, then the error addresses preferably in the EEPROM located on the memory module (electrically erasable programmable read only memory).

It but can also in the semiconductor memory device itself a non-volatile Memory area are created for recording the error addresses, either in the address range of the semiconductor memory device or about in one a special fashion accessible, nonvolatile Register set of the semiconductor memory device.

If imperfect, linearized address areas are to be created consistently in an imperfect semiconductor memory device, then a programmable address decoder is required for this, which makes it possible to suitably address internal address lines connected to the memory cells with external, connected to terminal devices of the semiconductor memory device to connect address lines.

These shortcut can be more common by a variation Redundancy concepts take place in that from a supply of redundant Memory cells resulting from faulty memory cells Gaps in a standard memory cell array starting from a lower one Address from being filled up, as far as the supply of redundant memory cells. The difference existing redundancy concepts consists in that just not inevitably Each defective memory cell must be replaced to a trafficable semiconductor memory device but the semiconductor memory device just in each Case marketable is and has a memory size, which results from the uppermost address, up to a consistently error-free Address space was created.

adversely on such a conception of a programmable address decoder is that either a high number of redundant memory cells be provided or a relatively large memory loss in the Semiconductor memory device must be accepted.

In its preferred embodiment The address decoder encodes the standard memory cell array in one Way around that addresses defective memory cells by functioning memory cells off the standard memory cell array itself will be replaced. It will during the programming of the address decoder, ensure that one or several throughout error-free address areas in the working address area of the semiconductor memory device arise. Unlike the first solution, where the number of redundant Speicherzel len and thus the number of replaceable erroneous Memory cells is limited in this solution are all located on the semiconductor memory device Memory cells for a transcoding available. The disadvantage is the opposite the first solution complex address decoder to be provided.

The Programming of the address decoder is dependent from during a test cycle determined Error addresses in a preferred manner via optical fuses and antifuses as programmable connection devices. This type of programming is with the usual in the semiconductor processing technology means in particular reliable way realizable.

In in a particularly preferred manner, fuses are provided which are themselves even after a hänsen program the semiconductor memory device. In this Case may be the programming of the address decoder at the end of reliability tests done or changed become. Leave it the overall yield of imperfect semiconductor memory devices with consistent Increase error-free address ranges.

As well Optimization of the yield is possible with respect to different specification features. For example can be faster by replacing slower memory cells Memory cells through the programmable address decoder a higher yield achieved at faster specified semiconductor memory devices become.

Just like that is it possible in this way, by Replacement of memory cells with lower retention performance by Memory cells of higher retention Performance the yield of semiconductor memory devices with to increase lower refresh rates.

following the invention is explained in more detail with reference to the drawings, wherein for each other corresponding components the same reference numerals are used. To increase the clarity was the presentation on for the explanation limited essential components of the invention. Show it:

1 a schematic representation of the method according to a first embodiment of the invention,

2 a schematic representation of the method according to a second embodiment of the invention,

Based on 1 the method according to the invention is explained in an exemplary embodiment, wherein an illustrated semiconductor memory device 1 is present in a preferred embodiment of the invention.

The semiconductor memory device 1 is in a data processing device 2 integrated. The inventive method also requires in the illustrated embodiment, a command processing unit 8th with a pipeline structure 11 for control commands to be executed 13 , The control commands 13 be through the pipeline structure 11 pushed, where they can be edited before their actual execution.

The semiconductor memory device 1 indicates in a work address area 5 associated standard memory cell array 6 functional memory cells 14 and error addresses 9 associated defective memory cells 15 on. In the following, memory cell designates a jointly addressable group of memory elements.

With the memory cells 14 . 15 are internal address lines 24 connected. A control and address bus 26 the data processing device 2 is with connection devices 22 the semiconductor memory device 1 connected. Within the semiconductor memory device 1 lead external address lines 25 to the connection devices 22 ,

In the illustrated embodiment, the semiconductor memory device 1 a programmable address decoder 23 on. The address decoder 23 arranges the internal address lines 24 the external address lines 25 in a way to that within the work address area 5 the semiconductor memory device 1 a consistently error-free address range 17 and an error address space 10 arises.

In this case, the error address space 10 also functional memory cells 14 contained, for example, by limited resources of the address decoder 23 not the consistently error-free address range 17 add.

To simplify the illustration, only a single, consistently functioning address area is shown in the figure 17 shown. But there are also, for example due to limited resources of the address decoder 23 , Solutions with several consistently error-free address ranges 17 possible.

The error addresses 9 or the error address ranges 10 are in a fault memory 7 stored non-volatile. This example contains the error memory 7 outside the semiconductor memory device 1 along with her on a memory module 19 ,

Furthermore, in the example, a spare memory 16 outside the semiconductor memory device 1 intended. The spare memory 16 but can also be in the semiconductor memory device 1 yourself. The spare memory 16 is like the semiconductor memory device 1 to a data bus 18 and the control and address bus 26 connected.

According to the exemplary embodiment of the method according to the invention, the semiconductor memory device 1 So erroneous memory cells 15 on. Through the programmable address decoder 23 become functional memory cells 14 the semiconductor memory device 1 sorted so that for addressing via the control and address bus 26 a consistently error-free address range 17 arises.

The information about the error address area 10 will be at the end of a test cycle for the memory module 19 in a fault memory 7 stored.

With the contents of the error memory 7 be in an address processing unit 12 within the command processing unit 8th the data processing device 2 Comparison register of a comparator device 3 loaded.

After that, all through the pipeline structure 11 the command processing unit 8th pushed control commands 13 then checked to see if the control commands 13 Memory accesses (access addresses) 20 in the work address area 5 the semiconductor memory device 1 contain.

If such an access exists, then the access address becomes 20 in the comparator device 3 then checked if they are in an error address range 10 is included. Is the access address 20 in an error address area 10 , so it is in a sequence in a recoding 4 to a replacement address 21 recoded. The replacement address 21 replaced in the sequence in the control command 13 the address 20 ,

2 shows a memory module 19 with four semiconductor memory devices 1a . 1b . 1c . 1d , Each of these semiconductor memory devices 1a - 1d represents for a 64 bit wide data bus in this example 18 a 16 bit wide data bus 27a - 27d to disposal.

None of the semiconductor memory devices specified on 2 ²⁸ memory locations 1a - 1d actually has the specified address range. In fact, the semiconductor memory device has 1a one at a, 1b one to b, 1c one to c and 1d one reduced by d, but with respect to addressing via a control and address bus 26 each consistently functional address range 17a - 17d on. Overall, with c>a>b> d only one address range 2 ²⁸ -c can be addressed, since the four semiconductor memory devices 1a - 1d addressed in parallel in this example.

The value for c or 2 ²⁸ -c may also be in the memory module 19 located fault memory 7 be filed.

A flow control in the data processing device 1 reads this value, thereby loading one of several comparison registers of a comparator device 3 that are in a pipeline structure 11 a command execution unit 8th the data processing device 2 successive control commands 13 in terms of in the store commands 13 monitored addresses.

1

Semiconductor memory device

2

Data processing device

3

comparator

4

recoding

5

Work address range

6

Standard memory cell area

7

error memory

8th

Command processing unit

9

error address

10

Error address range

11

Pipelined

12

Address processing unit

13

command

14

functional memory cell

15

erroneous memory cell

16

spare memory

17

consistently error-free address area

18

bus

19

memory module

20

(Access) address

21

alternate address

22

connecting device

23

programmable address decoder

24

internal address line

25

external address line

26

Tax- and address bus

27a-d

16-bit bus

a

Number of addresses in an error address area of the semiconductor memory device 1a

b

Number of addresses in an error address area of the semiconductor memory device 1b

c

Number of addresses in an error address area of the semiconductor memory device 1c

d

number the addresses in an error address range

Claims (8)

Method for integrating at least one imperfect semiconductor memory device ( 1 ) with functional ( 14 ) and faulty ( 15 ) Memory cells in a data processing device ( 2 ), wherein the semiconductor memory device ( 1 ) a work address area ( 5 ), in which by a programmable address decoder ( 23 ) in the semiconductor memory device ( 1 ) the functional memory cells ( 14 ) so that in the work address area ( 5 ) at least one consistently error-free address range ( 17 ) and at least one error address area ( 10 ) arises; an information about the error address area ( 10 ) in a fault memory ( 7 ) is filed; a command processing unit ( 8th ) of the data processing device ( 2 ) a pipeline structure ( 11 ) and an address processing unit ( 12 ) and by the address processing unit ( 12 ) before accessing an address in the work address area ( 5 ) in one through the pipeline structure ( 11 ) pushed control command ( 13 ) contained access address ( 20 ) is checked to see if the access address ( 20 ) in the error address area ( 10 ) lies; and in the presence of such access, the access address ( 20 ) into a replacement address ( 21 ) is recoded before the control command ( 13 ) is performed. Method according to claim 1, characterized in that in each case at least one semiconductor memory device ( 1 ) on a non-volatile memory device having memory module ( 19 ), the error address ranges ( 10 ) in the course of a test cycle of the memory module ( 19 ) are stored in the non-volatile memory device and used as fault memory ( 7 ) is used. Method according to claim 1, characterized in that in the semiconductor memory device ( 1 ) nonvolatile memory cells as fault memory ( 7 ) and the error address ranges ( 10 ) in the course of a test cycle of the semiconductor memory device ( 1 ) are stored in the nonvolatile memory cells. Semiconductor memory device for use in a method according to one of claims 1 to 3 with functional ( 14 ) and faulty ( 15 ) Memory cells, with connection devices ( 22 ) connected external address lines ( 25 ), with the memory cells ( 14 . 15 ) connected internal address lines ( 24 ), a programmable address decoder ( 23 ), the internal address lines ( 24 ) functional memory cells ( 14 ) in a manner to the external address lines ( 25 ) assigns at least one continuous address range ( 17 ) of functional memory cells ( 14 ), nonvolatile memory cells as fault memory ( 7 ) for storing the error address ranges; and a command processing unit ( 8th ), which has a pipeline structure ( 11 ) and an address processing unit ( 12 ), wherein by the address processing unit ( 12 ) one in one through the pipeline structure ( 11 ) pushed control command ( 13 ) contained access address ( 20 ) can be checked as to whether the access address ( 20 ) in the error address area ( 10 ) and, if such access is available, the access address ( 20 ) before execution of the control command ( 13 ) into the substitute address ( 21 ) is recodable. Semiconductor memory device according to claim 4, characterized by redundant memory cells whose internal address lines ( 24 ) by the programmable address decoder ( 23 ) to the addresses of defective memory cells ( 15 ) in the work address area ( 5 ) of a standard memory cell array ( 6 ) are re-encodable, so that the semiconductor memory device ( 1 ) at least one continuous address range ( 17 ) with functional memory cells ( 14 ) having. Semiconductor memory device according to one of claims 4 or 5, characterized in that by the programmable address decoder ( 23 ) faulty memory cells ( 15 ) in a standard memory cell array ( 6 ) by functional memory cells ( 14 ) from the standard memory cell array ( 6 ) are replaceable, so that the semiconductor memory device ( 1 ) at least one continuous address range ( 17 ) with functional memory cells ( 14 ) having. Semiconductor memory device according to one of Claims 4 to 6, characterized by optically programmable connection devices by means of which the address decoder ( 23 ) depending on a test result that the error addresses ( 9 ), is programmable. Memory module having - a base substrate - on the base substrate formed control and address bus ( 26 ) and a data bus ( 18 ) and - to the data bus ( 18 ) and the control and address bus ( 26 ) connected semiconductor memory devices ( 1 ), characterized in that the semiconductor memory devices ( 1 ) are formed as semiconductor memory devices according to one of claims 4 to 7.