DE10043761C2 - RF distribution - Google Patents
RF distributionInfo
- Publication number
- DE10043761C2 DE10043761C2 DE2000143761 DE10043761A DE10043761C2 DE 10043761 C2 DE10043761 C2 DE 10043761C2 DE 2000143761 DE2000143761 DE 2000143761 DE 10043761 A DE10043761 A DE 10043761A DE 10043761 C2 DE10043761 C2 DE 10043761C2
- Authority
- DE
- Germany
- Prior art keywords
- circuit
- distribution network
- odk
- receiver
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
- H03K5/1506—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/159—Applications of delay lines not covered by the preceding subgroups
Description
Die Erfindung betrifft ein HF-Verteilnetz gemäß dem Oberbegriff des Patentanspruches 1.The invention relates to an RF distribution network according to the Preamble of claim 1.
Ein solches Verteilnetz ist aus "RS-422-A Electrical Characteristics of Balanced Voltage Digital Interface Circuits", EIA Standard, December 1978, Seiten 1-17, bekannt.Such a distribution network is from "RS-422-A Electrical Characteristics of Balanced Voltage Digital Interface Circuits ", EIA Standard, December 1978, pages 1-17.
Elektronische Vermittlungs- und Übertragungssysteme für Sprach- und Dateninformationen benötigen den Anschluß von mehreren digitalen, integrierten HF-Empfangsschaltungen an eine digitale, integrierte HF-Senderschaltung zur Verteilung von hochfrequenten, komplementären Daten- und Taktsignalen. Dies kann mit Hilfe von HF-Verteilnetzen realisiert werden.Electronic switching and transmission systems for Voice and data information require the connection of several digital, integrated RF receiving circuits a digital, integrated RF transmitter circuit for distribution of high-frequency, complementary data and clock signals. This can be achieved with the help of HF distribution networks.
Bisher sind diese HF-Verteilnetze derart ausgestaltet, daß beispielsweise eine digitale, integrierte Verzweiger- Schaltung (Splitter) zwischen die HF-Sender- und die HF- Empfangsschaltungen geschaltet wird, die die Ausgangssignale der HF-Senderschaltung auf mehrere Leitungen aufteilt und jeweils einer HF-Empfangsschaltung zuführt.So far, these RF distribution networks have been designed such that for example a digital, integrated branching Connection (splitter) between the RF transmitter and the RF Receiving circuits is switched, the output signals splits the RF transmitter circuit over several lines and each feeds an RF receiving circuit.
Eine andere bekannte Möglichkeit besteht in der Zwischenschaltung von Entkoppler-Schaltungen (Buffern), die die Signale der HF-Senderschaltung jeweils einer beziehungsweise maximal zwei, sehr eng nebeneinander liegenden HF-Empfangsschaltungen zuführen. Another known possibility is the Interposition of decoupler circuits (buffers) that the signals of the RF transmitter circuit one each or a maximum of two, very close to each other supply lying RF receiving circuits.
Nachteilig bei beiden bekannten Ausführungen ist der Bedarf an Zusatzkomponenten, also an Splittern oder an Buffern sowie an HF-Leitungen und an Abschlußwiderständen W zum impedanzrichtigen Abschluß der HF-Leitungen zwischen der HF- Senderschaltung und dem Splitter/Buffer und zwischen Splitter/Buffer und den HF-Empfangsschaltungen. Hierdurch ergibt sich ein Mehrbedarf an Platz. Darüber hinaus führen die zusätzlichen Komponenten zu einer Zunahme an Verlustleistung.The disadvantage of both known designs is the need on additional components, i.e. on splitters or buffers as well on HF lines and on terminating resistors W for correct impedance termination of the HF lines between the HF Transmitter circuit and the splitter / buffer and between Splitter / Buffer and the RF receiving circuits. hereby there is an additional need for space. Lead beyond the additional components to an increase Power dissipation.
Es ist daher Aufgabe der Erfindung, ein HF-Verteilnetz zu entwickeln, das bei der Verteilung von HF-Signalen nur wenig Verlustleistung produziert und sehr wenig Platz benötigt.It is therefore an object of the invention to provide an RF distribution network develop that in the distribution of RF signals little Power dissipation and takes up very little space.
Die Aufgabe zur Entwicklung eines HF-Verteilnetzes wird durch den ersten unabhängigen Vorrichtungsanspruch gelöst.The task of developing an RF distribution network is accomplished by solved the first independent device claim.
Demgemäß schlagen die Erfinder vor, ein HF-Verteilnetz zur
Verteilung von komplementären, digitalen Daten- und/oder
Taktsignalen, mit zumindest einer HF-Senderschaltung,
mehreren HF-Empfangsschaltungen, zumindest einem
Abschlußwiderstand W und zumindest einem Leitungspaar,
bestehend aus jeweils zwei Leitern, das die Daten- und/oder
die Taktsignale von der HF-Senderschaltung zu den HF-
Empfangsschaltungen leitet, wobei die HF-Empfangsschaltungen
an dem zumindest einen Leitungspaar seriell hinter der HF-
Senderschaltung angeordnet sind, dahingehend
weiterzuentwickeln, daß die HF-Senderschaltung zu der ersten
HF-Empfangsschaltung und die HF-Empfangsschaltungen
zueinander Abstände a aufweisen, wobei die Abstände a
zwischen den einzelnen Schaltungen derart dimensioniert sind,
daß die doppelte spezifische Kettenlaufzeit τ'odK eines Daten-
und/oder eines Taktsignals auf dem Leitungsstück a zwischen
einem Ausgang der HF-Senderschaltung und dem Eingang der
ersten HF-Empfangsschaltung sowie zwischen den Eingängen der
Empfangsschaltung und der nächsten Empfangsschaltung kleiner
ist, als eine Pegelübergangsdauer T0%-100% der Daten- und/oder
der Taktsignale, so daß folgende Gleichung (1) gilt:
Accordingly, the inventors propose an RF distribution network for the distribution of complementary, digital data and / or clock signals, with at least one RF transmitter circuit, several RF reception circuits, at least one terminating resistor W and at least one line pair, each consisting of two conductors, which conducts the data and / or the clock signals from the RF transmitter circuit to the RF receiver circuits, the RF receiver circuits being arranged in series on the at least one line pair behind the RF transmitter circuit, in such a way that the RF transmitter circuit to the first RF receiving circuit and the RF receiving circuits have distances a from one another, the distances a between the individual circuits being dimensioned such that the double specific chain delay time τ ' odK of a data and / or a clock signal on the line section a between an output of the RF transmitter circuit and the input of the first RF receiver circuit and between the inputs of the receiving circuit and the next receiving circuit is smaller than a level transition duration T 0% -100% of the data and / or the clock signals, so that the following equation (1) applies:
2.a.τ'odK < 1,67.T20%-80% (1).2.a.τ ' odK <1.67.T 20% -80% (1).
Jedes einzelne Daten- und/oder Taktsignal wird gleichzeitig auf zwei Leitungen im Gegentaktbetrieb übertragen (komplementär). Ist der Pegel des Signals auf der einen Leitung 1, ist er zur gleichen Zeit auf der anderen Leitung 0 und umgekehrt.Each individual data and / or clock signal is transmitted simultaneously on two lines in push-pull mode (complementary). If the level of the signal on one line is 1 , it is at the same time on the other line 0 and vice versa.
Die Pegelübergangsdauer T0%-100% der Daten- und/oder der Taktsignale ist die Zeit, die für einen Pegelübergang von 0 auf 1 und umgekehrt (entspricht 0%-100%) benötigt wird. Da in der Schaltungstechnik üblicherweise Pegeländerungen zwischen 20% und 80% gemessen werden (entspricht 60%), wird mit Hilfe eines Skalierungsfaktors von 1,67 (100%/60%) der Wert auf die rechnerisch benötigten 100% gebracht.The level transition duration T 0% -100% of the data and / or the clock signals is the time required for a level transition from 0 to 1 and vice versa (corresponds to 0% -100%). Since level changes between 20% and 80% are usually measured in circuit technology (corresponds to 60%), the value is brought to the arithmetically required 100% using a scaling factor of 1.67 (100% / 60%).
Da ein Wellenwiderstand eines Leiters unter anderem davon abhängt, wie der Leiter betrieben wird, ergibt sich bei einem Gegentaktbetrieb (im Unterschied zu einem Gleichbetrieb) ein Gegentaktwellenwiderstand Zod.Since a wave impedance of a conductor depends, among other things, on how the conductor is operated, a push-pull wave resistance Z od results in a push-pull operation (in contrast to a synchronous operation).
Der Gegentaktwellenwiderstand Zod und eine spezifische
Gegentaktlaufzeit τ'od errechnen sich aus den Gleichungen (2)
und (3), mit C'1 und C'2, als kapazitiver und L'1 und L'2 als
induktiver Belag zwischen einem Bezugspotential und den
Leitern, und C'12 als kapazitiver und L'12 als induktiver Be
lag zwischen den Leitern, wobei C'1 = C'2 gilt:
The push-pull wave resistance Z od and a specific push-pull delay time τ ' od are calculated from equations (2) and (3), with C' 1 and C ' 2 , as capacitive and L' 1 and L ' 2 as inductive coating between a reference potential and the conductors, and C '12 as capacitive and L' 12 as inductive Be between the conductors, where C ' 1 = C' 2 applies:
Durch die im Leitungspaar auf beiden Leitern in den Abständen
a angebrachten HF-Empfangsschaltungen mit den Eingangskapazi
täten CE entsteht ein Kettenwellenwiderstand ZodK des Gegen
taktwellenwiderstandes Zod mit einer spezifischen Kettenlauf
zeit τ'odK. Der Kettenwellenwiderstand ZodK und die spezifi
sche Kettenlaufzeit τ'odK sind definiert durch die Gleichungen
(4) und (5):
Due to the RF receiving circuits with the input capacitances C E attached to the two conductors at intervals a, a chain wave resistance Z odK of the counter clock wave resistance Z od with a specific chain running time τ ' odK arises . The chain wave resistance Z odK and the specific chain running time τ ' odK are defined by equations (4) and (5):
Die Eingangskapazitäten CE der HF-Empfangsschaltungen verrin gern also den Kettenwellenwiderstand ZodK.The input capacitances C E of the RF receiving circuits are therefore happy to reduce the chain impedance Z odK .
Gilt die Gleichung (1), so können Oszillationen beziehungs weise Verbeulungen der Flanke bei Pegelwechseln verhindert werden. Diese Oszillationen treten dann auf, wenn die HF- Empfangsschaltung wesentlich weniger Zeit zum Schalten benö tigt, als ein Daten- oder ein Taktsignal braucht, um auf dem Streckenabschnitt a hin- und zurückzulaufen.If equation (1) applies, then oscillations can be related wise buckling of the flank is prevented when level changes become. These oscillations occur when the RF Receiving circuit need significantly less time to switch tigt as a data or a clock signal needs to on the To run section a back and forth.
In einer vorteilhaften Ausgestaltung des erfindungsgemäßen HF-Verteilnetzes weisen die HF-Empfangsschaltungen zueinander sowie die erste HF-Empfangsschaltung zu der HF- Senderschaltung gleiche Abstände a auf. In an advantageous embodiment of the invention RF distribution network, the RF receiving circuits point to each other as well as the first RF receiving circuit to the RF Transmitter circuit equal distances a on.
In einer weiteren vorteilhaften Weiterentwicklung ist das er
findungsgemäße HF-Verteilnetz derart ausgestaltet, daß die
doppelte spezifische Kettenlaufzeit τ'odK der Summe der Lei
tungslängen a zwischen der HF-Senderschaltung und der letzten
HF-Empfangsschaltung kleiner ist, als eine minimale Impuls
breite wmin der übertragenen Daten- und/oder Taktsignale, wo
bei die Gleichung (6) gelten soll:
In a further advantageous further development, the inventive HF distribution network is designed such that the double specific chain running time τ ' odK the sum of the line lengths a between the RF transmitter circuit and the last RF receiver circuit is smaller than a minimum pulse width w min of the transmitted data and / or clock signals, where equation (6) is to apply:
8.a.τ'odK < wmin (6)8.a.τ ' odK <w min (6)
Hierbei versteht man unter der minimalen Impulsbreite wmin die kleinste Zeitdauer zwischen zwei Pegelwechseln eines Signals von 0 auf 1 und von 1 auf 0 oder umgekehrt, das heißt von 1 auf 0 und von 0 auf 1. Die minimalen Impulsbreite wmin ist also die kürzeste mögliche Zeitdauer, die das Signal auf ei nem Pegel 1 oder 0 verbleibt.Here, the minimum pulse width w min is the smallest time between two level changes of a signal from 0 to 1 and from 1 to 0 or vice versa, that is from 1 to 0 and from 0 to 1. The minimum pulse width w min is therefore the shortest possible length of time that the signal remains at a level 1 or 0.
Eine andere vorteilhafte Ausgestaltung des erfindungsgemäßen HF-Verteilnetzes sieht vor, daß direkt vor und/oder hinter der letzten HF-Empfangsschaltung der zumindest eine Abschluß widerstand W vorgesehen ist, wobei der mindestens eine Abschlußwiderstand W derart ausgestaltet ist, daß er an einen Kettenwellenwiderstand ZodK angepaßt ist. Der zumindest eine Abschlußwiderstand W kann also vor oder hinter dem Eingang der letzten HF-Empfangsschaltung angeordnet sein, wobei die Anordnung hinter dem Eingang der letzten HF-Empfangsschaltung bevorzugt wird.Another advantageous embodiment of the RF distribution network according to the invention provides that the at least one terminating resistor W is provided directly in front of and / or behind the last RF receiving circuit , the at least one terminating resistor W being designed in such a way that it connects to a chain impedance Z odK is adjusted. The at least one terminating resistor W can therefore be arranged in front of or behind the input of the last RF reception circuit, the arrangement behind the input of the last HF reception circuit being preferred.
Dieser Abschlußwiderstand W wird also nicht an den nominalen Wellenwiderstand der Leitungen angepaßt, sondern an einen er rechneten Kettenwellenwiderstand ZodK. This terminating resistor W is therefore not adapted to the nominal characteristic impedance of the lines, but to a chain impedance Z odK calculated by it .
Eine Ausgestaltung des erfindungsgemäßen HF-Verteilnetzes
sieht vor, daß der mindestens eine Abschlußwiderstand W der
art ausgestaltet ist, daß er kleiner als ein Gegentaktwellen
widerstand Zod der Leiter, jedoch größer oder gleich dem er
rechneten Kettenwellenwiderstand ZodK ist, so daß die Glei
chung (7) gilt:
An embodiment of the RF distribution network according to the invention provides that the at least one terminating resistor W is designed such that it is smaller than a push-pull wave resistance Z od the conductor, but greater than or equal to the calculated chain wave resistance Z odK , so that the equation (7) applies:
ZodK ≦ W < Zod (7)Z odK ≦ W <Z od (7)
In einer Weiterentwicklung sind die Leiter als Stripline- Leitungen ausgebildet, das heißt, als ein querhomogenes Lei tersystem, bestehend aus mindestens einem planar angeordneten und verkoppelten Leiterpaar und zwei Bezugspotentialebenen, die ober- und unterhalb davon angeordnet sind.In a further development, the heads are stripline Lines formed, that is, as a cross-homogeneous Lei ter system, consisting of at least one planar and coupled conductor pair and two reference potential levels, which are arranged above and below it.
Besonders vorteilhaft ist das erfindungsgemäße HF-Verteilnetz ausgestaltet, wenn die HF-Senderschaltung eine hohe Anzahl von Senderausgängen und die HF-Empfangsschaltung eine hohe Anzahl von Empfängereingängen aufweisen, das heißt bei Ver wendung von hochintegrierten Sender- und Empfangsbausteinen. Einen solchen Einsatzfall stellt zum Beispiel eine Eingangs stufe einer Koppelbaugruppe des EWSD-Koppelnetzes SND (EWSD = Elektronisches Wählsystem Digital, SND = Switching Network) mit 32 Dateneingängen und 4 Takteingängen dar, die auf engs tem Raum an ihren 36 Senderausgängen eine Verteilung auf ins gesamt 144 Empfängereingangspunkte - jeweils doppelt, auf grund des komplementären Betriebs - vornimmt.The HF distribution network according to the invention is particularly advantageous designed when the RF transmitter circuit a large number of transmitter outputs and the RF receiving circuit a high Have number of receiver inputs, that is, with Ver application of highly integrated transmitter and receiver modules. An input is one such application level of a coupling module of the EWSD switching network SND (EWSD = Electronic dialing system digital, SND = Switching Network) with 32 data inputs and 4 clock inputs, which are based on engs a space on their 36 transmitter outputs a total of 144 receiver entry points - each double, on due to the complementary operation - makes.
Bisherige Lösungen, zum Beispiel die Integration von 36 Splitterschaltungen in die Ausgänge der integrierten Sender schaltung, sind problematisch und für den zuvor genannten Einsatzfall als Eingangsstufe einer Koppelbaugruppe des EWSD- Koppelnetzes SND nicht einsetzbar, auf Grund von einer Anschlußbegrenzung der einsetzbaren Gehäuse und den Platzver hältnissen.Previous solutions, for example the integration of 36 Splitter circuits in the outputs of the integrated transmitters circuit, are problematic and for the aforementioned Use as an input stage of a coupling module of the EWSD Coupling network SND cannot be used due to one Connection limitation of the usable housing and the space ver ratios.
Weitere Merkmale der Erfindung ergeben sich aus den Unteran sprüchen und der nachfolgenden Beschreibung der Ausführungs beispiele unter Bezugnahme auf die Zeichnungen.Further features of the invention result from the Unteran say and the following description of the execution examples with reference to the drawings.
Im folgenden wird die Erfindung anhand der Zeichnungen näher beschrieben. Es zeigen:The invention will be described in more detail below with reference to the drawings described. Show it:
Fig. 1: ein bekanntes 1 : 4-Verteilnetz mit einem Splitter; FIG. 1 shows a known 1: 4-distribution network with a splitter;
Fig. 2: ein bekanntes 1 : 4-Verteilnetz mit zwei Entkopp lern; Fig. 2: Learn a known 1: 4 distribution network with two decoupling;
Fig. 3: ein erfindungsgemäßes 1 : 4-Verteilnetz mit einem Abschlußwiderstandspaar; FIG. 3 shows an inventive 1: 4-distribution network with a terminating resistor pair;
Fig. 4: Querschnitt durch ein Leiterpaar mit den wirksa men Kapazitätsbelägen; Fig. 4: cross section through a pair of conductors with the effective capacitance coverings;
Fig. 5: ein erfindungsgemäßes 1 : 4-Verteilnetz mit einem Einzelwiderstand; FIG. 5 shows an inventive 1: 4-distribution with a single resistor;
Fig. 6: 1 : 4-Verteilnetze von 32 Daten- und 4 Taktsignalen eines Sender-ASICs zu vier Empfänger-ASICs einer Koppelnetzeingangsstufe; Fig. 6: 1: 4-distribution of 32 data and 4 clock signals of a transmitter-receiver ASICs to four ASICs a switching network input stage;
Fig. 7: Ausschnitt eines Leiterplattenquerschnittes A-A'. Fig. 7: Section of a circuit board cross section A-A '.
Die Fig. 1 zeigt ein bekanntes 1 : 4-Verteilnetz 1, das digi tale HF-Signale mit Hilfe eines Splitters 5, also einer Ver zweigerschaltung, von einer HF-Senderschaltung 2 auf vier HF- Empfangsschaltungen 3.1 bis 3.4 aufteilt. Die Übertragung der HF-Signale findet hierbei, wie auch in allen nachfolgend beschriebenen Ausführungsbeispielen, im Gegentaktbetrieb statt (komplementäre Signalübertragung). Fig. 1 shows a known 1: 4 distribution network 1 , the digital RF signals with the aid of a splitter 5 , ie a Ver branching circuit, from an RF transmitter circuit 2 to four RF receiving circuits 3.1 to 3.4 . The RF signals are transmitted in push-pull mode, as in all of the exemplary embodiments described below (complementary signal transmission).
Die HF-Senderschaltung 2 enthält einen invertierenden Ausgang 7, der die zu übertragenden HF-Signale auf dem Leiter 4.2, zur komplementären Signalübertragung, invertiert. Der inver tierende Ausgang 7 bewirkt darüber hinaus, daß keine zeitli che Verschiebung der beiden komplementären HF-Signale gegen einander auftritt. Entsprechend enthalten die HF- Empfangsschaltungen 3.X jeweils einen invertierenden Eingang 8.The RF transmitter circuit 2 contains an inverting output 7 , which inverts the RF signals to be transmitted on the conductor 4.2 , for complementary signal transmission. The inverting output 7 also causes no temporal che shift of the two complementary RF signals against each other occurs. Correspondingly, the RF receiving circuits 3 .X each contain an inverting input 8 .
Der Splitter 5, der die Leiter 4.1 und 4.2 aufteilt, besteht aus zwei Eingängen 11, acht Ausgängen 14, einem Empfänger 13 und vier Sendern 12.1 bis 12.2. Sowohl Sender 12.X als auch Empfänger 13 arbeiten an ihren Eingängen 8 und an ihren Aus gängen 7 komplementär. Der invertierende Ausgang 7 des Emp fängers 13 steuert dabei gleichzeitig die invertierenden Ein gänge 8 der vier Sender 12.X an.The splitter 5 , which divides the conductors 4.1 and 4.2 , consists of two inputs 11 , eight outputs 14 , a receiver 13 and four transmitters 12.1 to 12.2 . Both transmitter 12 .X and receiver 13 work on their inputs 8 and on their outputs 7 complementary. The inverting output 7 of the Emp catcher 13 simultaneously controls the inverting inputs 8 of the four transmitters 12 .X.
Der Splitter teilt also den Leiter 4.1 auf die Leiter 4.1', 4.3', 4.5' und 4.7' und den Leiter 4.2 auf die Leiter 4.2', 4.4', 4.6' und 4.8' auf, wobei die Leiter 4.1' und 4.2' Sig nale zu der HF-Empfangsschaltung 3.1 leiten, die Leiter 4.3' und 4.4' zu der Empfangsschaltung 3.2 und so fort.The splitter thus divides the conductor 4.1 into the conductors 4.1 ', 4.3 ', 4.5 'and 4.7 ' and the conductor 4.2 between the conductors 4.2 ', 4.4 ', 4.6 'and 4.8 ', the conductors 4.1 'and 4.2 ' Sig lead to the RF receiving circuit 3.1 , the conductors 4.3 'and 4.4 ' to the receiving circuit 3.2 and so on.
Weiterhin sind direkt an den Eingängen 11 des Splitters 5, die zugleich die Eingänge des Empfängers 13 darstellen, sowie an den Eingängen 10.1 bis 10.4 jeder HF-Empfangsschaltung 3.1 bis 3.4 ein Abschlußwiderstand W vorgesehen, so daß das be kannte 1 : 4-Verteilnetz 1 insgesamt zehn Abschlußwiderstände W benötigt.Furthermore, a terminating resistor W is provided directly at the inputs 11 of the splitter 5 , which also represent the inputs of the receiver 13 , and at the inputs 10.1 to 10.4 of each RF receiving circuit 3.1 to 3.4 , so that the known 1: 4 distribution network 1 a total of ten terminating resistors W are required.
Dieses bekannte 1 : 4-Verteilnetz 1 bedarf also einer großen Anzahl an Komponenten und benötigt entsprechenden Platz, um diese Komponenten unterzubringen. Bei vorgegebenen Abmessun gen der einsetzbaren Gehäuse kann dies zu Problemen führen.This known 1: 4 distribution network 1 therefore requires a large number of components and requires corresponding space in order to accommodate these components. With given dimensions of the usable housing, this can lead to problems.
Die Fig. 2 zeigt ein bekanntes 1 : 4-Verteilnetz 1, das mit Hilfe zweier Entkoppler-Schaltungen 6 die HF-Signale auf vier HF-Empfangsschaltungen 3.1 bis 3.4 aufteilt. Figs. 2 shows a known 1: 4-distribution network 1, by means of two uncoupling circuits 6, the RF signals on four RF receiver circuits divides 3.1 to 3.4.
Hierzu werden die Leiter 4.1 und 4.2 zuerst von den Entkopp lern 6 auf die Leiter 4.1' bis 4.4' aufgeteilt, die sich nach den Abschlußwiderständen W direkt vor den HF- Empfangsschaltungen 3.1 bis 3.4 auf die Leiter 4.1" bis 4.8" aufteilen. Die Eingänge 8 der Empfänger 3.X befinden sich hierbei so direkt hinter den Abschlußwiderständen W, wie es deren Gehäuseabmessungen erlauben.For this purpose, the conductors 4.1 and 4.2 are first divided by the decouplers 6 onto the conductors 4.1 'to 4.4 ', which are distributed according to the terminating resistors W directly before the RF receiving circuits 3.1 to 3.4 to the conductors 4.1 "to 4.8 ". The inputs 8 of the receiver 3 .X are located here directly behind the terminating resistors W, as their housing dimensions allow.
Wie in der Fig. 1 weist die HF-Senderschaltung 2 einen in vertierenden Ausgang 7 und die HF-Empfangsschaltungen 3.X in vertierende Eingänge 8 auf. Auch die beiden Entkoppler- Schaltungen 6 tragen jeweils einen invertierenden Eingang 8 und Ausgang 7. Die gestrichelte Abgrenzung soll andeuten, daß es sich um getrennt anzusteuernde Entkoppler-Schaltungen 6 handelt, die zwar in einem Bauelement kombiniert sein kön nen, aber getrennte Anschlüsse an einem den Gehäuse haben.As in FIG. 1, the RF transmitter circuit 2 has an inverting output 7 and the RF receiver circuits 3 .X have inverting inputs 8 . The two decoupler circuits 6 also each have an inverting input 8 and output 7 . The dashed line delimitation is intended to indicate that there are decoupler circuits 6 to be controlled separately, which can be combined in one component, but have separate connections on one of the housings.
In dieser Ausführung ist die Anzahl der benötigten Abschluß widerstände W im Vergleich zu der Schaltung aus der Fig. 1 auf sechs reduziert und auch der Leitungsaufwand ist gerin ger. Allerdings treten auch hier Platzprobleme auf, wenn hochintegrierte Schaltungen mit einer großen Anzahl an Sen derausgängen und Empfängereingängen verwendet werden.In this embodiment, the number of required terminating resistors W is reduced to six compared to the circuit of FIG. 1 and the amount of wiring is also low. However, space problems also arise here if highly integrated circuits with a large number of transmitter outputs and receiver inputs are used.
Die Fig. 3 zeigt ein bevorzugtes Ausführungsbeispiel des er findungsgemäßen 1 : 4-Verteilnetzes 1 zur Verteilung von komplementären, digitalen Daten- und/oder Taktsignalen, in dem vier HF-Empfangsschaltungen 3.1 bis 3.4 seriell in einem ge schlossenen Leitungszug hinter die HF-Senderschaltung 2 ge schaltet sind, wobei der Leitungszug aus zwei Leitern 4.1 und 4.2 besteht. Fig. 3 shows a preferred embodiment of the inventive 1: 4 distribution network 1 for the distribution of complementary, digital data and / or clock signals, in which four RF receiving circuits 3.1 to 3.4 serially in a closed cable path behind the RF transmitter circuit 2 ge are switched, the cable run consisting of two conductors 4.1 and 4.2 .
Die Abstände a zwischen den HF-Empfangsschaltungen 3.1 bis 3.4 sowie zwischen der HF-Empfangsschaltung 3.1 zu der HF- Senderschaltung 2 sind gleich. Die Leitungen ls stellen Ver bindungsleitungen zwischen den Eingängen 10.X am Gehäuse der HF-Empfangsschaltungen 3.X und einem Chip der HF- Empfangsschaltungen 3.X dar.The distances a between the RF receiving circuits 3.1 to 3.4 and between the RF receiving circuit 3.1 and the RF transmitter circuit 2 are the same. The lines ls represent connecting lines between the inputs 10 .X on the housing of the RF receiving circuits 3 .X and a chip of the RF receiving circuits 3 .X.
Direkt vor der letzten HF-Empfangsschaltung 3.4, das heißt an jedem der beiden Eingänge 10.4 der HF-Empfangsschaltung 3.4, ist zum impedanzrichtigen Abschluß der Leiter 4.1 und 4.2 ein Abschlußwiderstand W vorgesehen. Dieser Abschlußwiderstand W ist vorzugsweise an einen Kettenwellenwiderstand ZodK ange paßt.Directly in front of the last RF receiving circuit 3.4 , that is to say at each of the two inputs 10.4 of the RF receiving circuit 3.4 , a terminating resistor W is provided for terminating the conductors 4.1 and 4.2 with the correct impedance. This terminating resistor W is preferably fitted to a chain impedance Z odK .
Erfindungsgemäß werden vorzugsweise folgende übertragungs
technischen Anforderungen bei der Dimensionierung des HF-
Verteilnetzes 1 erfüllt:
According to the invention, the following transmission-technical requirements are preferably met when dimensioning the HF distribution network 1 :
-
a) Die doppelte Laufzeit des Leitungsstücks zwischen dem Sen
derausgang 9 und dem nächsten Empfängereingang 10.1 sowie
zwischen dem Empfängereingang 10.1 und dem darauf folgenden
Empfängereingang 10.2, und so weiter, im Abstand a, ist ge
genüber der Pegelübergangsdauer T0%-100% kleiner:
2.a.τ'odK < 1,67.T20%-80% (1)a) The double running time of the line section between the sensor output 9 and the next receiver input 10.1 and between the receiver input 10.1 and the subsequent receiver input 10.2 , and so on, at a distance a, is smaller than the level transition duration T 0% -100% :
2.a.τ ' odK <1.67.T 20% -80% (1) -
b) Zur Verhinderung ausgeprägter Reflexionen durch die Punkt
lasten CE der HF-Empfangsschaltungen 3.X soll die doppelte
Laufzeit der Summe der Abstände a zwischen der HF-
Senderschaltung 2 und der letzten HF-Empfangsschaltung 3.4
kleiner sein als die Impulsbreite wmin der übertragenen HF-
Signale. Bei dem 1 : 4 Verteilnetz 1 mit vier Abständen a er
gibt sich:
8.a.τ'odK < wmin (6)b) To prevent pronounced reflections by the point loads C E of the RF receiving circuits 3 .X, the double transit time of the sum of the distances a between the RF transmitter circuit 2 and the last RF receiving circuit 3.4 should be less than the pulse width w min of the transmitted RF signals. In the 1: 4 distribution network 1 with four distances a, there are:
8.a.τ ' odK < w min (6) -
c) Zur Reduzierung der Reflexionen sollen die beiden
Abschlußwiderstände W am Leitungsende an den Kettenwellenwi
derstandswert ZodK des seriellen HF-Verteilnetzes 1 angepaßt
werden:
ZodK ≦ W < Zod (7)c) To reduce the reflections, the two terminating resistors W at the line end should be adapted to the chain shaft resistance value Z odK of the serial HF distribution network 1 :
Z odK ≦ W <Z od (7)
Ein erfindungsgemäßes HF-Verteilnetz 1 kann zum Beispiel fol
gende Dimensionen aufweisen:
τ'od = 68,4 ps/cm
Zod (Daten- und Taktsignale) = 51 Ω
ZodK (Daten- und Taktsignale) ≈ 40 Ω
C'1 = C'2 = 1,04 pF/cm
C'12 = 0,15 pF/cm
CE = 3 pF
a = 4,7 cm
T20%-80% ≈ 500 ps
Schaltfrequenz der Datensignale: 184 Mbit/s
wmin (Datensignale) = 5,4 ns
Schaltfrequenz der Taktsignale: 184 MHz
wmin (Taktsignale) = 2,7 nsAn RF distribution network 1 according to the invention can have the following dimensions, for example:
τ ' od = 68.4 ps / cm
Z od (data and clock signals) = 51 Ω
Z odK (data and clock signals) ≈ 40 Ω
C ' 1 = C' 2 = 1.04 pF / cm
C '12 = 0.15 pF / cm
C E = 3 pF
a = 4.7 cm
T 20% -80% ≈ 500 ps
Switching frequency of the data signals: 184 Mbit / s
w min (data signals) = 5.4 ns
Switching frequency of the clock signals: 184 MHz
w min (clock signals) = 2.7 ns
Mit diesen Dimensionen ergibt sich aus der Gleichung (5) für die spezifische Kettenlaufzeit τ'odK der Wert 84,7 ps/cm und die Gleichung (1) wird erfüllt: 797 ps < 835 ps. With these dimensions, the value of 84.7 ps / cm results from the equation (5) for the specific chain running time τ ' odK and the equation (1) is fulfilled: 797 ps <835 ps.
Weiterhin wird für das Datensignal mit der errechneten spezi fischen Kettenlaufzeit τ'odK = 84,7 ps/cm die Gleichung (6) erfüllt: 3,18 ns < 5,4 ns.Equation (6) is also fulfilled for the data signal with the calculated specific chain transit time τ ' odK = 84.7 ps / cm: 3.18 ns <5.4 ns.
Beim Taktsignal jedoch wird die Gleichung (6) nicht erfüllt, da sich für die Impulsbreite der Taktsignale wmin = 2.7 ns er gibt. Eine störungsfreie Übertragung der Taktsignale ist je doch dennoch gewährleistet, wenn nach der Gleichung (7) die Abschlußwiderstände W der Taktleitung den Wert des Kettenwel lenwiderstandes ZodK von ≈ 40 Ω einnehmen.However, equation (6) is not fulfilled for the clock signal, since there is w min = 2.7 ns for the pulse width of the clock signals. A trouble-free transmission of the clock signals is nevertheless guaranteed if, according to equation (7), the terminating resistors W of the clock line assume the value of the chain shaft resistance Z odK of ≈ 40 Ω.
Die Datensignalleitungen dagegen werden mit W = 50 Ω abge schlossen.The data signal lines, however, are given with W = 50 Ω closed.
Die Fig. 4 zeigt einen Querschnitt durch ein Leiterpaar mit den Leitern 4.1 und 4.2 des erfindungsgemäßen 1 : 4- Verteilnetzes. Zwischen den Leitern 4.1 und 4.2 eines kom plementären Paares ergibt sich der Kapazitätsbelag C'12, zwi schen dem Leiter 4.1 und dem Bezugspotential GND beziehungs weise VCC (hier nicht gezeigt) der Kapazitätsbelag C'1 und zwischen dem Leiter 4.2 und dem Bezugspotential GND bezie hungsweise VCC der Kapazitätsbelag C'2. . The Figure 4 shows a cross section through a pair of conductors to the conductors of 4.1 and 4.2 of the present invention 1: 4- distribution network. Between the conductors 4.1 and 4.2 of a complementary pair, there is the capacitance C '12 , between the conductor 4.1 and the reference potential GND or VCC (not shown here) the capacitance C' 1 and between the conductor 4.2 and the reference potential GND approximately VCC the capacitance C ' 2 .
Die Fig. 5 zeigt ein weiteres Ausführungsbeispiel des erfin dungsgemäßen 1 : 4-Verteilnetzes 1. Im Unterschied zu der Fig. 3 ist hier lediglich ein einziger Abschlußwiderstand W an die Eingänge 10.4 der HF-Empfangsschaltung 3.4 angebracht, der jedoch doppelt so groß ist, wie jeder einzelne Abschluß widerstand W aus der Fig. 3. . The Figure 5 shows a further embodiment of the OF INVENTION to the invention 1: 4-distribution network 1. In contrast to FIG. 3, only a single terminating resistor W is attached to the inputs 10.4 of the RF receiving circuit 3.4 , which is however twice as large as each individual terminating resistor W from FIG. 3.
Für diesen Abschlußwiderstand W ergibt sich, mit den Dimensi onen beziehungsweise Werten aus der Fig. 3, bei den Daten signalleitungen 100 Ω und bei den Taktsignalleitungen ≈ 80 Ω. For this terminating resistor W results, with the dimensions or values from FIG. 3, in the data signal lines 100 Ω and in the clock signal lines ≈ 80 Ω.
Die Fig. 6 zeigt eine Vielzahl (achtzehn) von 1 : 4- Verteilnetzen zur Verteilung von 32 Daten- und 4 Taktsignalen eines hochintegrierten Sender-ASICs 2 zu vier hochintegrier ten Empfänger-ASICs 3.1 bis 3.4 einer Koppelnetzeingangsstu fe. Die Leiterpaare werden hierbei in getrennten HF-Kammern geführt (gezeigt in der Fig. 7), wobei die Leiter 4.1 und 4.2 der oberen HF-Kammer als durchgezogene Linien dargestellt sind. Aus Gründen der Übersichtlichkeit sind die Leiter 4.1' und 4.2' der unteren HF-Kammer lediglich bei der HF- Senderschaltung 2 dargestellt, und zwar als gestrichelte Li nien. Fig. 6 shows a variety (eighteen) of 1: 4 distribution networks for the distribution of 32 data and 4 clock signals of a highly integrated transmitter ASIC 2 to four highly integrated receiver ASICs 3.1 to 3.4 of a switching network input stage. The conductor pairs are guided in separate RF chambers (shown in FIG. 7), the conductors 4.1 and 4.2 of the upper RF chamber being shown as solid lines. For reasons of clarity, the conductors 4.1 'and 4.2 ' of the lower RF chamber are only shown in the RF transmitter circuit 2 , namely as dashed lines.
Die Leiter 4.X der oberen HF-Kammern verbinden die achtzehn Senderausgänge 9 und die insgesamt 72 Empfängereingänge 10.X der oberen Anschlußreihen (obere HF-Kammer), die Leiter 4.X' verbinden die achtzehn Senderausgänge 9' und die 72 Empfän gereingänge 10.X' der unteren Anschlußreihen (untere HF- Kammer).The conductors 4 .X of the upper RF chambers connect the eighteen transmitter outputs 9 and a total of 72 receiver inputs 10 .X of the upper connection rows (upper RF chamber), the conductors 4 .X 'connect the eighteen transmitter outputs 9 ' and the 72 receiver inputs 10 .X 'of the lower connection rows (lower HF chamber).
Aus Platzgründen sind vor den Eingängen 10.4' der letzten HF- Empfangsschaltung 3.4 achtzehn Abschlußwiderstände W' sowie hinter den Eingängen 10.4 achtzehn Abschlußwiderstände W an gebracht.For reasons of space, eighteen terminating resistors W 'are placed in front of the inputs 10.4 ' of the last RF receiving circuit 3.4 and eighteen terminating resistors W behind the inputs 10.4 .
Die Fig. 7 zeigt einen Ausschnitt des Leiterplattenquer schnittes A-A' der Fig. 6. Die Leiterpaare sind als Stripline-Leitungen, die Leiterplatte als eine Multilayer- Leiterplatte (Glasfaserepoxid) ausgebildet. Fig. 7 shows a section of the circuit board cross section AA 'of Fig. 6. The pairs of conductors are designed as stripline lines, the circuit board as a multilayer circuit board (glass fiber epoxy).
Hierbei werden die Leiterpaare in getrennten HF-Kammern, in einer oberen HF-Kammer 15.1 und einer unteren HF-Kammer 15.2 geführt. Jede dieser HF-Kammern 15.1 und 15.2 bildet ein querhomogenes Leitersystem, bestehend aus einem planar ange ordneten und verkoppelten Leiterpaar, den Leitern 4.1 und 4.2, und zwei ober- und unterhalb davon angeordneten Bezugs potentialebenen GND-GND und GND-VCC.In this case, the conductor pairs are guided in separate RF chambers, in an upper RF chamber 15.1 and a lower RF chamber 15.2 . Each of these RF chambers 15.1 and 15.2 forms a cross-homogeneous conductor system, consisting of a planar arranged and coupled conductor pair, the conductors 4.1 and 4.2 , and two reference potential levels GND-GND and GND-VCC arranged above and below it.
Es versteht sich, daß die vorstehend genannten Merkmale der Erfindung nicht nur in der jeweils angegebenen Kombination, sondern auch in anderen Kombinationen oder in Alleinstellung verwendbar sind, ohne den Rahmen der Erfindung zu verlassen.It is understood that the above features of Invention not only in the specified combination, but also in other combinations or alone can be used without departing from the scope of the invention.
Insgesamt wird durch die Erfindung erreicht, daß ein HF- Verteilnetz entwickelt wurde, das bei der Verteilung von HF- Signalen nur wenig Verlustleistung produziert und sehr wenig Platz benötigt.Overall, the invention ensures that an HF Distribution network was developed, which is used for the distribution of HF Signals produced little power and very little Space needed.
Claims (7)
2.a.τ'odK < 1,67.T20%-80%.1. RF distribution network ( 1 ) for distributing complementary, digital data and / or clock signals, with at least one RF transmitter circuit ( 2 ), several RF receiving circuits ( 3 .X), at least one terminating resistor W and at least one line pair, Consisting of two conductors ( 4.1 , 4.2 ), which conducts the data and / or the clock signals from the RF transmitter circuit ( 2 ) to the RF receiver circuits ( 3 ), the RF receiver circuits (3.X) on the at least one pair of serial lines are connected in parallel behind the RF transmitter circuit ( 2 ), characterized in that the RF transmitter circuit ( 2 ) is at a spacing a from the first RF receiver circuit ( 3.1 ) and the RF receiver circuits ( 3 .X) , which are dimensioned such that a double specific chain delay τ ' odK of the data and / or clock signal on the line section a between an output of the RF transmitter circuit ( 2 ) and the input of the first RF receiver circuit ( 3.1 ) and between the inputs of the receiving circuit ( 3 .n) and the next receiving circuit ( 3 .n + 1), with n = 1, 2, 3, is less than a level transition period T 0% -100% of the data and / or Clock signals, so that:
2.a.τ ' odK <1.67.T 20% -80% .
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