DE10002377A1 - Coil and coil system for integration into a microelectronic circuit and microelectronic circuit - Google Patents

Abstract

The invention relates to a coil (20) and a coil system to be integrated in a microelectronic circuit (10) and to a corresponding microelectronic circuit (10). According to the invention, the coil (20) is placed inside an oxide layer (13) of a chip (11), whereby the oxide layer (13) is placed on the substrate surface (14) of a substrate (12). The coil (20) comprises one or more windings (21), whereby the winding(s) (21) is/are formed by at least segments of two conductor tracks (22, 23), which are each provided in spatially separated metallization levels (24, 25), and by via-contacts (40) which connect these conductor track(s) (22) and/or conductor track segments (23). In order to be able to produce high-quality coils (20), a coil (20) is produced with the largest possible coil cross-section (27), whereby a standard metallization, especially a standard metallization using copper, can, however, be used for producing the coil (20). To this end, the via contacts (40) are formed from a stack (41) of two or more via elements (42) arranged one above the other. Parts (43) of the metallization levels can be located between the via elements (42).

Description

The present invention relates to a coil and a spu lens system for integration into a microelectronic scarf tung. The invention further relates to a microelectronic circuit.

For a whole range of circuit types, for example in oscillators, amplifiers, mixers or the like, inductors (coils) are required. These are among the Component types that are integrated on one chip problems with the other circuit parts nen. So far, this has led to inductances in many Cases are still used as discrete components, because otherwise as a coil form integrated on chips le would have. At very high frequencies, that is at Frequencies in areas far above 1 GHz have to integrated inductors are used in any case because then a Si over the leads of the discrete coils signal transmission becomes very difficult.

In Fig. 1, a typical coil implementation is Darge, as is known from the prior art. A metal path runs through a spiral, creating a number of turns with increasing radii. If several metal layers are available on the chip, such spirals can be stacked. The inductances add up through a series connection. With a parallel connection, rail resistances are reduced, which leads to lower power losses. However, these known coils or coils have a number of disadvantages. A particular disadvantage arises, for example, from reaching through the magnetic field into the substrate, usually a silicon substrate. As a rule, a relatively low-resistance substrate is used in modern CMOS technologies, which results in a relatively high induction current, which is caused by the alternating magnetic field. This leads to relatively high losses, which means that the quality of the integrated inductance (coil) is relatively low. In the Giahertz frequency range, the quality is, for example, orders of magnitude lower compared to discrete coils. Since the coil quality is an important performance parameter of analog circuits, there is a need to improve the quality of the coils.

The coil types described above are, for example used in standard CMOS processes. In such a process sen is used relatively low-resistance substrate, which the correspondingly low coil quality results. Will take place which uses a high-resistance substrate, the losses decrease and the quality of the bobbin increases. A high-resistance substrate however, can have a detrimental effect on a number of transistor properties. When using high impedance In any case, substrates would no longer be a standard CMOS process possible, so that a different process management would be required. However, this is not desirable.

Another way to improve the coil quality be is that the substrate material is directly under the coil is removed by a suitable etching process. Between Coil planes and the substrate can then be a metal layer be applied. By inserting slots Eddy currents are prevented, with an Ab shielding to the substrate is achieved. A disadvantage of one such a solution, however, is that a Me valley level is less available. In addition, so that only minor improvements in the coil quality len.

Another disadvantage of the known coils is the relatively large area requirement. The coil geometry shown in FIG. 1 requires an area of 0.3 with an inductance of approximately 9 nHz. 0.3 mm. If a larger inductance is required, the area requirement increases proportionally.

In EP-A-0 725 407 a three-dimensional, in a mi croelectronic circuit integrated coil described where the coil axis is horizontal to the chip surface. The coil has one or more turns, the Windings through conductor tracks of a lower metallization level and conductor tracks of an upper metallization level as well these connecting via contacts are established. As "Via" generally becomes a connector between two metal layers understood. In the known solution, the inductive through a between the conductor tracks and via contacts inserted core made of more permeable material, which is a fundamental feature of this known solution poses. In the coil geo disclosed in EP-A-0 725 407 only a small part of the magnetic field penetrates the substrate so that the associated losses become smaller and thus the quality of the coil is improved. Despite this advantage, this coil geometry has not so far used. For example, this is because at the moment no semiconductor-compatible core material is available. In addition, all highly permeable materials with high fre result in high magnetization losses, which in turn reduce the Limit coil quality. Furthermore, the usual ones metallizations used the via resistances too high.

Based on the state of the art, the present ing invention the task, a coil and a Coil system for integration in a microelectronic Circuit, as well as a microelectronic circuit ready ask at which the state of the art described Disadvantages are avoided. In particular, who should be reached that coils, or coil systems, of high quality manufactured in a simple and inexpensive manner and in mi Croelectronic circuits can be integrated.  

This task is accomplished according to the first aspect of the present Invention solved by a coil for integration into a mi microelectronic circuit, with one or more windun gene, wherein the turn (s) by at least segments of two Conductor tracks that are spatially separated from each other Metallization levels are formed, as well as these conductors Via contacts connecting the railway (s) and / or interconnect segments is / are formed. According to the invention, the coil is thereby ge indicates that each via contact consists of a stack of two or more via elements arranged one above the other is.

This creates a high quality coil that can be easily integrated into microelectronic circuits. The coil according to the invention is based on the basic structure of the coil described in EP-A-0 725 407. Because of the low penetration of stray fields into the substrate, high coil qualities can be achieved with such a coil geometry. The formula for the inductance with such a coil geometry is:

L = µ0. µr. A. N ² / l

Μ0 is the permeability constant (1.2 E ^-6 H / M) and µr is the relative permeability number (approx. 100,000 for ferromagnetic materials). A is the cross-sectional area of the coil perpendicular to the coil axis, N is the number of turns and 1 is the length of the coil. For the reasons described in the prior art, a magnetic core is dispensed with in the coil according to the invention. Instead, it is a principle of the present invention that the cross-sectional area of the coil is increased. In the solution described in EP-A-0 725 407, very long conductor tracks would be required to cover the areas in the usual thicknesses of the via contacts (intermetallic dielectrics) of 0.5 μm to 0.3 μm in standard metallizations 10-20 µm ² . However, these long conductor tracks have a correspondingly high track resistance, which reduces the quality of the coil. If you choose a higher number of turns instead, the path resistance also increases according to the longer cable length.

The inventive design of the via contacts in Form of stacks with two or more on top of each other orderly via elements, the cross section of the coil and so that their quality increases in a simple way, resp be wisely improved. By using multiple ge stacked via elements as via contact can be achieved that a standard metallization for making the coil can be used. That means that to enlarge the Cross-sectional area no particularly thick intermetallic Dielectric with correspondingly deep via contacts used must become. The generation particularly deeper, from the standard Metallization deviating via contacts would only be with Hil Fe of special processes possible, so that the manufacture of such tiger coils would be structurally complex and costly. Another advantage of the coil according to the invention is that that relatively large coil cross-sectional areas with short lei tracks can be achieved. Furthermore, one can additional magnetic core, which is one of the Basic requirements of those disclosed in EP-A-0 725 407 Solution.

Modern silicon technologies usually have 4 to 6 metal levels available. That means the vertical Distance between the bottom and the top metal layer (Metallization level) can be up to 4 µm. Now in a standard metallization the connection between the upper and lower metallization level not over one - especially long - via contact, but by stacking one on top of the other the via elements lying on the floor, the height of the Coil cross section just this 4 µm. As above  was shown, the distance between 2 tracks was the coil in known solutions so far about 0.5 microns.

In a specific example, the coil according to the invention can have one or more turns, one turn each because of conductor track pieces, or conductor tracks, on a lowest metallization level and on an upper one most metallization level as well as through the vertical connection serving via contacts from stacks of two or more Via elements between these metallization levels det.

Preferred embodiments of the coil according to the invention give themselves from the subclaims.

The via contacts can advantageously be at least essentially perpendicular to the conductor tracks and / or conductor track segments be aligned.

Preferably, at least between individual vias Elements of a stack Components of a metallization be provided.

Via contacts designed in this way make it possible for Use a standard metallization to manufacture the coil can be detected. It was surprisingly found out that that otherwise formed via contacts necessary thicker one-piece via contacts no night le.

Preferably limit the conductor track (s) and / or the lei tram segments and the via contacts the cross section of the Kitchen sink. This cross-sectional area is determined by the vertical len distance between the track (s) respectively the metallization levels forming the conductor track segments as well the respective length of the conductor track (s) or Lei terbahn segments on these metallization levels. These lengths  are limited due to the line resistance of the cables freely selectable. With longer pipe sections on the corresponding The corresponding metallization levels are accordingly larger Cross-sectional areas possible.

The winding or turns of the coil can be advantageous forming trace (s) and / or trace segments in egg Nem spaced from each other about 4 microns. How One has already been mentioned above Distance, for example, when about 4 to 6 metallisie levels are available.

In a further embodiment, the conductor track (s) and / or Conductor segments and / or the via elements and / or the components provided between individual via elements a metallization level made of copper, in particular of elec trolytically deposited copper. When used copper, the components show only a small amount Resistance to. Copper is used as conductor material the resistance of the as a stack of two remains or more via elements formed via contact low. This resistance can be, for example, 3 Ω at a 0.18 µm Technology. Through n-Via stacks, Paral This circuit can be reduced to 1 / n. Becomes to produce the coil with a standard metallization If copper is used, the verti kalen connecting pieces between the metal levels (the Via- Elements) are filled with the low-resistance copper.

Is particularly advantageous by means of an electrolytic Process deposited copper used. This manuf copper is already known per se. She is with for example in the essay "Copper Electroplating" by Alex other E. Braun described in the magazine "Semicon ductor International ", April 1999, pages 58ff is, and the disclosure content in this regard in the description Exercise of the present invention is included.  

The coil can advantageously be integrated into one and / or microelectronic arranged in a substrate Circuit be formed, the coil axis horizontal is aligned with the substrate surface. This allows the Penetration of stray fields into the substrate is reduced what leads to higher coil grades.

Preferably, the coil start and the coil end of the Coil can be arranged adjacent to each other, so that the Spu lenachse an at least approximately closed line, in particular which forms a circular line. By such a form The coil losses are reduced, which increases the coil axis leads to a further improvement in the coil quality. In particular re when the coil axis is an approximately circular line this geometry allows the coil to be used properly neter way can be shielded laterally, as in the white tter course of the description with regard to the invented Coil system according to the invention is explained in more detail.

According to the second aspect of the present invention, a Coil system for integration in a microelectronic Circuit provided that characterized according to the invention is by one or more as described above coils according to the invention. The advantages, effects, effects and the functioning of the coil system according to the invention is also invented to the above explanations full reference to the coil and hereby referred.

Advantageous embodiments of the coils according to the invention systems result from the subclaims.

A number can preferably be used to shield the coil (s) via stacks, each consisting of one or more via Element (s) are formed. This via stack are advantageous outside the coil (s), especially outside  the coil periphery, arranged around this. Becomes a whole bunch of via stacks arranged side by side to If a coil is put around, it can be an efficient late shielding of the coil can be achieved.

The via stacks can advantageously be approximately perpendicular to the spu be aligned.

In a further embodiment, at least one shielding level can be used be provided for vertical shielding of the coil.

For example, the shielding level can be designed as a metal level be educated.

In a further embodiment, the shielding level can be a poly Silicon surface or as a structure with a highly doped sub be trained.

If there are enough metallization levels available, then the top metallization level, for example, as a shield Use the level to shield the coil vertically upwards be det. Preferably, this metal level as ge slotted surface to be designed to reduce eddy currents tie. For a shielding of the coil at the bottom serve as a shielding level, for example, as poly-silicon layer or structure formed with highly doped substrate is. This lower shielding level can also be advantageous as ge slotted surface.

According to a third aspect of the present invention a microelectronic circuit is provided which a Has number of integrated components, at least ei nes of these components is designed as an inductor. The microelectronic circuit is ge according to the invention indicates that the component provided as an inductor as a coil according to the invention as described above and / or as an inventive as described above  Coil system is formed. This allows micro create electronic circuits in which coils or way coil systems, high quality can be integrated NEN, so that such microelectronic circuits also very high frequencies in areas well above 1 GHz can be used. On the advantages, effects, effects ten and the functioning of the microelectrics according to the invention tronic circuit is also based on the above guides to the coil according to the invention and to the fiction full reference and hereby referred.

The microelectronic circuit can advantageously be based on and / or be formed in a chip, the chip being made of a substrate and at least one oxide layer is formed.

The coil can preferably be the coil system, for example be arranged within the oxide layer. In this way can use a standard metal in the manufacture of the coil be used.

The invention will now un on the basis of exemplary embodiments ter explained in more detail with reference to the accompanying drawings. Show it:

Fig. 1 shows a schematic plan view of a well-known from the prior art coil configuration;

Fig. 2 shows a first embodiment of a coil according to the prior invention;

Fig. 3 is a schematic cross-sectional view of the coil according to the Invention according to Figure 2, wherein the coil is integrated in a microelectronic circuit.

Fig. 4 is a further view of the spool according to the invention according to Fig. 2,

Fig. 5 is a schematic cross-sectional view of the coil according to the Invention according to Figure 4, in which the course of the magnetic field lines is shown.

Fig. 6 shows a further embodiment of a coil according to the present invention:

Fig. 7 is a schematic plan view of an inventive SLI coil system using a coil according to Fig. 6;

Fig. 8 is a cross-sectional view of the coil system according to the invention along the section line VIII-VIII shown in Fig. 7;

FIG. 9 shows a further embodiment of a coil system according to the invention using a coil shown in FIG. 6: and

Fig. 10 is a cross-sectional view of the coil system according to the invention along the section line XX shown in Fig. 9.

In Fig. 1 a coil 90 is illustrated as it is known from the prior art. The coil 90 has a Me tallbahn 91 , which runs through a spiral, whereby a number of turns 92 arises with increasing radii. If several metal layers are available, the coils 90 formed in this way can be stacked on top of one another and then connected either in series or in parallel. However, such coils 90 have the disadvantages mentioned with regard to the introduction to the description.

In FIGS. 2 and 3, a first embodiment of a spool 20 according to the invention is shown for integration into a microelectronic circuit 10. As can be seen in particular from FIG. 3, the microelectronic circuit 10 is formed in a chip 11 , which in turn is formed from a substrate 12 and at least one oxide layer 13 . In the present exemplary embodiment, the oxide layer 13 is formed on the substrate surface 14 .

The coil 20 has a coil start 29 and a coil end 30 and a number of turns 21 . Each coil turn 21 is formed by conductor tracks 22 or conductor track segments 23 . The conductor tracks 22 , or the conductor track segments 23 , are formed by a lower metallization level 24 and an upper metallization level 25 . To connect the two metallization levels 24 , 25 , or the conductor tracks 22 or conductor track segments 23 , vertical connecting pieces are provided between the metallization levels 24 , 25 , which are referred to as via contacts 40 . All components of Win dung (en) 21 are made of copper and therefore have only a low resistance. The coil cross-sectional area 27 enclosed by the winding 21 is determined by the vertical distance 28 of the upper metallization level 25 to the lower metalization level 24 . In the present exemplary embodiment, this distance is approximately 4 μm. Furthermore, the coil cross-sectional area 27 is determined by the length of the conductor tracks 22 , or conductor track segments 23 , on the lower and upper metallization levels 24 , 25 . These lengths can be freely selected within limits due to the line resistance of the cables. This means that with longer pipe sections on the lower and upper metallization level 24 , 25 accordingly larger cross-sectional areas are possible.

In order to be able to manufacture the coil 20 by means of a standard metallization, without particularly deep via contacts being necessary, which could only be produced by means of a complex and expensive special process, the via contacts 40 have a stack 41 each consisting of two or more via contacts. Elements 42 . Components 43 of different metallization levels, which are formed between the lower and the upper metallization levels 24 , 25 , are located between the individual via elements 42 . If copper is used as the conductor material, which can be deposited by an electrolytic process, the resistance of this stack 41 remains above one another via elements 42 with intervening components 43 of metallization levels.

As can further be seen from FIGS. 4 and 5, the coil axis 26 of the coil 20 is formed horizontally to the substrate surface 14 . This results in only a small amount of magnetic stray fields reaching into the substrate 12 . This is illustrated by the course of the magnetic field lines 60 shown in FIG. 5.

Due to the large coil cross section 27 that can be produced by means of a standard metallization, a magnetic core as described in EP-A-0 725 407 can be dispensed with.

In Fig. 6, another embodiment of a coil 20 according to Inventive is illustrated. In this coil 20 , the coil axis 26 has an at least approximately closed, circular line. This also gives the entire coil 20 an approximately circular appearance. This coil configuration ensures that, in addition to the coil axis 26 formed as a closed line, the coil start 29 and the coil end 30 are directly adjacent to one another. The coil quality can be further improved by such a configuration of the coil 20 , since the scattering proportion is reduced. The basic structure of the coil 20 according to FIG. 6 corresponds approximately to that of the coil 20 shown in FIGS . 2 to 5, so that the same components are identified with identical reference numerals and reference is made to the explanations for this exemplary embodiment in order to avoid repetition.

In Figs. 7 and 8, now a coil system 70 provides Darge, in which one or more coils 20 of FIG. 6 ver be spent. For the sake of clarity, only a single coil 20 is shown. The coil 20 is in turn part of a microelectronic circuit 10 and arranged within an oxide layer 13 of a chip 11 , the oxide layer 13 being on the substrate surface 14 of a substrate 12 .

In order to be able to implement an efficient lateral shielding of the coil 20 , a series of via stacks 71 are provided which are arranged next to one another in the region outside the coil periphery 72 and are placed around the coil 20 . The via stacks 71 extend parallel to the via contacts 40 .

Similar to the via contacts 40 , the via stacks 71 consist of two or more via elements 75 , between which components 76 of metallization levels are located. The lowest metallization level, as with the coil 20, is the metalization level 24 , while the top metallization level, as with the coil 20, is the metallization level 25 . The standard metalization, preferably the standard metalization with copper, can thus also be used for the production of the via stack 71 . The via stack 71 can be produced simultaneously with the coil 20 .

In contrast to the via contacts 40 of the coil 20 , the via stacks 71 are connected to the substrate 12 via corresponding contacts 50 .

FIGS. 9 and 10 finally show a modified embodiment of a coil system 70 with respect to FIGS. 7 and 8. In this case, have again been designated Ver equal to FIGS. 7 and 8, like components having identical reference numerals.

In addition to the cell system in Figs. 7 and 8, Spu 70 includes the coil system 70 according to FIGS. 9 and 10 an upper shielding plane 73 and a lower Abschir MPlane 74th Standing in the illustrated in Fig. 10 mi kroelektronischen circuit 10 sufficient metallization available, the top metallization plane, in the present case, the shielding plane 73, for vertically Abschir the coil men 20 are used up. In the present exemplary embodiment, the upper shielding level 73 consists of metal. To prevent eddy currents, the upper shielding level 73 is formed as a slotted surface.

For the shielding of the coil 20 downward, the lower shielding plane 74 can be used, which can be formed, for example, as a poly silicon layer or structure with a highly doped substrate. Like the upper shielding plane 73 , the lower shielding plane 74 can also be designed as a slotted surface.

Claims (17)

1. Coil for integration into a microelectronic circuit device ( 10 ), with one or more turns ( 21 ), the turn (s) ( 21 ) by at least segments of two conductor tracks ( 22 , 23 ), each of which is spatially different from one another separate metallization levels ( 24 , 25 ) are formed, and the via contacts ( 40 ) connecting these conductor track (s) ( 22 ) and / or conductor track segments ( 23 ) are / are characterized , characterized in that each via contact ( 40 ) is formed from a stack ( 41 ) of two or more via elements ( 42 ) arranged one above the other. 2. Coil according to claim 1, characterized in that the via contacts ( 40 ) are at least substantially perpendicular to the conductor tracks ( 22 ) and / or conductor track segments ( 23 ). 3. Coil according to claim 1 or 2, characterized in that components ( 43 ) of a metallization level are provided at least between individual via elements ( 42 ) of a stack ( 41 ). 4. Coil according to one of claims 1 to 3, characterized in that the conductor track (s) ( 22 ) and / or the Lei terbahnsegmente ( 23 ) and the via contacts ( 40 ) the cross section ( 27 ) of the coil ( 20th ) limit. 5. Coil according to one of claims 1 to 4, characterized in that the winding ( 21 ) or turns of the coil ( 20 ) forming (s) conductor track (s) ( 22 ) and / or Lei terbahnsegmente ( 23 ) in one Distance of about 4 microns to each other. 6. Coil according to one of claims 1 to 5, characterized in that the conductor track (s) ( 22 ) and / or conductor track segments 823 ) and / or the via elements ( 42 ) and / or between individual via elements ( 42 ) provided components ( 43 ) of a metallization level made of copper, in particular of electrodeposited copper, are formed. 7. Coil according to one of claims 1 to 6, characterized in that the coil ( 20 ) for integration in an on and / or in a substrate ( 12 ) arranged microelectronic circuit ( 10 ) is formed and that the coil axis ( 26th ) is aligned horizontally to the substrate surface ( 14 ). 8. Coil according to one of claims 1 to 7, characterized in that the coil start ( 29 ) and the coil end ( 30 ) of the coil ( 20 ) are arranged adjacent to one another, so that the coil axis ( 26 ) is an at least approximately closed line , in particular a circular line. 9. coil system for integration into a microelectronic circuit 10 , characterized by one or more coils ( 20 ) according to one of claims 1 to 8. 10. Coil system according to claim 9, characterized in that for shielding the coil (s) ( 20 ), a number of via stacks ( 71 ), each of one or more via element (s) ( 75 ) are provided is and that the via stack ( 71 ) outside the coil (s) ( 20 ), in particular outside the coil periphery, are arranged around it. 11. Coil system according to claim 10, characterized in that the via stack ( 71 ) are aligned approximately perpendicular to the coil axis ( 26 ). 12. Coil system according to one of claims 9 to 11, characterized in that at least one shielding plane ( 73 , 74 ) is provided for vertical shielding of the coil ( 20 ). 13. Coil system according to claim 12, characterized in that the shielding plane ( 73 ) is designed as a metal plane. 14. Coil system according to claim 12 or 13, characterized in that the shielding level ( 74 ) is designed as a poly-silicon level or as a structure with a highly doped substrate. 15. Microelectronic circuit with a number of integrated components, at least one of these components being designed as an inductor, characterized in that the component provided as an inductor as a coil ( 20 ) according to one of Claims 1 to 8 and / or as a coil system ( 70 ) is formed according to one of claims 9 to 14. 15. Microelectronic circuit according to claim 15, characterized in that it is formed on and / or in a chip ( 11 ) and that the chip ( 11 ) is formed from a substrate ( 12 ) and at least one oxide layer ( 13 ). 17. Microelectronic circuit according to claim 16, characterized in that the coil ( 20 ) and / or the Spulensy stem ( 70 ) is arranged within the oxide layer ( 13 ).