DD285538A7 - CIRCUIT ARRANGEMENT FOR REINFORCING THE EQUIVALENT VOLTAGE COMPONENT IN A PICTURE SIGNAL - Google Patents

Abstract

The invention relates to the television technology, in which the image signals before or after each galvanic separation, modulation or conversion to be provided again with the correct DC components. The time-selective or certain level-related clamping, which is susceptible to failure of signal components, interference and additional signals, the invention replaces using largely the same circuit means as separation capacitor, voltage comparator with reference voltage, Tiefpaszglied and Verstaerker by comparing with a time average of a period of time by a Differenzverstaerker is used with appropriate comparison voltage, which forms an additional low-pass filter via an output-side resistor with the isolating capacitor and adjusts to the black level in each mode. Fig. 2 {image signal; DC component; Black level; Additional signals; disturbances; Signal failure; Reference voltage; voltage comparator; Tiefpasz; Average; Period}

Description

For this 3 pages drawings

Field of application of the invention

The invention relates to a circuit arrangement for the reintroduction of the DC component. This circuit arrangement is advantageously used in the processing and transmission of image signals, in image display devices, in the modulation of the image signals to a carrier frequency, at the input of A / D converters for image signals and after the demodulation of image signals.

Based on a standardized image signal U "= ₁ V, the transmission parameters in the transmission channel without reintroduction of the DC component must be designed for almost U ₁ , = 2 V quality. In the case of frequency-modulated or digital transmission of the image signal, in order to avoid transmission bandwidths which are too large, it makes sense to assign fixed values to the black value, the synchronizing value and the white value in the modulation range or in the digital range. The prerequisite for this is the reintroduction of the DC component before the modulation. From this, the following demands are derived for the reintroduction of the DC component:

The reference value of the DC component should be the black value or the black shoulder of the image signal.

- If the image signal fails, sin Gieichspannungswert should adjust according to the black level.

- With normal sync signal and additional sound transmission in the image signal and in case of partial interference or failure of the sync signals, the reference value of the DC component should be maintained at the black value.

Characteristic of the known state of the art Ee are generally known circuit arrangements for the reintroduction of the DC voltage value, in which the Image signals are passed through a capacitor and hinte. the capacitor the path of the ü'jer signal with a diode

fixed potential is connected. Depending on the polarity of the diode, the DC value of the signal adjusts itself after the

Capacitor such that either the positive or the negative peaks of the signal receive constant potentials. These Circuitry for reintroducing the black level has several disadvantages; among others, the soft Time constants necessary for the compensation of sudden changes in the DC voltage value of the signals in positive

and negative direction, strongly different from each other.

Such a circuit arrangement (DE-OS 2810706), starting from a low-voltage source, from a Coupling capacitor, a diode and a resistor that biases the diode in flux / direction. During the Synchronous pulses, the diode is conductive and charges the capacitor until a state of equilibrium between in the Pulse time on the diode incoming charge and the then drained via the resistor charge is reached. diodes

have an exact logarithmic characteristic. Since the sync signals are narrow pulses for H-sync and wide

Contain pulses for the V-sync, distortions of the so-called synchronous bottom arise. The narrow ones In order to generate the same charge, pulses must dive deeper into the diode characteristic than the pulse propagates: pulses. A number of known circuit arrangements (such as, for example, DE-AS 2507231 and DE-OS 2828654) for the reintroduction of the DC component use a clamping circuit on the black shoulder of the image signal, for which Klemmimpulse

needed.

These circuits require a proper sync signal, require a synonymous Amplitudensieb Separation of the sync signals and a preparation of the clamping pulses, which in their temporal position each of the Black shoulder of the image signal must be assigned. Another known circuit arrangement for a circuit (DE-OS 3430593) separates to restore the Black levels with a relatively large amount of circuitry after a clamp on the black shoulder the black level

off, prepare it and put it back to the image signal. This circuit arrangement sets a proper

S signal ahead and requires a properly working Amplitudensieb. In the area of the black shoulder for color image transmission, color image signals already have colorant components which are used for the color image Synchronization of the color information are important and their transmission by low-impedance clamping circuits

be affected. This inevitably leads to certain tolerances in the DC component with high-quality clamping circuits for color image signals.

Furthermore, circuit arrangements are known (eg DE-AS1762912), which, starting from the synchronizing signal, the image signal

to re-introduce the DC component to the synchronizing value. On the one hand are for the

Amplitude values of the synchronous level allow larger tolerance values that change the black value and the image content,

On the other hand, these circuits are dependent on a standard synchronous signal. Are during the duration of the horizontal sync signals z. B. additional sound signals integrated into the image channel, so are only temporally small portions of

Synchronization pulses for synchronization available, whereby the effort for the Amplitudensieb as a starting point for the Generation of clamping pulses increases significantly and a clamping on the very short residual signals of the synchronizing component

does not lead to a stable result.

There are also known clamping circuits which clamp at high speed to the synchronizing level (for example, see DE-PS 2418540; JP-OS 60-171871 (A) using comparators and reference voltages. They contain in addition to usual separation stages

controlled current sources, integration and buffer amplifiers or voltage current transformers and their typical

Application field are image storage devices, in which a recovery of the DC voltage value within a line

is required.

In addition to the already mentioned disadvantages of clamping to the synchronizing value, which requires a clean sync signal,

This circuit, because it restores the DC voltage value in each row, generates it, especially if the sync signal is either clean or noisy, due to the different DC values recovered

Line noise in the picture. It is necessary, in addition to such fast clamping circuits, a slow-acting Clamping to arrange, which is equipped with a corresponding time constant, which further increases the effort

elevated.

It is also known a circuit arrangement for determining the value of a reference level (DE-OS 3214756), the one Regulation allowed to a reference value. When using this circuit to re-introduce the DC component in an image signal generates the black level component and the vertical sync signals in the image signal

8afaastastlücke control errors, which lead to image synchronous distortions of the black level.

Object of the invention

The aim of the invention is to avoid the disadvantages of the listed known solutions and to keep the circuit complexity as small as possible.

Explanation of the essence of the invention

An analysis of the technical causes of defects of the known solutions shows that the known circuit arrangements for reintroducing the DC component of the image signal by signal components on the porch and the sync signal are operational only with great circuit complexity in the presence of an exact Schwarzwert- or sync signal remainder and in hard clamping the color carrier in the black value range or through the

Vertical blanking interval and the vertical sync components lead to image-synchronous distortions of the black level and continue to lose the reference value in deformations or disturbances in the sync signal or in the case of failure of the image signal and change the DC component.

The invention is based on the object to realize a circuit arrangement for recovering the DC component of image signals, avoids the Kurzzeitklemmung and uses the proportionate duration of the signal duration to obtain in all operating cases as a reference value for recovering the DC component, the black level and as an operating point for the Further processing of the image signal to stabilize. Starting from a low-impedance voltage source for the image signal at the isolating capacitor, at least one voltage comparator, a black level DC voltage, a low-pass filter and a differential amplifier, at the second input of which there is a further comparison voltage, which is based on a temporal mean value of the synchronous and semiconductor value, the object is achieved in that between the output of the differential amplifier and the Ausgannsseite the separating capacitor is a resistor is connected, which forms a second Tiefpaßglied with this, that between the output of the voltage comparator and the Tiefpaßglied in the course of the first input of the differential amplifier an AND or NAND gate whose second input is connected via a monostable multivibrator, via a NAND gate which is connected to a blocking signal synchronous with the image signal and a differentiating element is connected to the output of a second voltage comparator and there ß the first inputs of both voltage comparators are connected to the output side of the isolating capacitor, while the comparison voltage at the second input of the second voltage comparator between black and synchronous value.

In an advantageous development of the invention, a delay element and a monostable multivibrator can be connected downstream of the NAND gate behind the second voltage comparator and the output of the monostable multivibrator applies the blocking signal, which is synchronous to the image signal, to the second input of the NAND gate or the AND gate. The second voltage comparator can advantageously be followed by a further monostable multivibrator having a time constant corresponding to the H-synchronizing pulse duration whose output is linked to the output of the first voltage comparator via a further NAND gate.

Furthermore, advantageously, the NAND gate also be followed by an additional monostable multivibrator whose inverting output is connected to a transistor which discharges the capacitor of an integrator, which is connected via level converter elements to an input of a NAND gate whose other input directly to the inverting output of this monostable multivibrator and whose output is connected to the second input of the NAND gate before the differential amplifier. The second input of the NAND gate behind the second voltage comparator is then fed back via a separate further monostable multivibrator.

The mentioned developments serve the improved adaptation of the circuit to all possible operating cases and the avoidance of time-critical dimensions.

The particular effect of the invention is that the clamping does not relate to one or more specific times but to periods, as shown in the following explained operation of this circuit. At the first voltage comparator is located at the one input, e.g. at the inverting input, the image signal, which comes from a low-impedance Spannungsquello and is also connected via a capacitor to the output. At the second input of the voltage comparator is a DC voltage corresponding to the desired black level. It is advantageous between the capacitor and the first input of the voltage comparator for the suppression of the color carrier in color image signals a Tiefpaßglied, z. B. an R-C member, switched.

At the output of the voltage comparator is for the Bildsignalantoile whose voltage values are above the black level comparison voltage at the second input, L level, e.g. O V, and for voltage levels below the black level comparison voltage, Η level. The voltage comparator is followed by an AND gate, which advantageously, starting from a second voltage comparator, derived from the synchronizing signals, the first voltage comparator output only for the duration of the horizontal blanking interval in each line, for example, for the duration of about 20% of the line for the generation of the control signal releases. Between the output of the AND gate and the one input of the downstream differential amplifier, a low-pass filter is connected, which consists for example of an R-C member. The other input of the variable gain amplifier is, e.g. connected via a voltage divider, with a defined DC voltage, which is set to a voltage value between the Η value and the L value of the gate output. The ripple amplified DC voltage at the output of the differential amplifier is connected via a resistor to the Ausgangsoite of the capacitor in the image signal path. There arises a stabilized DC component, which refers to the predetermined at the second input of the voltage comparator DC voltage.

It is assumed that the synchronous component of an image signal takes up 10% of the temporal signal sequence and the synchronous and black level component accounts for about 20%. Behind the low-pass filter at the input of the differential amplifier results in a ripple DC voltage whose DC voltage component is proportional to the time relationship of the Η values and L values of the output of the voltage comparator.

If the DC voltage at the second differential amplifier input is set to correspond to the time average of 5% H level and 95% L level at the voltage comparator output, then the DC component of the image signal stabilizes at the synchronous level with a temporally 10% synchronous level component. If, on the other hand, the voltage value at the second differential amplifier input is selected according to a mean voltage of 15% und level and 85% L level at the voltage comparator output, then the DC component of the image signal stabilizes (with temporal portion of synchronous and black value of 20%) to the predetermined at the second input of the voltage comparator DC voltage value corresponding to the black level. Both in case of failure of the sync signal as well as uch the failure of the entire image signal always this black level remains as the reference voltage at the output of the circuit stable. The tolerance of the stabilization is determined by the gap width of the voltage comparator, which is approximately in the range of 1 mV. For an image signal with U "= 1 V, these tolerance values are sufficient.

The second voltage comparator is disabled for the duration of the image content of the line, so that only the line sync pulses are effective and the half line pulses of the V sync pulse mixture are thereby blocked. In this circuit, the control time constants can be optimally adapted. If the synchronizing signal or the entire image signal fails in this circuit arrangement, the second comparator is not activated and the circuit arrangement acts like the basic circuit and stabilizes the output to the predetermined black level. If additional information is stored in the region of the synchronizing signal (for example, ITU sound signals) and signal components which exceed the black value in the positive direction occur, it is advantageous for the duration of these signals, in the synchronous region, to derive the output of the first comparator from the synchronizing signal Add impulse, which corresponds in its control effect to the black level and avoids a false control.

Ausfuhrungsbelsplel

The invention is explained below with reference to exemplary embodiments. In the accompanying drawings show the

1 is a block diagram,

Fig. 2 to 4: block diagrams of various advantageous developments and Fig. 5 and 6: voltage waveforms as a function of time.

As the block diagrams 1 to 4 show, the input signal U, a low-impedance voltage source (not shown) via a capacitor 1 is connected to the output. Behind the capacitor 1 is the image signal at an input of a in Fig. 1 and two voltage comparators (Fig. 2 to 4) 2 and 11 z. B. supplied to the inverting inputs.

It is advantageous for color image signals in front of the input of the comparators or a respective low-pass filter for suppressing the color carrier, e.g. an R-C member 9, 10 and 12, 13, respectively.

At the second input of the voltage comparator 2 is a DC voltage Ui, which corresponds to the desired black level.

The output of the voltage comparator 2 in Fig. 1 is designed so that it at the output for image signal components which are voltage above U, L values, z. B. O V, and outputs a defined output voltage Η values for image signal components that are voltage below U. The same applies to the output of the AND gate 16 (FIG. 2) and the output of the NAND gate 19 (FIGS. 3 and 4), provided they are enabled by the additional electronics.

Between the output of the voltage comparator 2 (FIG. 1), the output of the AND gate 16 (FIG. 2) and the output of the NAND gate 19 (FIGS. 3 and 4) and the one input of the differential amplifier 3 is a low-pass filter , which is formed as an RC element 4,5, arranged. The other input of the differential amplifier 3 is connected to a defined DC voltage U _m , which is set between the L value and the H value of the comparator output or the gate outputs. It is obtained in the example by the voltage divider 6.7 from the operating voltage Ub. The output of the differential amplifier 3 is connected to the reintroduction of the DC component behind the capacitor 1 via the resistor 8 to the output U.

If there is no image signal at the input U, then a DC voltage is present at the output U ₁ which, in accordance with the gap width of the voltage comparator, is about 1 mV relative to U ₁ .

Exceeds the input level of the voltage comparator 2 the positive threshold compared to the reference voltage Ui, this switches at the output to L value and lowers via the low-pass filter 4.5, the differential amplifier 3 and the resistor 8, the output level U, in the negative direction. If the level at this input is more negative than the threshold value, which determines the comparison voltage Ui at the other input of the voltage comparator 2, its output switches to Η value and arises via the low-pass filter 4, 5, the differential amplifier 3 and via the resistor 8 at the Output side of the capacitor 1, an increase of the output level U, in the positive direction. As a result, the output level U. in conjunction with the time constant, which are given by the low-pass filter 4,5, the differential amplifier and the R-C member 8, 1 corresponding to the gap width of the voltage comparator to the predetermined reference voltage.

In the aforementioned condition that about 10% of the temporal signal sequence by the synchronous component and about 20% of the temporal signal flow through the synchronous plus black shoulder shoulder in the blanking claimed, arises at an applied image signal behind the low-pass filter 4.5 at the input of the differential amplifier 3 a undulating DC voltage. Their DC component is proportional to the time relationship of the Η values and L values of the output signal of the voltage comparator 2 or the λ. Character of the gates 16 and 19.

If an image signal from a not shown low-impedance voltage source at the input and the voltage divider 6.7 is set according to a mean DC voltage U _n , 15% und value and 85% L value, then the DC component corresponding to FIG. 5 is based on the predetermined DC voltage value Ui on the black shoulder. The basic circuit according to FIG. 1, despite the large time constant, the black level range and the vertical synchronization signals in the picture change blanking interval, leads to control errors and image-synchronous distortions of the black level.

The advantageously further developed circuits according to FIGS. 2 to 4 show, as common features, a second voltage comparator 11 at one input of which the image signal is also present and whose second input is connected to such a comparison voltage U ₂ that it disconnects the synchronizing signals (see FIG. 5) ). The output of the voltage comparator 11 is a differentiating element consisting of the capacitor 14 and the resistor 15 and a NAND gate 17 connected downstream. Its control at the second input blocks the disturbing equalization pulses and V-sync pulses whose rising edges are in the middle of the line. Controls a sync pulse with its rising edge in the negative direction of the voltage comparator 11, receives its output H-PegθI and controls via the differentiator 14,15 cHs NAND gate 17 with a positive pulse. If the second input of the gate 17 is at Η value, a negative pulse triggered by the rising edge Ae of the H synchronizing pulse, which in FIG. 2 and FIG Delayed the duration of the horizontal blanking sync signal plus black shoulder and then the monostable multivibrator 21 drives. On whose

Output is a negative pulse for the duration of the image content of each line (see Fig. 5), which controls the AND gate 16 and the NAND gate 17. Thus, the outputs of the comparators for the duration of Bildinhblts each line and in the vertical blanking interval for the duration of the spurious balancing pulses and the disturbing portions of the V-sync signals are disabled. If the synchronization signals are missing, the gate 16 of FIG. 2 or the gates 18, 19 of FIGS. 3 and 4 remain open. As a result, the output of the voltage comparator 2 via the low-pass filter 4.5 is connected to the differential amplifier 3 and these circuits operate as the basic circuit already described Fig. 1. The fact that the output of the voltage comparator 2 only for the duration of the horizontal blanking range (sync signal plus Schwarzschulter ), the time constants of the RC elements 4, δ before the differential amplifier 3 and 8,1 after this can be lower.

During the picture content in the temporal line sequence is at the low-pass R-C circuit 4.5 levels and the control voltage drops (see Fig. 5 and 6). At the beginning of the front porch and the sync signal, the enabled voltage comparator 2 switches over and at the low-pass R-C circuit 4,5 is Η level. 6, and raises the DC component of the image signal until, in the region of the rear porch, the voltage comparator 2 returns to the L level in conjunction with the reference voltage Ui. Since the voltage comparator 2 in each row, triggered by the front edge of the synchronizing signal, switches to Η level and corrects the DC component as it reaches the reference value Ui by switching in comparison with Ui within the back porch in the horizontal blanking range, this circuit stabilizes the DC component with a greater accuracy than the gap width of the comparator. The roof waste in each row can be kept in the per thousand range by appropriate choice of the time constant of the control, based on the black and white jump of the image signal.

If additional information (eg ITU) is stored in the horizontal sync pulses and these exceed the black value in the positive direction, a monostable multivibrator between the output of the gate 17 and a NAND gate 19 can be switched on according to FIG. The pulse at the output of the gate 17, which is triggered by the rising edge of the sync pulse, drives the monostable multivibrator 22. This generates for the duration of the additional information within the synchronous signal, a negative pulse which is located at the second input of the NAND gate 19, at whose output, regardless of the output signal of the voltage comparator 2 for this time, a Η level appears. This prevents incorrect control of the DC component in the transmission of this additional information. In the circuit arrangements according to FIGS. 2 and 3, the delay circuit 20 and the monostable multivibrator 21 must be adjusted relatively precisely so that the gates 16; 17; 18, the outputs of the voltage comparators 2 and 11 release shortly before the rising edge of the next horizontal sync pulse. An advantageous circuit arrangement for reducing this effort is shown in FIG. The derived from the rising edge of the horizontal sync pulses negative pulses at the output of the gate 17 control three monostable multivibrators 22; 23; 24. The monostable multivibrator 24 generates a blocking pulse of about ³ A of line length, which blocks the NAND gate 17 with its second input for this duration to suppress the equalizing pulses and the vertical sync pulses in the middle of the line during the vertical blanking interval. The monostable multivibrator 23 generates negative pulses for driving the NAND gate 25 and positive pulses for driving the transistor 26 with the length of the horizontal blanking range (sync signal plus black shoulder), see Fig.5.

The monostable multivibrator 22 is required only in the transmission of information in the sync signal and acts as already described in the circuit arrangement according to Figure 3. If disturbances of the horizontal sync signals are excluded, eliminates the monostable multivibrator 22 and the two NAND gates 18 and 19 can be replaced as shown in Fig. 2 by an AND gate 16 whose second input from the output of the NAND gate 25 Fig.4 controlled is.

The circuit arrangement according to FIG. 4 does not provide pulses in the case of image signals without a synchronizing signal to the monostable multivibrators 22, 23 and 24. The transistor 26 remains locked, via a resistor 29 and diodes 32, the transistor 27 is opened, thus switching the input of the NAND gate 25 to the L level. The output of the NAND gate 25 turns on the NAND gate 18 and since the monostable multivibrator 22 does not provide blocking pulses, the NAND gate 19 is also turned on. The circuit operates as the basic circuit Fig. 1 and stabilizes image signals without sync signal to black level and also keeps the black level with respect to Ui constant without input signal. If synchronizing signals are present, the transistor 26 is driven by positive pulses of the monstable multivibrator 23. He discharges the capacitor 28 and thus blocks the transistor 27. The time constant of the RC circuit 28,29 is tuned so that when a line-frequency pulse train, the transistor 27 remains locked and the NAND gate 25 via the resistor 30 at an input Η value is switched. For the duration of the horizontal blanking isi is released by the negative pulse of the monostable multivibrator 23 via the NAND gate 25, the output of the voltage comparator 2 to the gate 18. The stabilization of the DC component of the image signals is carried out as already described in FIG. 2.

Claims (4)

1. Circuit arrangement for reintroducing the DC component into an image signal after their separation using a separator capacitor, at least one voltage comparator, a Schwarzwertvergleicherspannung, a low pass member and a differential amplifier, at the second input of a further comparison voltage is based on a time average of the synchronous and Black value is related, characterized in that between the output of the differential amplifier (3) and the output side of the separating capacitor (1), a resistor (8) is turned on, which forms with this a second Tiefpaßglied that between the output of the voltage comparator (2) and in the course of the first input of the differential amplifier (3) is an AND or NAND gate (16; 18) whose second input via a monostable multivibrator (21; 23) with a synchronous to the image signal blocking signal via a linking NAND gate (17) and a differentiating member (14; 15) is connected to the output of a second voltage comparator (11) and that the first inputs of both voltage comparators (2; 11) are connected to the output side of the isolating capacitor while the comparison voltage (U ₂ ) is connected to the second input of the second voltage comparator (11) Black and sync value is. 2. A circuit arrangement according to claim 1, characterized in that the NAND gate (17) behind the second voltage comparator (11), a delay element (20) and a monostable multivibrator (21) are connected downstream and that the output of the monostable multivibrator (21) to the image signal synchronous lock signal to the second input of the NAND gate (17; 18) and the AND-gating (16) sets. 3. A circuit arrangement according to claim 1 and 2, characterized in that the second voltage comparator (11) is followed by a monostable multivibrator (22) with a time constant corresponding to the H-sync pulse duration whose output via another NAND gate (19) to the output the first voltage comparator (2) is linked. 4. A circuit arrangement according to claim 1 and 3, characterized in that the NAND gate (17) in addition a monostable multivibrator (23) is connected downstream, the non-inverting output to a transistor (26) verb. which discharges the capacitor (28) of an integrator (28; 29) which is connected via level converter elements (27; 30; 31; 32) to an input of a NAND gate (25) whose other input is directly connected to the inverting one Output of the monostable multivibrator (23) and whose output is connected to the second input of the NAND gate (18) and that the second input of the NAND gate (17) via a separate monostable multivibrator (24) is fed back.