DD271410A1 - CIRCUIT ARRANGEMENT FOR IMPLEMENTING INTERFACES FOR SYNCHRONOUS PROCESSES IN PUBLIC DATA NETWORKS BETWEEN DATA END INSTRUMENTS AND DATA TRANSMISSION DEVICES - Google Patents

Abstract

The invention relates to a circuit arrangement for the implementation of interfaces for synchronous methods in public data networks between data terminal equipment (DTE) and data transmission facilities (DUeE), in particular the implementation of the interface X.21 a DEE to interface V.36 DUeE a possibility for Pruefschleifenbildung according to V.54 , According to the invention, the control of the (DUeE) essentially the interface lines directly or via the combinatorial circuits (6, 7, 8) connected to each other. For switching on test loops, the corresponding bit sequence is detected in a recognition circuit (1) and converted via the flip-flops (4, 5) into the associated signals (140, 141). The test loops are switched off by the monitoring of the lines (C) and (T) by means of a detection circuit (1) and subsequent activation of reset circuits (2, 3). The display of local or remote test loops via a flip-flop (9) and the subsequent combinatorial circuit (7). Fig. 1

Description

Modern DEE have interfaces according to recommendation X.21, whereby the definition of the interface lines according to X.24. Essentially the following lines are used: line for the operating earth or return line (G), line for the transmitted signal (T), line for the received signal (R), line for the control signal (C), line for signaling signals (I), Line for the send step clock (X2) and line for the receive step clock (Y).

An interface according to the CCITT recommendation V.24 or V.36 has a line for the operating earth (102), for the transmission data (103), for the reception data (104), for the signal transmission part turn on (105), for the signal Ready to transmit (106), for the ready signal (107), for the received signal level (109), for the transmission step (114) and for the reception step (115) on.

From WO 85/05519 an arrangement is known, with the help of which, inter alia, the cooperation of data terminal equipment according to V.24 with data transmission facilities according to X.21 in services with circuit switching is possible. The actual data transfer phase takes place via a serial input / output module (SLO). A parallel input module (PIO) is used to establish the connection with the help of a dialing procedure, for which the static state of the X.21-Schmittstellenstgnale must be evaluated. The arrangement and the method described do not include the control sequences for looping. In principle, a modified method can be used for loopback control. It would be disadvantageous that different software versions for a X.21 or. a V.36 port controller must be provided. This is associated with an increased programming and program maintenance effort.

Object of the invention

The object of the invention is to realize an interface conversion from X.21-DEE to V.36-DUE, including the possibility of loopback design with minimal hardware overhead, without the need for different software versions for X.21 and εіpеѴ.Зb line termination control.

Explanation of the essence of the invention

The object of the invention is to provide a circuit arrangement for implementing the interface according to X.21 a DEE in an interface to V.36 of a DÜE in public data networks in services with leased lines, with the possibility of looping test should exist. The evaluation of the parallel control signals necessary for the loop test should be carried out without additional PIO and without changing the software.

According to the invention the object is achieved such that the lines X2, C and T of the interface X.21 are connected directly to a detection circuit for certain bit sequences. The line T is still connected to the line 103 and the line X 2 is still connected to the line 114 of the interface V.36. The lead C also leads to an input of a first and a second reset circuit and to an input of a first combinational circuit The first output of the detection circuit is connected to the set input and the second output of the bit sequence detection circuit is via the first reset circuit to the reset input of a first flipflop The third output of the detection circuit is connected to the set input and the fourth output is connected via the second reset circuit to the reset input of a second flip-flop whose output is coupled to line 140. Line I is via a second combinational circuit with the line 109 and the line Y is connected directly to the line 115. The line R is connected to a third combinatorial circuit which is coupled to the line 104 and the output of a third flip-flop Line 114 and line 142. Line 142 is also connected to the first combinational circuit whose output is applied to line 105. The operation of the circuit arrangement according to the invention can be divided essentially into three sections. First, the operational readiness is to be displayed and the data transmission device to be controlled. If data is transmitted from the DEE (X.21) to the DÜE (V.36), the transmitting part is switched on via the first combinational circuit with the signal of the control line C. The transmission data is transmitted directly from line T on line 103. In the opposite direction, the received signal level on line 109 is converted by means of the second combinatorial circuit in the message signal on line I. The receive data arrive via the third combinatorial circuit from the line 104 on line R. Transmit and receive step clock are transmitted directly.

Secondly, the switching on and off of a remote or local test loop should take place. When turned on, the detection circuit recognizes the incoming on line T bit sequence to form the corresponding loop in connection with the state of the control line C. Accordingly, then the first or second flip-flop is set and on line 141, the formation of a near or on line 140 a remote loopback. The switching off of the loops is carried out according to CCITT recommendation by a time-defined interruption of the data stream on the transmission line (loop commands) or after the transmission of test data by inactivating the line C. By continuous monitoring of the lines T and C by the detection circuit and the first and second Reset circuit is effected with appropriate control, the turning off of the loops by the first and second reset circuit by the first and second flip-flop are reset, with which the interface signals 141 or 140 are inactive. Third, the display of test conditions should be done. A distinction is made between the display of test loops switched by the local unit and the test loops activated by remote units. The display of loops, which were turned on by the local unit, according to the invention, in that after activation of the test indicator (signal 142) by the DÜE, the signal 105 (transmit part turn on) is activated via the first combinatorial circuit, the Schleifenschaltkommando the line T. is fed directly via line 103 of the DÜE and is returned via the established loop through line 104 and via the third combinatorial circuit therewith line R of the X.21 interface and recognized as a switched loop. With a corresponding control state of the line C, test data of the line T are received on the line R. To indicate the loop desired by a remote DTU, the third flip-flop, upon activation of the interface signal 142 (activation of the test indication), generates a corresponding control sequence which is supplied via the third combinatorial circuit on line R to the DEE.

The inventive circuit arrangement may preferably be designed such that the detection circuit is realized by an 8-bit shift register and a first and second comparator connected in parallel at its output, wherein each comparator output leads to an OR circuit via a respective D flip-flop The first and the second reset circuit are formed in principle by a payer and a parallel connected to the output of the first and second decoder The output of the OR circuit leads to the payer whose clock input is also connected to the line X2 (transmit clock) The output of the first and second the second decoder is respectively connected to the D input of the first and second flip-flops, at the clock input of the Sendeschnttakt of line Π 4 and at which Rucksetzeingang the negated by an inverter control signal C is applied

exemplary

The invention will be explained in more detail below with reference to exemplary embodiments

1 is a block diagram of the inventive solution and

2 shows a preferred embodiment of the inventive solution

1 shows the solution according to the invention, which is arranged between the interface X 21 of the data terminal device and the interface V 36 of the data transmission device. The data transmission device also has an interface for test looping according to V 54 with the lines 140 (remote loop for point-to-point Connections), 141 (local loop) and 142 (test display) to The data transmission takes place on fixed connections (leased lines) in full-duplex mode. No dial-up network is performed

The lines X 2, C and T of the interface X 21 are connected directly to the detection circuit 1 The line T is still connected to the line 103 and the line X2 is still connected to the line 114 of the interface V 36 The line C also leads to a Input of the reset circuits 2 and 3 as well as an input of the combinatorial circuit 8 The line I is connected via the combinational circuit 6 with the line 109 and the line Y is directly connected to the line 115. The line R is connected to the combinational circuit 7, the coupled to line 104 and to the output of flip-flop 9. It is connected to line 114 and line 142. Line 142 is also connected to combinational circuit 8 whose output is applied to line 105. The first output of detection circuit 1 is at the set input and the second output of the detection circuit is connected via the reset circuit 2 to the reset input of the flip-flop The third output of the detection circuit 1 is connected to the set input and the fourth output is connected via the reset circuit 3 to the reset input of the flip-flop 5 whose output is coupled to the line 140 circuit according to the invention are distinguished essentially three Tetlaufgaben

1 Display of the operational readiness and control of the data transmission device

2 Turn on or off a remote or local test loop

3 Display of test states

The subtask "Displaying Betnebsbereitschaft and controlling the data transmission device" is inventively solved with the help of combinatorial circuits 6,7 and 8

Line T in the conversion directly forms V 36 interface signal 103, step clock lines 114, 115 form the X 21 interface signals X 2 and Y. The state of interface line I is mainly through combinational circuit 6 through signal 109, line R through the combinational circuit 7 controlled by the signal 104 and the line 105 via the combinatorial circuit 8 by the signal C.

The detection circuit 1 serves to detect the typical bit sequences for the loop control (X21 loop switching commands). The reset circuits 2 and 3 are for the Grinding type specific reset circuits Loop switching commands of the line T in connection with the state of the line C are detected in the recognition circuit 1. They can be realized by digital comparators, PLL circuits or by analog time comparison circuits. Depending on the recognized command type in the recognition circuit 1, the flip-flop

4 or 5, the interface signals 141 or 140 are activated

A cancellation of the loops is carried out according to CCITT recommendation by a time-defined interruption of the data stream on the transmission line (loop commands) or after the transmission of test data by inactivating the line C By constant monitoring of the lines T and C by the detection circuit 1 and the reset circuits 2 and 3, with appropriate control, the switching off of the loops by the reset circuits 2 or 3 is effected by resetting the flip-flops 4 or 5, whereby the interface signals 141 or 140 are inactive. For the display of test states, two sequences are distinguished in principle - a) the display of Loops that have been turned on by the unit under consideration and b) Display a loop that has been activated by the remote DEE / DUE

According to the invention, the display of loops according to a) takes place in that, after activation of the test indication (signal 142) by the DUE, the signal 105 is activated, the loop switching command is applied to the line T via line 103 of the DUE and via the established loop by line 104 and thus line R of the X 21 interface is returned and recognized as a switched loop At entspechendem control state of the line C test data of the line T on the line R are received to display the loop to b) generates the flip-flop 9 after activation of the interface signal 142 a corresponding control sequence, which is supplied via the combinatorial circuit 7 on the line R of the DEE on the basis of Figure 2, the implementation of an X 21 interface to V 36 interface is explained in more detail, wherein the interface to X 21 part of a data terminal (DEE) and the Interfaces according to V 36, V 54 Part of a data transmission device (DU E) are

The signals of the X.21 interface transmit (line T), transmit step clock (line X2) and receive step clock (line Y) directly form the V.Se interface signals 103,114,115. The state of the interface line I is controlled mainly by the signal 109, the line R by the signal 104 and the line 105 by C.

The V.Se interface signal 107 is not evaluated because the readiness of the DTU through line 104 (binary 1 state), 109 (OFF state), corresponding to the X.21 interface with χ = 1 and i = OFF is signaled. Assuming that the data is transmitted between the subscribers on dedicated lines (leased lines) in full-duplex operation and the line control of the X.21 interface by a serial input / output circuit (SIO) with limited control options, the Ѵ.Зb interface signal 106 not considered.

For test loop or test loop activation of types 3 and 2, according to CCITT Recommendation X.21 on line T alternating groups, type 3 four binary 0 and binary 1, type 2 two binary 0 and binary 1 in conjunction with C = OFF sent for a maximum period of 2s. Depending on the type, these loop switching commands are recognized in the local or remote DÜE and sent back on line R if i = OFF. The remote DÜE transfers closed loop 2 to the DEE on line R 0101 ... at i = OFF. Test data is sent at с = ON and received at i = ON on line R. The loops are canceled by terminating the loop switching command at с = OFF or at с from ON to OFF. The control of the loop switching commands is performed according to CCITT Recommendation V.54 through the interface lines 140 (loop 2, far loop), 141 (loop 3, local loop), and through the test display 142. The El N state on line 142 signals the fabrication of the test state, subsequent test data on line 103 (105 in the ON state) are looped back to line 104 (109 in the ON state).

The implementation of the X.21 control information for test loop activation on loop switching commands of Recommendation V.54 will now be explained in more detail with reference to FIG.

In this case, the detection circuit 1 shown in FIG. 1 is realized by an 8-bit shift register 10, the 8-bit comparators 11 and 12 connected in parallel at its output, the D flip-flops 13 and 14 and an OR circuit. In this case, the output of the 8-bit comparator 11 is connected to the D input of the D flip-flop 14. At the clock inputs of the D-flip-flops 13, 14 of the transmission step clock X2 and the reset inputs to the control signal C of the interface X.21. The outputs of the D flip-flops 13 and 14 are connected to the OR circuit 18.

The reset circuits 2 and 3 are principally formed by the counter 15 and the decoders 16 and 17. The output of the OR circuit 18 leads to the counter 15 whose clock input is also connected to the line X2 (transmission step clock). The output of the counter 15 is connected to the decoders 16 and 17. The input of the decoder 16 is further connected to the output of the 8-bit comparator 11 and the output of the D flip-flop 13. Accordingly, the input of the decoder 17 is further connected to the output of the 8-bit comparator 12 and the output of the D flip-flop 14. The output of the decoder 16 or 17 is connected to the D input of the flip-flop 4 and 5, at the clock input of the transmission step clock of line 114 and at whose reset input the negated by the inverter 19 control signal C is applied. Information on the loop switching command is taken over the line T of the X.21 interface at с = OFF in the 8-bit shift register 10 and fed to the 8-bit comparators 11 and 12. Depending on the type of command, the flip-flop 13 or 14 is set, so the 6-stage counter 15 is activated by the Schrittakt 114. After each 8 bits or 4 bits, the counter output is compared with the comparator outputs in the decoders 16 and 17. If the comparator output is inactive, flip-flops 13, 14 and counter 15 are reset; when the comparator output is active, the counter 15 is still clocked by the signal 114. At count 32 and 24, the flip-flop 4 or 5 is set. Flip-flop 4 switches line 141, flip-flop 5 switches line 140 to the ON state. After the loop is established in the DUE, line 142 enters the ON state. By the set flip-flop 4 or 5 and line 142 in the ON state, the line 105 is switched by the combinational circuit 8 in the ON state. Although the signal 109 has assumed the ON state by the ON state of the signal 105 and the ON loop, the line I remains OFF by с = OFF and line 140 or 141. Due to the ON state of the line 105, the loop switching command is supplied to the line T via line 103 of the DUE and fed back via the established loop through line 104 and thus line R of the X.21 interface. The switched loop is detected in the DEE after X.21.

When с = ON and i = ON (line I at loop established controlled by line C and the ON state of line 109), transmitted test data of line T is received on line R. If line C is not brought into the on state after the recognized loop has been established, the loop can be triggered by not sending the loop switching command at t Φ 0 according to the CCITT recommendation. After the ON state of the flip-flops 4 or 5, the output of the comparators 11 or 12 continues to be monitored for the continuous loop switching command. After absence of the bit pattern, the counter 15 is activated, after 32 bits at loop 3 and 24 bits at loop 2, the flip-flop 4 or 5 is reset, so that the interface signal 141 or 140 assumes the OFF state. By the OFF state of the flip-flops 4 or 5, the flip-flops 13,14 and the counter 15 are reset and switched via the combinatorial circuit 8 and line 105 in the OFF state. If r Φ O and i = OFF, the data transfer phase can be entered with с = ON. The binary 1 of the line 104 becomes operative on the line R with the OFF state of the line 142 by coupling in the combinational circuit 7. If line 109 is in the OFF state, line I also assumes the OFF state via the combinatorial circuit 6. When the remote DTC closes loop 2, the DEE on the line 142 on line 109 signals OFF in the OFF state that the DUE is under control and not ready to perform a data transfer. According to CCITT Recommendation X.21, this state is to be communicated to the DEE by r = 0101 ... if i = OFF. The bit sequence formed by flip-flop 9 derived from the step clock of the line 114 is supplied to the line R together with the ON state of the line 142 and flip-flops 4 and 5 in the OFF state via the combinational circuit 7. Line I is kept OFF by the OFF state of line 109 via combinational circuit 6.

With the solution according to the invention, an efficient circuit for interface conversion has been created with the help of which, based on uniform software, both X.21 and also V.36 connection controllers can be realized. Thus, this solution is also suitable for the construction of simple interface adapter for coupling industrially manufactured devices with X.21 interface to devices with V.36 interface. This is of particular importance for the construction of automated data networks using switching technology with X.21 interfaces, since the transmission technology (MODEM) according to V.36 standard can be used in a favorable manner.

Claims (2)

1. Circuit arrangement for the implementation of interfaces for synchronous methods in public data networks between data terminal equipment (DTE) and data transmission equipment (DUE), in particular for the implementation of the interface X.21 of a DEE in the interface V.36 of a DÜE with the possibility for test loop formation according to V.54, characterized in that the lines [Xl], (C) and (T) of the interface X.21 are connected directly to a bit control sequence detection circuit (1), that the line (T) is further connected to the line (103) and the line (X2) is further connected to the line (114) of the interface V.36, that the line (C) also to an input of a first and a second reset circuit (2, 3) and to an input of a first combinational circuit (8) leads that the first output of the detection circuit (1) with the set input and the second output via the first reset circuit (2) with the reset input of a first Fl ipflops (4) whose output is coupled to the line (141), that the third output of the detection circuit (1) with the set input and the fourth output via the second reset circuit (3) with the reset input of a second flip-flop (5) whose output is coupled to the line (140), that the line (I) via a second combinational circuit (6) with the line (109) and the line (Y) is connected directly to the line (115), in that the line (R) is connected to a third combinatorial circuit (7) whose first input is coupled to the line (104) and whose second input is coupled to the output of a third flipflop (9) connected to the line (114) and the line (142) is connected, wherein line (142) is also connected to the first combinational circuit (8) whose output is applied to the line (105). 2. Circuit arrangement for the implementation of interfaces for synchronous methods in public data networks between data terminal equipment (DTE) and data transmission equipment (DÜE) according to item 1, characterized in that the detection circuit (1) by an 8-bit shift register (10) and a parallel at its Output connected first and second comparator (11,12), wherein each comparator output via a respective D flip-flop (13,14) leads to an OR circuit (18), is realized that while the line (X2) with the clock inputs and the line (C) is connected to the reset inputs of the D flip-flops (13, 14), in that the first and second reset circuits (2, 3) are connected by a counter (15) and a first and second decoder connected in parallel at the output thereof ( 16,17) is formed, that the output of the OR circuit (18) leads to the counter (15) whose clock input is also connected to the line (X2) that the output of the D flip-flop (13) or (14) and the output of the comparator (11) or (12) to the input of the decoder (16) or (17) leads that the output of the first and the second decoder (16,17) is connected to the D input of the first and second flip-flops (4, 5) at whose clock input the transmission step clock of line (114) and at its reset input by a negator (19) negated control signal (C) is applied, that the output of Flip-flop (4,5) is connected to the inputs of the combinatorial circuits (6,7,8), and that the clock input of flip-flop (9) is connected to the line (X2) and the signal input is connected to its own negated output. For this 2 pages drawings Field of application of the invention The invention relates to the connection of data terminal equipment (DTE) to data transmission equipment (DUE) in public digital data networks, where DUE and DEE have different interface characteristics from each other. In particular, the conversion of the interface X.21 of a DEE to the interface V.36 of a DUE with the possibility of a test loop formation according to V.54 is considered. Characteristic of the known state of the art The work of public digital data networks is regulated in particular according to the recommendations of the CCITT. These recommendations are constantly evolving. Problems arise when devices with interfaces are to be coupled according to different CCITT recommendations. So z. B. Recommendations for data transmission over the telephone network (V series) known. For the data transmission via digital public data transmission networks further recommendations (X-Sene) were developed.