DD255612A1 - METHOD AND DEVICE FOR INFORMATION PROCESSING IN DEVICES AND PROCESSES - Google Patents

Abstract

The invention finds application in automation devices and in process automation. The veraenderliche logic (program) is included only in some excellent modules and will be transferred to the rest. All modules can contain processors. The system is suitable for small to large information processing tasks. Thus, it can be used in process or in a centralized form. The modular character allows the system to cover broad information processing classes, making the costs of each task relevant. Two module concepts are assumed, modules with exchangeable memories, whereby the logic (program) for the configuration of the latter contain. However, all modules are already preconfigured, due to the varying logic (program), the adaptation to the specific task takes place. The modules are designed autonomously. If one or more modules fail, the system behavior is not significantly disturbed.

Description

For this 5 pages drawings

field of use

The invention relates to a method and device for processing information in devices and processes and has application in automation devices and in process automation.

Characteristics of the known prior art

For several years, multiprocessor systems have been used in information processing. A special Enwickiung thereby represent the modular multiprocessor or multi-computer systems. These systems are characterized by the fact that they are composed of several modules and preconfigured to a high degree. Their interchangeability makes it possible to cover a relatively wide range of tasks. It is not necessary to modify system-specific components. In general, one starts from a master-slave principle, i. h., there is a master module and several slave modules. The master module is characterized by the fact that it takes over the control and controller function of the system and thus contains the entire intelligence of the system. Characteristic of this system structure is the uMAC 4000 system (analogue dialogue 15-1 1981).

For the arrangement of the modules within the system one proceeds either from Party-Line-Conection or from Radial-Line-Conection, whereby the Party-Line-Conection found larger application. The Kontron-Kobus system has a typical party-line arrangement (ELECTRONIC information 11/82). With this arrangement, one already goes the way of distributed intelligence. In order to increase the system universality, it was only in DE 3029246 that the modules were assembled with:

Initialization phase performed. This facilitates the adaptation of new modules. In DE 2842085 the modular:

System adapted to a central computer, which assumes the master function. This makes it possible to use the functions of

Central computer, which are also outside its tasks within the modular system. Disadvantage of said arrangements is that one always starts from a master, which is in the form of a module or a higher-level system (eg central computer). As a result, if the master fails, the system is no longer functional or significantly disturbed. The modules of the individual systems are designed so that the configuration is fixed. Changing their function within their task class is therefore impossible or difficult. For all systems, the design is difficult to understand since it was only tailored to specific task classes. The advantage in DE 3029246 of the retrofittability of modules has the disadvantage that thereby the programming of the modules previously not closed solvable.

In the system presented in DE 2843085, the presence of a central computer is necessary. This brings on the one hand the disadvantage that when using the system a special central computer must be present and on the other hand the

Process proximity is lost. In Kontron-Kobus, the path of distributed intelligence has been taken, but this,

is limited exclusively to the function of the slave modules after their assembly. The uMAC 4000 system has all; already mentioned disadvantages and is a modular system still in the conventional sense.

Object of the invention 'i

The aim of the invention is a system for distributed information processing, which is suitable for smaller, medium and large;

Information processing tasks is universally applicable. \

It will find application both near the process and in centralized systems. The cost of the system is the j

relevant tasks relevant. j

Decentralized information processing improves reliability. j

Explanation of the essence of the invention

The object of the invention is to provide a method and a system for distributed information processing in which the variable logic (program) is contained only in a few excellent modules and can be used in all modules of processors.

Its modular character is intended to create a particularly reliable system that tolerates the failure of subscribers both during initialization and during operation. According to the invention, the object is achieved in that the logic (program), which requires the information processing of the modules of the level 1, from the proportion that is relevant to all information processing functions of the target process class and for the internal traffic, and a proportion that is adapted for adaptation the information processing to the concrete process is assembled, whereby this second part of the logic (program) of the level 1 modules is stored in level 2 modules. The internal traffic between arbitrary modules is handled by a data channel described by allowing traffic between any level 1 and level 2 modules in both directions and the management of the data channel being organized such that the failure of modules is the traffic relations does not interfere with the other modules, transferring over the data channel both the part of the logic (program) contained in level 2 modules and needed for generating the overall function of the level 1 modules, as well as the traffic of data of the information processing function between Modules unwinds.

All modules have a processing circuit, one non-removable memory with the logic (program) for the information processing function of the target process class and the realization of the internal traffic, the modules of the level 2 exchangeable memories for the logic (program) of the information processing of the concrete process, the modules of the Level 1 is a read / write memory for receiving the part of the logic (program) transferred to them from the level 2 modules. Furthermore, the level 1 modules have an input S / output interface. The processing circuitry in the level 1 and level 2 modules may be similar. The processing circuit for the information processing function of the target process class and the realization of the internal traffic for all level 2 modules can be realized by single-chip microcomputers and the non-exchangeable memory can be contained in the single-chip microcomputer or connected via a memory expansion interface. The read / write memory used to acquire the logic (program) transferred from level 2 modules to level 1 modules may be included in the single-level microchip computer of the level 1 modules. Similarly, the input-output interface of the level 1 modules may be partially or completely implemented by the single chip microcomputers. During system commissioning

In all modules, only the data channel management is active. The information processing function becomes active only after the transmission of the logic (program) from level 2 to level 1 modules.

embodiments

The invention will be explained in more detail with reference to an embodiment. In the accompanying drawings show:

FIG. 1a: Principle structure of the method (diced blocks addable modules)

Figure 1 b: Principle structure of the device

Figure 2: Representation of a special level-2 module

Figure 3: Representation of a special level 1 module

Figur4: The embodiment underlying the principle

The principle of the figure shows a device of the method. The device (module system) consists of 4 modules 22, 23, 24, 25 of which are 2 modules of level 1 modules 24, 25 and 2 modules of level 2 modules 22, 23. The level 1 and level 2 modules have the same processing processor - a single-chip microcomputer. The single-chip microcomputer has 4 input / output ports 21.8., 21.9., 21.10., 21.11. Furthermore, it has an internal RAM area 21.12. and an internal ROM area 21.13. Inputs 0 and RESET are controlled by the logic 21.6., 21.7. occupied in order to achieve a defined work of the single-chip microcomputer. About TOR 0.1 21.8., 21.9. becomes an extreme program memory 21.1., 21.2. connected. For memory selection, an address decoder 21.3. used. For the latching of the low-order addresses, an address latch 21.5. used, which is controlled via the control logic. The following single-chip microcomputer output signals enter the control logic:

AS (address strobe) DS (data strobe) R / W (read / write)

P / D (program / data memory select)

The external memory drive is used only in the level 2 22,23 modules. Gate 3 has a serial input channel (s' ⁿ ) and a serial output channel (s ^out ). The serial I / O is connected to a serial bus via a galvanic isolation 21.4. coupled. In the modules of level 1 24,25 the gates 0 ... 3 21.8., 21.9., 21.10., 21.11. Interfacelogics of the module's task class 21.14. connected. All modules are coupled via the serial bus 48. Furthermore, all modules have a UART for the bus communication 38,39,40,41. The modules are named after their task class. Thus, the modules 22, 23 are processing modules, where module 22 is processing module 1 and module 23 is processing module 2. Module 24 is an incremental module and module 25 is a communication module. The processing modules are, by nature, level 2 modules, ie modules with removable memories 42, ..., 45. On the memory 42 is the logic (program) for processing data supplied by the incremental module (digital filter). On the memory 44 is the logic (program) for communication-dependent preparation of the measured value corresponding to the key operated in the communication module (display: weight or number of pieces). Furthermore, the address of the module for the result display (address of the communication module) is located on memory 44. On memory 43 is the logic (program) for the preparation of incremental data, which are processed in the incremental module (averaging, zero point corrector). Furthermore, there is the destination address for the processed data (processing module 1). On memory 45 is the logic (program) for configuring the communication module (keyboard size 16, display 8-digit 7-segment and quasi-analog bar display). Furthermore, there is the destination address of the key codes (processing module 2). From this it can be deduced that the operating modes of the other two modules (modules of level 1) are determined on the memories of the processing modules and thus the adaptation to the specific process takes place. Logic 6 (program) of memory 43 and memory 45 is transferred to the non-volatile memories (RAM) of modules 24,25. These memories are contained in the single-chip microcomputer (see also 17a, 17b). The two modules become workable with the logic (program) located in the non-removable memories (PROM). In the non-removable memory (PROM) of the communication module is a communication interpreter and in the non-removable memory (PROM) of the incremental module is an interpreter for analog signal processing. To the interface of the incremental module 36, a weighing sensor 46 is connected and to the interface of the communication module, a display 47 is connected. The two interfaces are as already the memory partially contained in the respective single-chip microcomputers.

How the system works: After the system has been initialized, all modules are configured. Via XI and X2, the incrementally encrypted measured values of the weighing sensor are adopted. In the incremental interface, they are then recoded into a parallel data format. From there, the data is transferred via a port to the single-chip microcomputer, where the data is then processed. The averaged and zero-corrected data are sent to the processing module 1. Before the incremental module is allowed to send, it must have the transmission permission transmitted cyclically. The send address (destination address) was transferred during initialization. The processing module 1 receives the processed data and further processes it (digital filter, standstill control). The further processed there data is sent to the processing module 2, if processing module 1 has the right to send. The processing module 2 then converts the data into pieces or transfers them to the communication module without interference, given a corresponding keypress of the keyboard. the processing module 2 sends, if it has the right to send, the communication module, the corresponding data. In the communication module, the prepared data is then displayed either on the quasi-analogue bar or or on the eight-digit 7-segment display, depending on the keypress. Furthermore, another data format can be set via the keyboard. This applies to corresponding weight indications, z. Mg, g, kg. In this system configuration, the possible failure of the processing module 2 has been considered as follows: The processing module 1 additionally contains on the memory 42 a minimal logic (program) for configuring the communication module. Thus, upon detection of the failure of the processing module 2, the data will be taken directly from the

Processing module 1 sent to the communication module. In this system configuration, it is further possible to consider the failure of the processing module 1 as follows:

Analogous to processing module 1 is also in the processing module 2 to memory 44 a minimal logic (program) for the acquisition of the data of the incremental module and its initialization. In the event of failure of the processing module 1, the data is thus sent directly to the processing module 2.

In both failure modes, the respective failure is displayed. In case of failure of both processing modules, the basic state (as state after RESET) is assumed when detected. There is also a logic (program) for detecting the failure of the incremental module, which is then also displayed. In case of failure of the communication module, an error detection is not necessary because the failure is immediately recognizable there.

Claims (9)

Method for processing information in devices and processes, characterized in that the logic (5.1., 5.2.) (Program) required for the information processing of level 1 modules (5, 6, 7, 8) consists of one share (5.2), which is relevant for all information processing functions of the target process class and for the internal data traffic, and a part (5.1.), Which serves to adapt to the information processing to the concrete process, is composed, whereby this second part of the logic (program) of the level 1 modules is stored in the modules of the level and transmitted to the level 1 modules. 2. The method according to claim 1, characterized in that the internal traffic between any modules via a data channel (20) is handled, which is characterized in that the traffic between any modules of the level 1 (5,6,7,8) and level 2 (1,2,3,4) is possible in both directions and the management of the data channel is organized so that the proportion of arbitrary modules does not destroy the traffic relationships of the other modules, whereby via the data channel both the part of the logic (program ), which is included in the modules of level 2 (1.1.) and is needed to generate the overall function of the modules of level 1 (5.1.), as well as the part that handles the traffic of data of the information processing function between modules. 3. The method according to claim 2, characterized in that after system commissioning in all modules of the level 1 and level 2, only the data channel management is active and the information processing function only after transmission of the logic (1.1., 5.1.) (Program) of the modules of Level 2 (1, 2, 3,4) becomes active on the level 1 modules (5, 6, 7, 8). Method according to claim 1, characterized in that the part of the logic (program) (1.1., 5.1.) Of the level 1 modules (5, 6, 7, 8) of level 2 modules (1, 2, 3 , 4) can be changed during the operation of the information processing function, wherein the transmission of data and logic (program) (1.1., 1.2., 5.1., 5.2.) With the same data format and is distinguished by codes of a corresponding code field , 5. Device for processing information in devices and processes, characterized in that all modules of the level 1 (5,6,7,8) and the level 2 (1,2,3,4) a processing circuit (9,15), respectively a non-exchangeable memory (10a, 10b, 17a, 17b) with the logic (program) for the information processing function of the target process class and the realization of the internal data traffic (20), the modules of level 2 an exchangeable memory (12, 13) for the logic (Program) the information processing of the concrete process, the level 1 modules a read / write memory (17a) for receiving the part of the logic (program), which is transmitted to them by level 2 modules and an input-Z output Interface (18). 6. Device according to claim 5, characterized in that all modules of the level 1 (5,6,7,8) and the level 2 (1, 2,3, 4) have a similar processing circuit (9,15). 7. Device according to claim 5 to 6, characterized in that the processing circuit for the information processing function of the Zielprozeßkiasse and the realization of the internal traffic for all modules of the level 1 (5, 6,7,8) and the level 2 (1,2, 3, 4) are implemented by a single-chip microcomputer (9, 14, 15, 16) and the non-replaceable memory (10b, 17b) is contained in single-chip microcomputers or via its memory expansion interface - is connected. 8. Device according to claim I _1, characterized in that the read / write memory (17a) is used to receive the logic (program), which is transmitted from modules of level 2 to modules of level 1, with in Einchipmikrorechner the modules of the level 1 (15) is realized. 9. Device according to claim 7, characterized in that the EingangsVAusgangs interface (18) of the modules of the level 1 is partially or completely realized by the single-chip microcomputer contained on them.