DD132215B1 - MICROPROCESSOR-CONTROLLED PERIPHERAL CONNECTION WITH DIRECT MEMORY ACCESS - Google Patents

Description

Title of the invention

Microprocessor-controlled peripheral connection with direct memory access

Field of application of the invention

The invention relates to a microprocessor-controlled peripheral access with direct memory access for connecting peripheral devices with high data transmission rate, preferably diskette memories, to such microprocessor-controlled systems in which the microprocessor is not able due to its operating speed, the data exchange between the peripheral device and memory of the system control, so that the data traffic must be done by a direct memory access operating independently of the microprocessor.

Chara kterist ik the known technical solutions

Such direct memory accesses (also known as DSK = Direct Memory Channel or J) LIA = Direct i.Imory Access) are known (radio television electronics, Issue 6/77 pages 197-198). There is also a known Llikrorechner DSK, whose structure in 7ig, 9 is shown. The DSK control is based on that the Llikroprozessor (also referred to as ZVS = central processing unit) at the time of direct memory access by the peripheral device via a Steueroin ang (RjJADY) in the V / artezustand

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is offset. The memory is addressed by the microprocessor via address interception registers, the outputs of which are interconnected via address multiplexers to the outputs of an address counter provided for memory addressing in DSK operation. The data flow

* to work memory via data multiplexer either

from the microprocessor via the ZVE bus drivers or from the peripheral device via the external device control.

In addition, data amplifiers are required to load-rate the data outputs of the memory to the input RIP to the CPU data bus and to the data inputs of the external device controller.

The disadvantage is therefore that a high additional address counter, multiplexer and amplifier effort is required to realize the direct memory access in microprocessor-controlled systems.

Object of the invention

The aim of the invention is therefore to reduce the additional effort for the direct memory access to a minimum, thereby significantly improving the economy of the overall system.

Explanation of the essence of the invention Technical problem

The invention has for its object to eliminate the disadvantages of the known technical solutions, which consist in that the memory addresses in microprocessor and DSK operation at different locations (in the address latch registers or the address counter) are generated and selected via address multiplexer must be that the data from the microprocessor or the peripheral device via the memory inputs upstream additional data multiplexer must be interconnected and further that the memory outputs via additional data amplifiers to the enlarged

Load must be adapted by the data inputs of the peripheral device during DSK operation,

Features of the invention 5

According to the invention the object is achieved in that the address latch used by the microprocessor for memory addressing fully or partially equipped with the additional function of an address counter v / ird. It depends on the maximum length to be transmitted in DSK operation Blocklungen, whether the entire address latch must receive a counting function or whether only the least significant part of the address latch must be formed as a counter. For diskette memory controllers, an 8-3 bit counter is generally sufficient if only blocks up to max. 256 bytes must be transferred. The default setting of the address latch register to the starting address of the memory area to be addressed occurs during the DSC operation by a memory addressing operation of the microprocessor as it runs including Speicherie- sen. The setting clock for the 2 (higher-order) address byte is used to set a flip-flop at the same time, which sets the microprocessor into the V / art state via a control input. This flip-flop can only be set if another, pre-settable by the microprocessor preparatory flip-flop was set. The byte transfer operation in the DSK mode is performed under shakehand (RUF / ElTD) control independent of the microprocessor, the address counter, as well as a byte counter additionally present in each DSK controller, being strobed on every byte transmitted. The byte counter terminates at ITull passage the DSK operation by resetting the control flip-flops.

The data read from memory in DSK operation passes to the :: ZVE bus driver via the input multiplexer and via the ZVE data bus. From ZVE-Dustreiber the data can be sent to the external device clock, this data line over the ZY ^ -data bus 1st no ;; l: .cii, because the ZVE-Datenausf

-O-

in the V / art ρ state, the ZYE is in a high state and thus does not affect the ZvE-Da ^ епЪая The data passed in: D3K ~ 3e ·; γ1 eb from pe?

via an additional input of the already existing input multiplexer to the ZVE data bus and via the ZVE bus driver to the data inputs of the memory. The use of the ZVE data bus is also possible again due to the high-impedance state of the ZVE data outputs.

embodiment

The solution according to the invention will be explained in more detail below with reference to an exemplary embodiment which represents the connection of a floppy disk memory ("floppy disk") to a microprocessor-controlled system

 The accompanying drawings show:

the microprocessor with data bus Pig. 2: the block diagram of the control logic of the microprocessor the address latch of the microprocessor the memory block diagram the control of the direct memory access the block diagram of the external device control at the DSK (floppy disk control unit) clock diagram of the microprocessor diagram "reading a data field" block diagram of the overall system block diagram of the prior art, from which delimits the invention

In Pig. The overall system comprising the solution according to the invention is shown in block diagram form, showing a direct memory channel (DSK) microcomputer with microprocessor 1 (e.g., 8008, U 808D) peripheral equipment, preferably diskette-type controllers. The ingredients of Pig. 8 are shown in detail in FIGS. 1-6. Fig. 8 contains only the most essential connections between the puncture groups, in particular the address and data links, which are most important for the representation of the inventive solution

 Microprocessor 1 (FIGS. 1, 8, hereinafter referred to as ZVE)

Pig. 1: Pig. 2: Pig. 3: Pig. 4: Pig. 5: Pig. 6: Pig. 7a: Pig. 7b: Pig. 8th: Pig. 9:

requires) two clocks C1 and C2, which are generated together with the clocks DTP and IiTP required for the floppy disk controller 17 (Pig. 6; 8) at a frequency of 500 IdIz by the crystal controlled clock generator 2, apply the input signal READY = 0 to the ZVE1 generates an internal state of the state used to realize the direct memory access.

The control input IUT of the ZVS1 is only needed to remove from the stop state assumed after switching on; It has no significance for the circuit according to the invention. The outputs SYLT, ZUSO - ZUS2 indicate the internal state of the ZVE1 and are required in the control logic 8 (Pig. 2; 8), which requires the cooperation of the ZVE1, in particular with the address latch 9; (Pig. 3; 8) and the memory 11; 12 with Chipselectdecoder 13 (Pig 4, 8) controls. Since the control logic 8 is a standard circuit, which is inevitably predetermined by the structure of the ZVE1, an exact representation in this connection has been dispensed with. The signals generated by the control logic 8 (T1, T2, HUT, SLB, TTosS, USB) are shown in the timing diagram (Fig. 7a). "The inputs and outputs D0-D7 represent the byte-organized bidirectional CPU data bus, over which data , Addresses and control information are input and output. The state of the input in the ZVE 1 is characterized by the signal 2ΊΊΤ = 0, whereby the open-collector gate 4 is opened and the potential resistors 5 are switched on / ground. Through the Open Ccllector gates 3; 7 of the input multiplexer is controlled which data is switched on the Y / IRED-OPi-linked data input bus ElEC-EI37.

In the case of the control voltage SLB = 1, the memory outputs applied to the gates 3 are switched on, the control outputs K 3CH * ILtRB = 1 the outputs of the diskette memory control unit 17 applied to the gates 7. V / other inputs of the input multiplexer are without for the circuit according to the invention Meaning and therefore not shown.

With the signal "IT = 1, the SYE 1 can output data via the ZYE data bus DO-D7, for reasons of the capacity ate decoupling (ictj DatenauGgafcebue. D ₁ ISO -." OAB 7 via the ZVE-Bu.s-

driver 6 is necessary (Fig. 1, 8). Important for the circuit according to the invention is that bein signal ON = O pending for input to the data center 1 data also on the data output bus DAB0-DAB7 abut.

The 14 used by the CPU 1 to address the program memory 11 (Pig, 4) (in the illustrated example consisting of ROMs or pROLIs 256 χ 8 bits) or the data memory (RAM) 12 (PIG 4) (RAIJs 256 χ 1 bit) Bit wide addresses are output in 2 steps with the clocks H, T2 (Pig. 2) via the CPU data bus D0-D7 and must be in the address strobe register 9; 10 cached. The address register 9; 10 is partially formed according to the invention as a counter. In the example shown, a maximum of 131 byte long blocks are to be stored on a diskette memory; to be able to address 131 bytes, an at least 8-digit address counter 9 is required. The 14 address lines (Figure 3) are labeled AUB0-AUB7 (low-order address part) and SAD3-SAD13 (high-order address part). The low-order part 9 of the address latch 9; 10 is used for receiving the Akkumulatorinhaltes OUTPUT commands, so that the address lines AUB0-AUB7 in this Palle have the meaning of an output bus for the accumulator content. The address of the output gate addressed by one of the OUTPUT instructions is indicated by address lines SAD9-SAD13 (Pig * 3).

The delivery gates are timed with the acquisition cycle UEB. In Pig. 5, the direct memory access control by the disk memory is shown. Before the beginning of a transmission, the byte counter 14 designed as a down counter is preset to the position "number of bytes to be transmitted - 1" with the OUTPUT command 0UT10 decoded by gate 15. Perner is set by the OUTPUT command OUT10, the flip-flop 16, which outputs the signal ICBER (direct memory mode standby).

After transmission of the intended number of bytes, the plip-plop 16 is reset by the overflow of the byte counter 14. When presetting the byte counter 14, there are the following possibilities:

Standard memory stored on floppy disk memories is stored on a track of 26 sectors. Each sector contains one ID-Peil and one data field. In addition, an index mark is recorded in front of the first sector. The ID field contains 7 bytes: ID-Llarke, lane address, 0, sector address, 0, 2 CRC-bytes.

The data field contains 131 bytes: data address tag, 128 data bytes, 2 CRC bytes

Between ID-PID and associated data field there is a gap, consisting of 17 Hullbytes, between data field and the following ID-FeId one of 33 Iiullbytes.

The recording of a data field must be preceded by the data address label б Iiullbytes and after the second CRC byte, at least 1 hIlbyte must be recorded. The recording of the б ITullbytes in front of the data field is carried out in the same way as the recording of the envelopes during initialization of the disk by a hull recording plip-plop that can be switched on by the ZVS 1 and recorded in the diskette memory control unit 17 (Pig. 6) is included and that as well as the other elements of the diskette memory controller 17 for the representation of the inventive Schaltungsanordnujag is not essential and therefore only in the block diagram was shown

 The following solution was provided in order to preselect the byte counter 14 with the OUTPUT command OUT'10 with as few lines of the output bus AUBO-AUB7 as possible for the accumulator contents: The bits 0, 3, 4> 5, б are set to 0, bit 1 v / ird L is set, and only the bits 2 and 7 are freely adjustable via the address lines AUB2 and AUB7 by the microprocessor 1 (ZVD 1).

This results in the following scheme for the read and write operations (including initialization) necessary for the disk 11 ensp eer:

Byte counter setting Віѣ 4 5 6 7 Number of bytes surgery 0 12 3 0 0 0 0 Write index mark (+2 zeros) OLOO 0 0 0 0 3 · Write ID-PeId OLLO 0 0 0 L 7 Write data field (+ 4 zeros) OLLO 0 0 0 0 135 Read index mark (+ 2 envelopes) OLOO 0 0 0 0 3 Read ID-PeId OLLO 0 0 0 L 7 Reading data field OLOO 131

The address lines AUBO, AUB1, AUB3 - AUB6 in connection with the OUTPUT command 0UT10 are freely available; some of this is needed to set plip-plops (which are not shown in detail here) contained in the disk storage controller 17 (FIG. 6) to determine the type of operation to be performed. For example, to read a data field, after detecting the associated ID field, a flip-flop (included in disk memory controller 17) is set which enables a gate to which the signal MKF 3 ("data address flag detected") is applied so that the next succeeding data address tag can release a pregip plip plop FRKAHM for the transfer operation from the floppy disk to the main memory (diagram Fig. 7b). Other control flip-flops are associated with reading the index mark, reading an ID field, writing the index mark, and writing an ID or data field.

The signal KSCH indicating the transfer direction is generated in the floppy disk storage control unit 17 by the above-mentioned control flip-flops, namely, the signal KSCH

the following meaning:

KSCH = 0 when transferring storage to floppy disk, KSCH = 1 when transferring floppy disk to storage. The transfer between floppy disk and memory is, as already described, prepared by the OUTPUT command OUT1O, which sets, inter alia, flip-flop 16. The signal KBER = 1 generated by flip-flop 16 enables the gate 18, and the subsequent instruction "read memory" can be read in the cycle "data read" (PCR cycle, characterized by the voltages JJJb ¹ F 2 b = 1, DFF27 = 1) with the clock T2 turn on the designed as ITAlTD latch flip-flop 19, which generates the signal DSZ = 1 turn on. In addition, the command "read memory" has the task in the data read cycle to set the starting address for the direct memory operation in the address latch 9, 10 and to put the data bus D0-D7 of the ZYE 1 in the waiting state of the data read cycle in the high-resistance state. By the signal DSZ = 1, the input signal READY = 0 via the open-collector gate 20, and thereby enters the ZYE 1 in the waiting state.

The actual transfer to or from the memory is initiated by the floppy disk controller 17 (Figure 6) by sending a ringing signal КАІБІ for each byte requested or offered. I. By means of the D flip-flop 21, which generates the feedback signal KARB, a so-called shake-hand operation is carried out, wherein flip-flop 21 with the signal DSZ = 1 enabled edge of the generated by the ZVE 1 Synchronization clock SYi ¹ I switches to the position indicated by the call signal IiAITIJ present at the D input.

If the return signal KARB = 1, the transfer of a byte ζigle memory 12 or to the disk storage control unit 17 is processed. When transferred to the memory 12, a memory write pulse SSB is generated by the gates 22. At the same time, the control voltage KSCH · KARB = 1 at the gates 7 feeds the Y / decision data ", 7L) FO-7 / DP7 from the floppy disk into the data input bus ТГХЪи-ЕХВ'Т and via the ZVE data buoys and the ZYB-type drivers at data inputs DABG-DAB7 the memory 12. The gates 3 are thereby by the SoGuerüpccuiiing 3LL '= 0, generated by the control

Voltage DSZ · KSCH in switching mode 23, locked. When transferring memory 12 to the diskette memory control unit 17, the memory data present on the data output bus DAB0-DAB7 via the input multiplexer 3-5 and the CPU bus drivers 6 are taken over by the takeover clock KUEB generated by the gate 24. All data transfer operations are handled during the acknowledgment signal KAEB = 1. The trailing edge of the negative feedback signal "ШШ" can therefore be used to advance both the address counter 9 and the byte counter 14 after each byte transmission. · After transmission of the last byte, the byte counter 14 outputs a "carry backward" pulse which is routed to the clock input of the flip-flop 16 and turns off the signal KBER The signal ICBER = 0, the signal DSZ = 0 and the input signal READY = 1, so that the CPU 1 can leave the waiting state again.

Claims (1)

claim Microprocessor-based direct memory access peripheral port for connecting high speed peripheral devices, preferably floppy disk memories, to a microprocessor (ZVE) settable address latch, an input multiplexer for the bi-directional CPU data bus, ZVE bus drivers connected thereto, and a direct memory access byte counter; characterized in that the address latch (9; 10) is formed completely or partially according to the block to be transmitted in the direct memory access block length as a bytewise weiterschaltbarer address counter whose outputs are connected to the address inputs of the data memory and the associated Chipselectdecoders (12; in that a flip-flop (16), which can be preselected by the microprocessor (1) simultaneously with the byte counter (14), whose clock input is connected to the "carry backward" output of the byte counter (14) anden, is connected to the set input and directly to the reset input of another flip-flop (19) via an ITAND gate (IS), which also applies the read cycle characterizing cycle control signals DFF26 and DFF27 and the higher clock latch set register clock T2 is, whose output via an open-collector gate (20) at the input READY of the microprocessor (1) is applied and that the data inputs of the external device firing (17) and the memory (12) directly to the outputs (DAB0-DA37) of the ZYE bus driver (6) and the data outputs (V / DF0-V / DF7) of the external device controller (17) are connected via an additional input (7) of the input multiplexer (3-5) to the CPU data bus, wherein the data outputs (D0-D7) of the microprocessor (1) are in the high-resistance state during the direct memory access. For this J? Pages Drawings