CR20160441A - Miembro de circuito y estructura de montaje que tiene espacio hueco, y procedimiento para la fabricación de la estructura de montaje - Google Patents
Miembro de circuito y estructura de montaje que tiene espacio hueco, y procedimiento para la fabricación de la estructura de montajeInfo
- Publication number
- CR20160441A CR20160441A CR20160441A CR20160441A CR20160441A CR 20160441 A CR20160441 A CR 20160441A CR 20160441 A CR20160441 A CR 20160441A CR 20160441 A CR20160441 A CR 20160441A CR 20160441 A CR20160441 A CR 20160441A
- Authority
- CR
- Costa Rica
- Prior art keywords
- assembly structure
- procedure
- manufacture
- circuit
- hollow space
- Prior art date
Links
- 239000011796 hollow space material Substances 0.000 title 1
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
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- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Un miembro de circuito que incluye: un elemento que tiene una región funcional; una cubierta de tabla dispuesta opuesta a la región funcional; y una nervadura formada para rodear la región funcional, para proporcionar un espacio entre la región funcional y la cubierta. L a cubierta incluye una lámina S que tiene un espesor de 100 micras o menos. La lámina S tiene un módulo de tracción elástica Es a 175° C de la lámina S es preferiblemente 20GPa o más.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2014073326 | 2014-03-31 | ||
PCT/JP2015/001860 WO2015151514A1 (ja) | 2014-03-31 | 2015-03-31 | 中空部を有する回路部材および実装構造体、ならびに実装構造体の製造方法 |
Publications (1)
Publication Number | Publication Date |
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CR20160441A true CR20160441A (es) | 2016-12-01 |
Family
ID=54239859
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CR20160441A CR20160441A (es) | 2014-03-31 | 2015-03-31 | Miembro de circuito y estructura de montaje que tiene espacio hueco, y procedimiento para la fabricación de la estructura de montaje |
Country Status (8)
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US (1) | US20170117874A1 (es) |
EP (1) | EP3128545A4 (es) |
JP (1) | JPWO2015151514A1 (es) |
KR (1) | KR20160140744A (es) |
CN (1) | CN106170854A (es) |
CR (1) | CR20160441A (es) |
TW (1) | TW201601260A (es) |
WO (1) | WO2015151514A1 (es) |
Families Citing this family (11)
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CN104576964A (zh) * | 2014-12-17 | 2015-04-29 | 深圳市华星光电技术有限公司 | 透明柔性封装衬底及柔性oled封装方法 |
KR101931508B1 (ko) * | 2015-03-27 | 2018-12-21 | 가부시키가이샤 무라타 세이사쿠쇼 | 탄성파 장치, 통신 모듈 기기 및 탄성파 장치의 제조 방법 |
KR102513134B1 (ko) | 2017-09-29 | 2023-03-24 | 나가세케무텍쿠스가부시키가이샤 | 실장 구조체의 제조 방법 및 이것에 이용되는 시트 |
JP7224296B2 (ja) * | 2017-10-31 | 2023-02-17 | ナガセケムテックス株式会社 | 実装構造体の製造方法およびこれに用いられるシート |
CN110229488A (zh) * | 2018-03-05 | 2019-09-13 | 科思创德国股份有限公司 | 热塑性复合材料制件及其制备方法和用途 |
US10497566B1 (en) * | 2018-06-19 | 2019-12-03 | Macronix International Co., Ltd. | Layout design for fanout patterns in self-aligned double patterning process |
US11777465B2 (en) | 2018-08-30 | 2023-10-03 | Skyworks Solutions, Inc. | Packaged surface acoustic wave devices |
EP3863388A4 (en) * | 2018-10-05 | 2022-06-15 | Kabushiki Kaisha Toshiba | SEMICONDUCTOR HOUSING |
US11938688B2 (en) * | 2018-12-18 | 2024-03-26 | Resonac Corporation | Laminate, printed wiring board, semiconductor package, and method for manufacturing laminate |
JP7243186B2 (ja) * | 2018-12-27 | 2023-03-22 | 住友ベークライト株式会社 | 封止用樹脂組成物、中空パッケージおよびその製造方法 |
WO2022065496A1 (ja) * | 2020-09-28 | 2022-03-31 | 昭和電工マテリアルズ株式会社 | 回路接続用接着剤フィルム、無機フィラー含有組成物、並びに、回路接続構造体及びその製造方法 |
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US6861757B2 (en) * | 2001-09-03 | 2005-03-01 | Nec Corporation | Interconnecting substrate for carrying semiconductor device, method of producing thereof and package of semiconductor device |
JP2005210045A (ja) * | 2003-12-24 | 2005-08-04 | Kyocera Corp | 光半導体装置 |
JP4131330B2 (ja) * | 2004-07-27 | 2008-08-13 | 松下電工株式会社 | 光半導体装置 |
JP2006237405A (ja) * | 2005-02-25 | 2006-09-07 | Toshiba Corp | 電子部品装置 |
JP4986545B2 (ja) * | 2006-08-31 | 2012-07-25 | 京セラクリスタルデバイス株式会社 | 水晶振動子 |
WO2009057699A1 (ja) * | 2007-10-30 | 2009-05-07 | Kyocera Corporation | 弾性波装置 |
JP2009226571A (ja) * | 2008-02-28 | 2009-10-08 | Nippon Kayaku Co Ltd | マイクロデバイス及びその製造方法 |
JP2010199474A (ja) * | 2009-02-27 | 2010-09-09 | Kyocera Chemical Corp | 電子部品用中空パッケージ、電子部品用中空パッケージの接着シート、および蓋体、ならびに電子部品の製造方法 |
JP5444833B2 (ja) * | 2009-05-18 | 2014-03-19 | 日立化成株式会社 | 感光性樹脂組成物、リブパターンの形成方法及び電子部品 |
JP5425005B2 (ja) * | 2009-08-19 | 2014-02-26 | 日本電波工業株式会社 | 圧電部品及びその製造方法 |
WO2011145750A1 (ja) | 2010-05-20 | 2011-11-24 | 日立化成工業株式会社 | 感光性樹脂組成物、感光性フィルム、リブパターンの形成方法、中空構造とその形成方法及び電子部品 |
JP2012084954A (ja) * | 2010-10-07 | 2012-04-26 | Panasonic Corp | 弾性波素子とこれを用いた電子機器 |
WO2012144370A1 (ja) * | 2011-04-19 | 2012-10-26 | 京セラ株式会社 | 電子部品および弾性波装置 |
JP5660985B2 (ja) * | 2011-07-13 | 2015-01-28 | 日東電工株式会社 | 貼着型制振材 |
JPWO2013042751A1 (ja) * | 2011-09-22 | 2015-03-26 | 日立化成株式会社 | 積層体、積層板、多層積層板、プリント配線板及び積層板の製造方法 |
WO2013128823A1 (ja) * | 2012-02-28 | 2013-09-06 | パナソニック株式会社 | 弾性波装置およびその製造方法 |
JP2013178526A (ja) | 2013-04-01 | 2013-09-09 | Hitachi Chemical Co Ltd | 中空構造体及びその製造方法 |
US10224260B2 (en) * | 2013-11-26 | 2019-03-05 | Infineon Technologies Ag | Semiconductor package with air gap |
-
2015
- 2015-03-31 CN CN201580017971.XA patent/CN106170854A/zh active Pending
- 2015-03-31 WO PCT/JP2015/001860 patent/WO2015151514A1/ja active Application Filing
- 2015-03-31 JP JP2016511390A patent/JPWO2015151514A1/ja active Pending
- 2015-03-31 EP EP15773495.5A patent/EP3128545A4/en not_active Withdrawn
- 2015-03-31 US US15/300,587 patent/US20170117874A1/en not_active Abandoned
- 2015-03-31 TW TW104110627A patent/TW201601260A/zh unknown
- 2015-03-31 KR KR1020167028912A patent/KR20160140744A/ko unknown
- 2015-03-31 CR CR20160441A patent/CR20160441A/es unknown
Also Published As
Publication number | Publication date |
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JPWO2015151514A1 (ja) | 2017-04-13 |
WO2015151514A1 (ja) | 2015-10-08 |
CN106170854A (zh) | 2016-11-30 |
EP3128545A1 (en) | 2017-02-08 |
KR20160140744A (ko) | 2016-12-07 |
EP3128545A4 (en) | 2018-02-28 |
US20170117874A1 (en) | 2017-04-27 |
TW201601260A (zh) | 2016-01-01 |
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