CN85105842A - Multilayer printed circuit board - Google Patents
Multilayer printed circuit board Download PDFInfo
- Publication number
- CN85105842A CN85105842A CN 85105842 CN85105842A CN85105842A CN 85105842 A CN85105842 A CN 85105842A CN 85105842 CN85105842 CN 85105842 CN 85105842 A CN85105842 A CN 85105842A CN 85105842 A CN85105842 A CN 85105842A
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- China
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- space
- bus plane
- hole
- printed circuit
- multilayer board
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Abstract
In the multilayer printed circuit that comprises signals layer, bus plane and some through holes, for making the insulation of through hole and bus plane, the shape in formed each space is made into basically and has the square of four fillets on the bus plane.Thereby strengthened the bus plane area that is left between the adjacent space, in order to suppress the increase of this zone resistance.
Description
The present invention relates to a kind of multilayer board.Specially refer to a kind of improved form in formed space on the via regions of the bus plane of multilayer board.
The bus plane of multilayer board has a space (not contacting conductor part) in its throughhole portions, in the hope of avoid short circuit between bus plane conductor and via conductors.General multilayer board has circular void or is the square space at four right angles.For example, in notification number is 121168/74 not authorization Japan Patent, circular void is disclosed just.
Along with large scale integrated circuit in the increase aspect speed and the density, multilayer board also corresponding increasing on density and area of large scale integrated circuit make to be installed.When some electronic components that comprise large scale integrated circuit are installed in higher density when having on very high component density and the large-area multilayer board, the electric current that is added on those electronic components will be very big.Therefore, must make the impedance of bus plane enough little to suppress the pressure drop at bus plane two ends.For this reason, the void area that reduces to be formed at bus plane is highly effective.
Meanwhile, have on very high component density and the large-area multilayer board, must adopt strict more dimensional discrepancy condition, such as the formation position deviation in lamination deviation and hole etc.Must be to the definite of bus plane void size based among the overall consideration to above-mentioned situation.Too little as void size, then because the dimensional discrepancy that causes in manufacture process can increase the short trouble between through hole and the bus plane conductor, thereby cause the productivity ratio of multilayer board to descend.
One of purpose of the present invention provides a kind of multilayer board, and the sort circuit plate can reduce owing to forming the bus plane impedance that the space increases, and can not cause the short trouble between via conductors and the bus plane conductor simultaneously.
Another object of the present invention provides a kind of multilayer board that is applicable to the circuit element high-density installation.
According to the present invention, in multilayer printed circuit, comprise the some conductive layers that are overrided to form by means of some insulating barriers; Also comprise some through holes of selectively each conductive layer being coupled together of being used for; Also have some spaces in addition, insulating effect is played in the corresponding position that is used for forming on as the conductive layer of bus plane through hole, and its each space is all made basically and had the square of four fillets.
Even the mode with bidimensional is arranged a lot of spaces on bus plane, owing to, still can make and leave very wide conductive layer between the adjacent space according to above-mentioned special void shape of the present invention.Therefore, the conductor resistance between adjacent space is just littler than the prior art.
Other purpose of the present invention and advantage will be more obvious in the narration in conjunction with the accompanying drawings below.
Fig. 1 is the sectional structure schematic illustration of multilayer board;
Fig. 2 is the oblique view that explanation is formed at some spaces of bus plane;
Fig. 3 is the key diagram according to space of the present invention flat shape;
Fig. 4 is when total position error is in the permitted maximum range, the actual range key diagram at through hole edge;
Fig. 5 shows according to the comparison of space of the present invention with general circular void; And
Fig. 6 then shows the comparison according to space of the present invention and general square space.
Fig. 1 is the cutaway view that illustrative is used multilayer board of the present invention.According to multilayer board of the present invention, with regard to its sectional structure, similar with the multilayer board known to general.Therefore for simplicity, Fig. 1 illustration the structure of a simplification.It comprises the insulated substrate 10 that has as the conductive layer 3 of bus plane; Have conductive layer 3 as printing signal line or another bus plane ' another insulated substrate 10 '; And a thermosetting adhesive layer 12, be used for its two sides of insulated substrate 10 and 10 ' be laminated on.
In Fig. 1, through hole 1A, 1B and 1C get through hole with drill bit or similar tool and form on stacked printed circuit board (PCB), and form conducting film with the method for electroless plating and/or electro deposition in these holes.These conducting films are connected on the bus plane or signal link of this printed circuit board (PCB) the inside selectively.The then corresponding wiring layer that is positioned at circuit board surface that is connected on of the other end of conducting film.Shown in Figure 2 as what bus plane 3 parts were amplified, except that through hole 1C will be with bus plane be connected, space 2(2A～2E) is partly to remove the bus plane around through hole 1A～1E formed.
According to multilayer board of the present invention, it is characterized in that the shape in bus plane 3 or 3 ' last formed space 2.Each space is square substantially.And its four angles are the circular arc that radius is R.
Fig. 3 is the zoomed-in view in space 2.Point Q is the lattice point of an imagination, represents the normal place of through hole 1 central point.Label 21 has been represented the maximum allowable offset scope of the edge offset imagination lattice point of actual through hole.M
XAnd M
YRepresent the size of space 2 on directions X and Y direction respectively.R is each angle radius of curvature at these four angles, space.On behalf of the minimum between through hole and the bus plane, L then to guarantee the gap.
Each basic unit 10 and 10 of multilayer board ' manufacture process in, we must allow each space on the bus plane to imagine lattice point Q relatively to a certain degree position deviation.When opening the hole in addition in the basic unit that is laminated, we also must allow between through hole and the imagination lattice point certain position deviation is arranged.By caused position deviation or dimensional discrepancy in each step of above-mentioned manufacture process, be referred to as " total position error " hereinafter.
With respect to the imagination lattice point, represent with the part that dotted line enclosed 22 of Fig. 4 that as total position error allowed band of through hole 1 central point then the maximum allowable offset scope 21 of this through hole marginal position is of a size of N at directions X and Y direction respectively
XAnd N
Y, they can be expressed as:
N
X=(in maximum total placement error value of directions X)+bit diameter,
N
Y=(in maximum total placement error value of Y direction)+bit diameter.
Therefore, space 2 sizes of Fig. 3 can be expressed as:
M
X＝N
X+2L
M
Y＝N
Y+2L
R＝r+L
R=bit diameter/2 in the formula.
Fig. 5 and Fig. 6 illustrated according to the present invention space 2 respectively with general circular void 2 ' and with general square space 2 " comparable situation.
Total placement error value and the through hole of supposing them are identical with minimum clearance between the bus plane, and as obviously seeing among Fig. 5, then the size in space 2 is made in its four circular arc portions and the general circular void 2 ' mutually and connect.So comparing with the space of prior art in this space of the present invention, can reduce whole shaded area dimensionally.As shown in Figure 6, the size in this space 2 of the present invention is made with general square space 2 and " is connect mutually.Therefore it is long-pending that this space of the present invention can be saved four edged surfaces being with shade dimensionally again.
Like this, just can reduce the occupied area in each space.As shown in Figure 2, when on bus plane 3, will forming many space 2A for through hole is used with two-dimensional way, 2B, 2D during 2E etc., compares with prior art, just might leave wideer conductive layer between each adjacent space of multi-layer wiring board according to the present invention.Therefore, just might suppress the increase of resistance in these positions.Because in this case, its total position error permissible value is identical with the permissible value of prior art, so the variation of creating conditions can not reduce its productivity ratio.
In above-mentioned embodiment, the approximate square in this space.But different when total position error of total position error of its directions X and Y direction, or when arranging some through hole, this space can be the rectangle that is circular arc at its four angles.
Claims (3)
1, multilayer printed circuit comprises the some conductive layers that are overrided to form by some insulating barriers; Comprise that also some are used for the some through holes that selectively each conductive layer coupled together; Also have some spaces in addition, insulating effect is played in the corresponding position that is used for forming on as the conductive layer of bus plane through hole, it is characterized in that described each space is basically to have the square of four fillets.
2,, it is characterized in that described each space is the square that has four fillets basically according to the multilayer board of claim 1.
3,, it is characterized in that each of four fillets in described space all has the radius of curvature bigger than the radius of described through hole according to the multilayer board of claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 85105842 CN85105842A (en) | 1985-07-23 | 1985-07-23 | Multilayer printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 85105842 CN85105842A (en) | 1985-07-23 | 1985-07-23 | Multilayer printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN85105842A true CN85105842A (en) | 1987-01-28 |
Family
ID=4794743
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 85105842 Pending CN85105842A (en) | 1985-07-23 | 1985-07-23 | Multilayer printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN85105842A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100381027C (en) * | 1999-09-02 | 2008-04-09 | 伊比登株式会社 | Printed wiring board and method of producing same |
| CN102958290A (en) * | 2012-11-15 | 2013-03-06 | 广东生益科技股份有限公司 | PCB (printed circuit board) manufacturing method capable of improving PCB large copper surface upwarp |
| CN107069357A (en) * | 2011-05-31 | 2017-08-18 | 服务器技术股份有限公司 | Method and apparatus for multiple input electric energy to be assigned into adjacent output |
| CN107466167A (en) * | 2017-08-10 | 2017-12-12 | 上海幂方电子科技有限公司 | A kind of method that inkjet printing prepares flexible printed multilayer circuit board |
-
1985
- 1985-07-23 CN CN 85105842 patent/CN85105842A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100381027C (en) * | 1999-09-02 | 2008-04-09 | 伊比登株式会社 | Printed wiring board and method of producing same |
| CN107069357A (en) * | 2011-05-31 | 2017-08-18 | 服务器技术股份有限公司 | Method and apparatus for multiple input electric energy to be assigned into adjacent output |
| CN107069357B (en) * | 2011-05-31 | 2020-11-06 | 服务器技术股份有限公司 | Method and apparatus for distributing multiple input electrical energy to adjacent outputs |
| CN102958290A (en) * | 2012-11-15 | 2013-03-06 | 广东生益科技股份有限公司 | PCB (printed circuit board) manufacturing method capable of improving PCB large copper surface upwarp |
| CN102958290B (en) * | 2012-11-15 | 2015-10-28 | 广东生益科技股份有限公司 | Improve the pcb board manufacture method that the large copper face of pcb board warps |
| CN107466167A (en) * | 2017-08-10 | 2017-12-12 | 上海幂方电子科技有限公司 | A kind of method that inkjet printing prepares flexible printed multilayer circuit board |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
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| WD01 | Invention patent application deemed withdrawn after publication |