CN2519335Y - Controlling logic circuit of gate keeper dog - Google Patents
Controlling logic circuit of gate keeper dog Download PDFInfo
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- CN2519335Y CN2519335Y CN 01279116 CN01279116U CN2519335Y CN 2519335 Y CN2519335 Y CN 2519335Y CN 01279116 CN01279116 CN 01279116 CN 01279116 U CN01279116 U CN 01279116U CN 2519335 Y CN2519335 Y CN 2519335Y
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Abstract
The utility model discloses a watchdog control logic circuit being arranged between a CPU system and a watchdog circuit, the control logic circuit board at least comprises a timer, a first logic circuit and a second circuit, which adopts the way to introduce the signal of cleaning dog into the logic through which the production of cleaning dog signals can be controlled or the CPU cleaning dog signal can be used so as to realize the control towards the watchdog circuit, at the same time through adding a plurality of control bits into logic to cooperate with the system restoration signals produced by the watchdog circuit can realize the flexible and restored control of the CPU peripheral circuit, and the utility model solves the problem that the CPU can not clean dogs during the period for a veneer from being powered up to completing loading and starting process, which can also provide the veneer the choice between the debug mode and the working state while exerts no influence on the stability of the watch-dog circuit.
Description
Technical field
The utility model relates to monitoring technique, specifically, relates to the circuit of house dog steering logic in a kind of cpu system.
Background technology
Watchdog circuit is the interference protection measure that generally adopts in the embedded control system, make system or circuit under situation about being interfered, can reset automatically, restart and normally operation, thereby normal operation recover in the assurance system from soft, hard error.
Watchdog circuit is made of a counter that carries impulse source that is independent of outside the CPU usually.Utilize the reset signal of the spill over of counter as CPU, when the CPU operate as normal, CPU just exports a pulse at set intervals with counter O reset, and this pulse signal is called dog signal clearly.If the zero clearing cycle of the time ratio CPU that counter regularly overflows is long, counter just can not overflow all the time, but system's operate as normal; After CPU is absorbed in endless loop, cause and can not normally carry out zero clearing the counter in the watchdog circuit, after a period of time, counter output spill over, spill over makes system reset as the reset trigger signal of CPU, thereby withdraws from endless loop.Watchdog circuit is except that the CPU that resets, and except that CPU other of also can resetting possesses the device of reset function.
Existing watchdog circuit can be divided into two kinds.A kind of is the hardware watchdog circuit, for example shown in Figure 1, and Fig. 1 is general hardware watchdog circuit diagram.Watchdog circuit adds simple peripheral circuit by the watchdog circuit chip to be realized, the reset signal of cpu system and watchdog circuit is direct-connected by physical cord, the spill over that the watchdog chip internal counter produces, directly or through a not gate give the reset signal that needs control chip, CPU is by the WDI end of an one I/O end (I/O) mouthful output reset signal to watchdog circuit chip MAX706.Another kind is the software watchdog circuit, uses the timing of pure software realization house dog to overflow function.
Existing watchdog circuit all can not be taken into account the problem of reliability and dirigibility.Though the hardware watchdog circuit can guarantee the reliability of watchdog circuit, but lost the flexible control of CPU to watchdog circuit, design is fatal so in some applications, for example, in single-board telecommunication, what bottom used is vxworks operating system, and veneer needs about 5～6 seconds time at the start-up routine loaded that powers on, and interior during this period of time CPU can't send dog signal clearly to watchdog circuit.And the time of overflowing of most of watchdog circuit design all between 0.5～2 second, if adopt simple watchdog circuit, then veneer can ceaselessly reset and can't finish the work, and can't realize debugging the function that CPU under the attitude closes house dog.The design of the house dog of pure software is that in case processor is died, software watchdog can't play a role, so its reliability can not get assurance with the operated to basis of software.
The utility model content
The purpose of this utility model is to provide the control logic circuit of a kind of house dog, solve veneer power on to load start-up routine finish during CPU dog problem clearly, watchdog circuit reliability and dirigibility are taken into account.
The utility model is realized by following concrete scheme:
The control logic circuit of a kind of house dog between CPU and watchdog circuit, is characterized in that:
Described control logic circuit comprises timer, first logical circuit, second logical circuit at least;
The hard reset signal of CPU or warm reset signal are sent into timer as the timing enabling signal of timer, and the elapsed time clock signal that system clock provides is sent into timer; In addition,
The clear dog signal that clear dog signal of clock that is provided by system clock and CPU send connects the input end of first logical circuit as input signal, and overflowing of above-mentioned timer is connected to the first logical circuit control end;
The clear dog signal of the output signal of above-mentioned first logical circuit and above-mentioned clock connects the input end of second logical circuit as output signal, and a debugging attitude/operating conditions selects signal to connect the second logical circuit control end; The output signal of this second logical circuit is connected to the clear dog signal input part of watchdog circuit chip.
Described first logical circuit is the alternative data selector.
Described second logical circuit is the alternative data selector.
The elapsed time clock signal of the clear dog signal of described clock, timer is to be provided by the external crystal-controlled oscillation frequency dividing circuit.
Described control logic circuit further comprises peripheral chip reset control logic circuit, and this circuit is made up of the logic gates and the control register that resets at least; The position signal of the hard reset signal of CPU and the control register that resets is delivered to each logic gates input end respectively, or the position signal of the warm reset signal of CPU and the control register that resets is delivered to each logic gates input end respectively; The output terminal of each logic gates is connected to each external chip reset terminal respectively.
Above-mentioned control logic circuit can be realized by the CPLD-XC95288XL-10ns-PQFP208 chip.
One logic gates further is set, and the output terminal of this logic gates connects the hand-reset end of described watchdog chip, watchdog chip overflow end and the hand-reset push button signalling is connected to the input end of this logic gates.
The utility model is given watchdog circuit with the clear dog signal of CPU by control logic circuit, can realize the flexible control to watchdog circuit, and provides debugging attitude and operating conditions to select, and does not influence the reliability of watchdog circuit; Debugging attitude by the clear dog signal controlling of clock watchdog circuit, the clear dog signal controlling watchdog circuit that sends by CPU at operating conditions, can also add the slow time-delay that starts, when the start-up routine of CPU needs the long period, power on the back clear dog signal of use clock so that the loading of start-up routine at operating conditions, provide dog signal clearly by CPU afterwards, solved Board Power up to load start-up routine finish during CPU dog problem clearly; Cooperate with the systematic reset signal that watchdog circuit produces by in logic, increasing some control bits simultaneously, can realize the control that resets flexibly the CPU peripheral circuit; Use special watchdog chip and simply be connected the reliability that has guaranteed house dog, can satisfy the designing requirement of watchdog circuit.
Description of drawings
Fig. 1 is general hardware watchdog circuit diagram;
Fig. 2 is for using board resetting circuit embodiments synoptic diagram of the present utility model;
Fig. 3 is control logic circuit figure of the present utility model;
Fig. 4 is a peripheral chip reset control logic circuit diagram of the present utility model.
Embodiment
For make the purpose of this utility model, technical scheme, and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the utility model is further described.
The present common device that possesses watchdog function as ADM706, ADM708, MAX706, TC1232 etc., can be finished electrification reset and the reset signal of system is provided.For example, power on or input end when trigger pip is arranged, the monostable reset signal of 200ms can be provided, by this reset signal system is finished completely and reset.Utilize above-mentioned device to come the surveillance state, the assurance system can restart under abnormal conditions.
On general veneer, adopt MAX706 or ADM706 watchdog circuit as CPU.MAX706 or ADM706 are a kind of electrification reset chips with watchdog circuit, the low level that when chip power, can the produce a 200ms (/RESET) signal that resets, timing circuit in the while opening chip, if clear dog signal input part (WDI) signal no change in 1.6 seconds, will house dog overflow end (/WDO) output a timing spill over, use/WDO signal as the hand-reset end (/MR) input signal, thus produce reset output signal/RESET CPU that resets by the MAX706 internal circuit.Be that MPC8260 is applied as example explanation with MAX706 chip, CPU below.
After the system start-up, since support file random access memory (SDRAM) initialization, move internal memory and start-up course needs roughly 8～10 seconds based on plate support software bag (BSP) start-up routine of vxworks operating system from guiding ROM (read-only memory) (BOOT ROM), dog clearly during this period.
For addressing the above problem, referring to shown in Figure 2.Fig. 2 is for using board resetting circuit embodiments synoptic diagram of the present utility model.Be the house dog device of the various models of compatibility, with the MAX706 chip /WDO end, a manual reset key be connected to the input end of a logical AND gate, the output terminal of this logical AND gate be connected to the watchdog circuit chip /the MR input end; Can add the filter capacitor of one 0.1 F at the hand-reset end of MAX706, carry out the anti-shake processing of input signal, in case influence resets normally; Watchdog chip /the port reset end of RESET output termination MPC8260 (/POREST).The output signal of control logic circuit (WDI-CPLD) is connected to the clear dog signal end WDI of MAX706, and the output signal RESET1 of control logic circuit, RESET2...RESETn are to each peripheral chip input reset signal.For avoid BSP between the starting period timer among the MAX706 overflow Reset Board, the clear dog signal (WDI-CPU) of CPU is introduced control logic circuit, and at 10 seconds back off timer of control logic circuit design, during 10 seconds, the clear dog signal of clock that is provided by system clock provides the clear dog signal of MAX706; After the BSP loading is finished, switch to normal Watchdog pattern, by the clear dog of CPU software, in case CPU can not produce clear dog signal in 1.6 seconds, MAX706 driving/WDO signal is effective, feeds back to/MR, cause MAX706 /the RESET signal is effective, resetting when finishing system's operation exception.
Referring to shown in Figure 3.Fig. 3 is control logic circuit figure control logic circuit figure of the present utility model.Wherein first logical circuit in the control logic circuit, second logical circuit are the alternative data selection circuit.The elapsed time clock signal of the hard reset signal of CPU or warm reset signal, timer is delivered to timer; The clear dog signal that the clear dog signal of the clock that system clock provides, CPU send is the first data selection circuit input signal; The clear dog signal of the output of first data selection circuit and described clock is the second data selection circuit input signal; The output signal of second logical circuit is the clear dog signal input part (WDI) that the WDI-CPLD signal is delivered to the watchdog circuit chip; The spill over of timer (Osc-sel), CPU powers on or read from the I/O end (I/O) of CPU the back that resets debugging attitude/operating conditions signal (Work-Debug-sel) are respectively as the control signal that enables of first data selection circuit, second data selection circuit.
Each uses signal, interface module, description of use as shown in the table.
| Use signal | Interface module | Description of use |
| Debugging attitude/operating conditions is selected (Work-Debug-sel) | The veneer wire jumper | Be used for selecting debugging attitude " 0 " and operating conditions " 1 " |
| Hard reset (HRESET-CPU) | MPC8260 CPU | House dog time-delay control count enable signal |
| Elapsed time clock 1.49Hz | The logical timer module | House dog time-delay control counting clock |
| The clear dog 6Hz of clock | The logical timer module | The clear dog signal of logic when debugging attitude and delay |
| WDI-CPU | MPC8260 CPU | The clear dog signal that CPU sends |
| WDI-CPLD | MAX706 | The clear dog signal input of MAX706 |
| Port reset (POREST) | MPC8260 CPU | Cpu signal resets |
The control logic circuit job description.
(1) debugging attitude and operating conditions are selected.Debugging attitude/operating conditions selects signal (Work-Debug-sel) by wire jumper and toggle switch control, and when this signal is the debugging attitude during for low level, control logic circuit is selected the input of the clear dog signal of 6Hz clock as the WDI of MAX706; When this level is an operating conditions during for high level, the control logic circuit clear dog signal that time-delay back CPU sends of selecting to power on.
(2) realize the clear dog process of time-delay that powers on during operating conditions.After initial watchdog circuit powers on or resets, CPU produces the HRESET-8260 signal, timer in this signal enabling control logic circuit begins regularly, this moment this timer to overflow output signal Osc-sel be 0, it is 1 that debugging attitude/operating conditions is selected signal, and data selection circuit selects the clear dog signal of 6Hz clock to export the clear dog signal input part (WDI) of MAX706 to as the WDI-CPLD signal; Produce after timer is timed to 10 seconds that to overflow output signal (Osc-sel) be 1, the clear dog signal WDI-CPU signal of selecting CPU to send exports the WDI of MAX706 to as the WDI-CPLD signal; After this, timer is timed and overflows lockedly, and initial Watchdog lost efficacy, and system enters normal Watchdog pattern.Under the normal mode, if CPU did not send dog signal clearly here to the WDI of MAX706 end in 1.6 seconds, then MAX706 thinks cpu fault, its/WDO produces spill over, and the port reset end of CPU/PORESET exports a low level veneer is resetted.
Elapsed time clock 1.49Hz that timer uses and the clear dog signal of clock of 6Hz obtain by the logic frequency division by external crystal-controlled oscillation, and be irrelevant with veneer cpu system state, and the clock source that can guarantee house dog so is not subjected to the influence of system; The timing of timer was chosen as about 10 seconds, can change according to the concrete single board starting time.
In control logic circuit, can add peripheral chip reset control logic circuit, in order to resetting flexibly to peripheral chip.Referring to shown in Figure 4.Fig. 4 is a peripheral chip reset control logic circuit diagram of the present utility model.One control register that resets is arranged in the circuit, and matching with reset signal that CPU produces resets.In the present embodiment to the control that resets of external chip be with position signal and the CPU hard reset signal of the control register that resets with, like this can be by to the method for control bit zero setting, realize resetting rather than just resetting once when only being confined to cpu reset to external chip.The control register position reset among the figure when " 1 ", then by CPU /the HRESET signal peripheral chip that resets, during for " 0 " by the control register position that the resets peripheral chip that resets.This circuit effectively designs by the low level that resets, if it is effectively high to reset in the system, can will change into or door (or) realization with door (and) among the figure, and this moment, " 1 " " 0 " implication of control bit was just in time opposite with design among the figure.
At this watchdog circuit, the required work of doing of board software is:
A. powering on or debugging single board attitude/operating conditions sign Work-Debug-sel is read from the I/O mouth of CPU in the back that resets;
If B. debugging single board attitude/operating conditions sign is set to debugging mode, then close the clear dog module of software watchdog;
If C. debugging single board attitude/operating conditions sign is set to mode of operation, load BSP, a clear immediately then dog;
D. start regularly clear dog task;
E. start other business.
Above-mentioned timer, alternative data selector, can realize in logical device that with door, the control register that resets this logical device is the CPLD-XC95288XL-10ns-PQFP208 of Xilinx company.
In sum, the house dog control logic circuit that the utility model provides, debugging during attitude by the clear dog signal controlling of clock watchdog circuit; During operating conditions, the back elder generation that powers on to timing, provides dog signal clearly by CPU software by the clear dog of clock afterwards.The watchdog circuit of this plate can not be closed, and such design is safer, does not have situation about can not save oneself.
Claims (7)
1. the control logic circuit of a house dog between CPU and watchdog circuit, is characterized in that:
Described control logic circuit comprises timer, first logical circuit, second logical circuit at least;
The hard reset signal of CPU or warm reset signal are sent into timer as the timing enabling signal of timer, and the elapsed time clock signal that system clock provides is sent into timer; In addition,
The clear dog signal that clear dog signal of clock that is provided by system clock and CPU send connects the input end of first logical circuit as input signal, and overflowing of above-mentioned timer is connected to the first logical circuit control end;
The clear dog signal of the output signal of above-mentioned first logical circuit and above-mentioned clock connects the input end of second logical circuit as output signal, and a debugging attitude/operating conditions selects signal to connect the second logical circuit control end; The output signal of this second logical circuit is connected to the clear dog signal input part of watchdog circuit chip.
2. the control logic circuit of a kind of house dog according to claim 1, it is characterized in that: described first logical circuit is the alternative data selector.
3. the control logic circuit of a kind of house dog according to claim 1, it is characterized in that: described second logical circuit is the alternative data selector.
4. the control logic circuit of a kind of house dog according to claim 1, it is characterized in that: the elapsed time clock signal of the clear dog signal of described clock, timer is to be provided by the external crystal-controlled oscillation frequency dividing circuit.
5. the control logic circuit of a kind of house dog according to claim 1, it is characterized in that: described control logic circuit further comprises peripheral chip reset control logic circuit, this circuit is made up of the logic gates and the control register that resets at least; The position signal of the hard reset signal of CPU and the control register that resets is delivered to each logic gates input end respectively, or the position signal of the warm reset signal of CPU and the control register that resets is delivered to each logic gates input end respectively; The output terminal of each logic gates is connected to each external chip reset terminal respectively.
6. according to the control logic circuit of the arbitrary described a kind of house dog of claim 1 to 5, it is characterized in that: described control logic circuit can be realized by the CPLD-XC95288XL-10ns-PQFP208 chip.
7. the control logic circuit of a kind of house dog according to claim 1, it is characterized in that: a logic gates further is set, the output terminal of this logic gates connects the hand-reset end of described watchdog chip, watchdog chip overflow end and the hand-reset push button signalling is connected to the input end of this logic gates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01279116 CN2519335Y (en) | 2001-12-24 | 2001-12-24 | Controlling logic circuit of gate keeper dog |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01279116 CN2519335Y (en) | 2001-12-24 | 2001-12-24 | Controlling logic circuit of gate keeper dog |
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| CN2519335Y true CN2519335Y (en) | 2002-10-30 |
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| CN 01279116 Expired - Lifetime CN2519335Y (en) | 2001-12-24 | 2001-12-24 | Controlling logic circuit of gate keeper dog |
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Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1312586C (en) * | 2003-05-29 | 2007-04-25 | 中兴通讯股份有限公司 | Apparatus for choosing watchdog function of control watch dog chip |
| CN1323500C (en) * | 2003-11-05 | 2007-06-27 | 中兴通讯股份有限公司 | Function testing method and system for hardware watchdog |
| CN1323355C (en) * | 2002-12-10 | 2007-06-27 | 中兴通讯股份有限公司 | Real-time adjustable reset method and device for watch dog |
| CN100354832C (en) * | 2005-01-05 | 2007-12-12 | 杭州华三通信技术有限公司 | Watch-dog Circuit |
| CN100403227C (en) * | 2006-09-04 | 2008-07-16 | 华为技术有限公司 | Method and device for upper and lower electric treatment of veneer |
| CN100416458C (en) * | 2005-12-09 | 2008-09-03 | 中兴通讯股份有限公司 | Resetting method for preventing system from dead to stop operation by associating software and hardware |
| CN101169679B (en) * | 2006-10-25 | 2010-05-19 | 中兴通讯股份有限公司 | Multiple state reset method and multiple state reset circuit |
| CN101369237B (en) * | 2007-08-14 | 2011-01-05 | 中兴通讯股份有限公司 | Watchdog reset circuit and reset method |
| CN1549542B (en) * | 2003-05-15 | 2011-08-10 | 中兴通讯股份有限公司 | Digital communication system resetting apparatus and method |
| CN101770404B (en) * | 2008-12-31 | 2012-08-15 | 环旭电子股份有限公司 | Watchdog circuit capable of keeping status and method for keeping restart status thereof |
| CN102915258A (en) * | 2012-11-30 | 2013-02-06 | 福建师范大学 | Control method of watchdog circuit |
| CN103676722A (en) * | 2012-09-14 | 2014-03-26 | 英飞凌科技股份有限公司 | Safety system challenge-and-response using modified watchdog timer |
| CN103713960A (en) * | 2012-09-29 | 2014-04-09 | 西门子电力自动化有限公司 | Watchdog circuit used for embedded system |
| US8764636B2 (en) | 2005-06-21 | 2014-07-01 | Olympus Medical Systems Corp. | Electronic endoscopic apparatus |
| CN105892607A (en) * | 2016-04-01 | 2016-08-24 | 上海斐讯数据通信技术有限公司 | Circuit and method for preventing switch from being repetitively reset |
| CN111309508A (en) * | 2020-02-18 | 2020-06-19 | 西安微电子技术研究所 | Embedded type satellite-borne computer watchdog circuit and working method thereof |
-
2001
- 2001-12-24 CN CN 01279116 patent/CN2519335Y/en not_active Expired - Lifetime
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| CN1323355C (en) * | 2002-12-10 | 2007-06-27 | 中兴通讯股份有限公司 | Real-time adjustable reset method and device for watch dog |
| CN1549542B (en) * | 2003-05-15 | 2011-08-10 | 中兴通讯股份有限公司 | Digital communication system resetting apparatus and method |
| CN1312586C (en) * | 2003-05-29 | 2007-04-25 | 中兴通讯股份有限公司 | Apparatus for choosing watchdog function of control watch dog chip |
| CN1323500C (en) * | 2003-11-05 | 2007-06-27 | 中兴通讯股份有限公司 | Function testing method and system for hardware watchdog |
| CN100354832C (en) * | 2005-01-05 | 2007-12-12 | 杭州华三通信技术有限公司 | Watch-dog Circuit |
| US8764636B2 (en) | 2005-06-21 | 2014-07-01 | Olympus Medical Systems Corp. | Electronic endoscopic apparatus |
| CN100416458C (en) * | 2005-12-09 | 2008-09-03 | 中兴通讯股份有限公司 | Resetting method for preventing system from dead to stop operation by associating software and hardware |
| CN100403227C (en) * | 2006-09-04 | 2008-07-16 | 华为技术有限公司 | Method and device for upper and lower electric treatment of veneer |
| CN101169679B (en) * | 2006-10-25 | 2010-05-19 | 中兴通讯股份有限公司 | Multiple state reset method and multiple state reset circuit |
| CN101369237B (en) * | 2007-08-14 | 2011-01-05 | 中兴通讯股份有限公司 | Watchdog reset circuit and reset method |
| CN101770404B (en) * | 2008-12-31 | 2012-08-15 | 环旭电子股份有限公司 | Watchdog circuit capable of keeping status and method for keeping restart status thereof |
| CN103676722A (en) * | 2012-09-14 | 2014-03-26 | 英飞凌科技股份有限公司 | Safety system challenge-and-response using modified watchdog timer |
| CN103676722B (en) * | 2012-09-14 | 2016-09-14 | 英飞凌科技股份有限公司 | Use interrogation and the response of the security system of the watchdog timer of amendment |
| CN103713960A (en) * | 2012-09-29 | 2014-04-09 | 西门子电力自动化有限公司 | Watchdog circuit used for embedded system |
| CN103713960B (en) * | 2012-09-29 | 2017-11-14 | 西门子电力自动化有限公司 | Watchdog circuit for embedded system |
| CN102915258A (en) * | 2012-11-30 | 2013-02-06 | 福建师范大学 | Control method of watchdog circuit |
| CN105892607A (en) * | 2016-04-01 | 2016-08-24 | 上海斐讯数据通信技术有限公司 | Circuit and method for preventing switch from being repetitively reset |
| CN111309508A (en) * | 2020-02-18 | 2020-06-19 | 西安微电子技术研究所 | Embedded type satellite-borne computer watchdog circuit and working method thereof |
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CX01 | Expiry of patent term |
Expiration termination date: 20111224 Granted publication date: 20021030 |