CN2245307Y - Full duplex transfer device for simplex unit - Google Patents

Abstract

The utility model relates to a full duplex transfer device for simplex units, characterized in that voice analog signal are compressed and transmitted in share time. The structure of the full duplex transfer device comprises a simplex unit interface, a sync signal generator, a logic chip selection circuit, a standard recording and reproducing circuit, a double frequency recording and reproducing circuit and an intermediate memory register assembly. Audio sending signal coming from a simplex unit is stored in a standard rate after analog-to-digital conversion, then taken out in a double frequency rate, and sent out by the simplex unit after digital-to-analog conversion. The compressed analog signal that is received is stored in a double frequency rate after analog-to-digital conversion, then taken out in a standard rate, and achieves voice recovery after digital-to-analog conversion. Each of the talking two parties uses 1/2 of a preset cycle to complete voice information exchange under a full sequence, so that the simplex unit can achieve a duplex operation mode.

Description

The full duplex conversion equipment of simplex unit

The utility model belongs to a kind of radio communication isolated plant, specifically expands to the isolated plant that the duplex communication pattern designs for existing simplex mode communication equipment.

Intercom with simplex mode work is that simplex unit is modal a kind of.As a kind of mobile communication facility, because the working frequency range background noise is little, the electric wave loss is that other wireless communication frequency band is incomparable for a short time.Particularly used widely in fields such as point duty, security, production scheduling, field works because its networking cost is cheap.In recent years, be able in fast development aspect the civilian wireless network owing to having solved the technology barrier that intercom enters local network.Yet the simplex unit deadly defect has limited its development, and the simplex mode of Here it is simplex unit determines to realize by ptt switch the conversion of " receipts " and " sending out ", and user manually ptt switch finishes the conversion of giving orders or instructions and receiving words.The compounding practice of this " hand " and " mouth " and usefulness often makes unprofessional user feel extremely inconvenience, sometimes even can lose important information, causes communication failure.It is more outstanding that this weakness shows when simplex unit enters local network, almost is difficult to realize once successful communication when particularly partner does not know to be the simplex unit networking.For overcoming this weakness of simplex unit, the technical staff has made a large amount of research, has proposed multiple improvement project: 1. ptt switch is changed the quasi-duplex scheme that realizes automatically with voice.See " simplex channel duplexer " (ZL93215698.3).Its core technology is to realize automatic control to ptt switch by voice signal, and the difficulty of the user of intercom is removed from " mouth " and " hand " coordinated manipulation produces the effect of similar portable phone.Common intercom is loaded onto this auxiliary equipment by the simplex unit interface and is truly had very big performance to improve along with the further improvement to this technical scheme, its antijamming capability, all there is breakthrough aspects such as reliability, normal talking on effect near portable phone, but it must can only be called quasi-duplex unexpectedly, be still single worker's pattern in fact, must want the weakness of drop-out in the time of also just can't overcoming double talk.Particularly both sides are in arguement, or all want to rob when talking about, and whom can't receive the other side's information with regard to.This weakness is that this type of technical scheme is unsurmountable.2. use compression digital signal timesharing " receipts " " to send out " the full duplex scheme that realizes.Recently external specialized companies compression digital signal timesharing technical scheme of transmission that released one after another.This scheme is that analog voice signal is carried out the A/D conversion with the standard sampling rate, deposit in respectively in each side's intercom memory, by automatic realization the in the cycle of setting ptt switch is changed synchronously then, respectively issue in the other side's machine after the audio digital signals compression with both sides and store with 1/2 time timesharing busy channel, and then read with standard speed respectively, can realize the communication under the full-time preface state of both sides like this, promptly real duplex communication effect.Yet simplex unit delimited in UHF and VHF frequency range, and its channel spacing is 25KHZ and 12.5KHZ.Owing to particularly to the hand-held confidential smaller volume of asking, and will have higher noise recently to overcome the specific conditions such as influence that block loss in the mobile communication, make it can't adopt adaptive technique., the digital coding mode can not adopt the ADPCM coding so can only taking PCM.The sample intelligence amount of A/D conversion is 64KBit like this.If adopt the pattern of 1 times of digital compression to transmit, it takies frequency range and is not less than 128KHZ for each channel, can cause with 25KHZ six channels at interval and disturb, and this is that the radio control system is unallowed.Also be that this technology case pushes away the very big obstacle that expands application.According to above analysis as can be seen, under existing condition, the full duplex of existing simplex unit is improved technical scheme and be still waiting further improvement.

Goal of the invention of the present utility model provides a new solution that simplex unit is improved to the full-duplex communication mode, the full duplex conversion equipment of a simplex unit promptly is provided, this device is realized the compression timesharing transmission of analog signal by the compressed digital technology, thereby implements real simplex unit duplex communication pattern guaranteeing not exceed under the principle of simplex unit channel width.

The utility model key content is that the transformation digital data transmission that contracts is compressed analog signal transmission.General voice analog signal frequency is 300HZ-4KHZ, and promptly maximum frequency range is 4KHZ, compresses one times of highest frequency and increases to 8KHZ.Thereby the frequency range that the compressed analog signal transmission can not exceed channel in the V/U frequency range limits.If can realize the technical conceive of timesharing transmission, then the diplex operation mode of simplex unit might realize.The key of problem is how to go to realize the compression scheme of voice analog signal.Compression digital signal is transmitted in technical very simple, and the clock frequency that need only improve digital baseband signal gets final product.But just can not directly finish analog signal compression transmission.When adopting the magnetoelectricity direct-recording system, the scheme of fast speed playback can't realize.Because transfer delay is recorded, put to record, the physical dimension of putting head, the sending and receiving Synchronous Processing all can not realize in portable simplex unit.In addition, audio analog signals is made up of the numerous single-tone of certain bandwidth, and the frequency and the amplitude of each single-tone have randomness.The amplitude of tone signal, phase place all can't gone through frequency multiplication, the back reproduction of resetting.Again the serious naturally distortion of He Cheng analog signal is so that be unable to recognize at all.So want to realize that by frequency multiplication the analog signal compression also is impracticable.Be left unique scheme and only do the compression that intermediate treatment realizes analog signal by digitizing technique.Promptly earlier analog signal conversion is become digital signal, after finishing compression and handling, carry out digital-to-analogue conversion again, the analog signal after obtaining compressing.Analog signal after the compression is that information exchange is finished in available 1/2 time timesharing, thereby realizes the duplex communication mode of simplex unit, this just this reality novel design philosophy is arranged.It is perhaps not difficult to release the design's thought from the shortcoming of digitized voice signal transmission, but because communicating pair all needs from the analog signal to the digital signal, change into analog signal from digital signal again, middle compression in addition, restore a series of complex process, and will guarantee the phase relation of strict synchronism on the sequential, make specific embodiment, particularly the synchronous sequence management becomes very complicated, this key also of the present utility model just and creation point.

For realizing above key, take the frequency of audio frequency lower limit among the design as synchronizing signal, and the simulated audio signal after making synchronizing signal with compression sends, and is received as the other side's pressure external synchronization signal, and mutual correction realizes the anti-phase synchronous design of communicating pair strictness.And control whole digitization of speech signals, compression, digital-to-analogue conversion, emission, reception and restore the sequential benchmark of handling by the fractional frequency signal of synchronizing signal, realize strict synchronously.Concrete design is as follows: in the structure still according to the control circuit that has the simplex unit interface that is connected with the simplex unit main frame and ptt switch to change, also comprise synchronous generator in the structure, logic chip select circuit, standard playback circuitry, frequency multiplication playback circuitry and distributor group.The local synchronous signal that synchronous generator produces is the reference signal of management local circuit work schedule, is again to guarantee the strict anti-phase synchronous cue with the communication party.Thereby, external synchronization signal from the simplex unit interface is delivered to synchronous generator, proofread and correct the local synchronous signal phase place by external synchronization signal, the local synchronous signal that this partial circuit generated is delivered to the modulation input of simplex unit again by the simplex unit interface, send to the external synchronization signal of communication counterpart as it with audio signal.The selectable frequency range of local synchronous signal is 280HZ-360HZ, to choose 300HZ for well.This part circuit also produces 60 fractional frequency signals and 120 fractional frequency signals are each circuit of this machine sequential benchmark of conversion work state on time.Wherein 60 fractional frequency signals are delivered to the ptt switch control end in the simplex unit interface respectively, the reading and writing control end of logic chip select circuit control end and frequency multiplication playback circuitry.Its effect is the automatic conversion of controlling ptt switch with 1/2 setting cycle, and the logic chip select circuit is selected the distributor operating state, and the record of frequency multiplication playback circuitry, puts conversion.As to select 30OHZ synchronizing signal, its change-over time be 200ms.Also generate 120 fens vertical synchronizing signals from synchronous generator and also deliver to logic chip select circuit control end, this signal is that setting cycle is a 400ms distributor operating state at interval, for ensureing the multiple reading and writing state under two kinds of speed, should add delay circuit between 120 fractional frequency signals and 60 fractional frequency signals, distribute to guarantee rational sequential.

Logic chip select circuit among the design is mainly used to control distributor group operating state.Because analog signal-digital signal intermediate treatment complexity, and sequential is strict, and also just loaded down with trivial details and strict from the operation of distributor reading and writing.So except timing control signal from synchronous generator, the gating signal input of logic chip select circuit is connected to the state control signal output of standard playback circuitry and frequency multiplication playback circuitry respectively, promptly transmit the status signal of recording playback unit, with the sequential relations of distribution of decision recording playback unit and distributor.Directly transport to the distributor group by the sheet gating control signal that the logic chip select circuit sends.

Standard record, discharge road and frequency multiplication playback circuitry are the groundwork circuit among the design.The notion of standard recording playback is that the cpu clock frequency of setting wherein is a benchmark.Cpu clock frequency in the frequency multiplication playback circuitry is its 2 times.The multiple relation of working frequent by both realizes the analog signal compression and restores.Because both shared distributors are so both buses link to each other with distributor.The ACL line of both CPU links to each other with the ACL line of simplex unit master cpu (not having the simplex unit utilization start of CPU to set current potential links to each other with the ACL line of between the two CPU).The standard playback circuitry is introduced the audio signal that Mic sends from the simplex unit interface, deposits distributor in reference speed after the A/D conversion; The received audio signal (digitlization) that also will deposit distributor simultaneously in takes out with reference speed, transports to the simplex unit interface and introduce its SP mouth after digital-to-analogue conversion.The frequency multiplication playback circuitry is to read the digitized voice signal (being equivalent to compression) that has existed wherein for 2 times with reference speed rate from distributor, export the simplex unit interface again to through digital-to-analogue conversion formation compressed analog signal and deliver to its modulation input, what send through simplex unit like this promptly is the compressed analog signal that contains the 300HZ synchronizing signal again, and its time of accounting for is 1/2 of setting cycle.Other 1/2 cycle simplex unit is received is compressed analog signal (containing synchronizing signal) from the other side's mobile phone, its compressed analog signal of being drawn by the frequency discriminator of simplex unit is sent into the frequency multiplication playback circuitry through the simplex unit interface, after analog-to-digital conversion, deposit the storage slice, thin piece of distributor group appointment in 2 times of reference speed rate, the shared time also was 1/2 cycle, be 200ms, at this moment deposit in this memory promptly is the digitized voice signal of receiving the other side, need only take out (being equivalent to restore) with standard speed, can obtain the whole voice messagings to being sent in the one-period through digital-to-analogue conversion again.Because standard playback circuitry and frequency multiplication playback circuitry have a distributor group, the reading and writing conversion just needs the strict sequential relations of distribution.Sound at standard playback circuitry and frequency multiplication playback circuitry in the design has a timing distribution circuit.Concrete scheme can increase a frequency division phase shifter in the frequency multiplication playback circuitry.The frequency division phase shifter takes out clock frequency signal from the frequency multiplication playback circuitry and does and deliver to the standard playback circuitry after the time-delay two divided-frequency is handled and do that the outer of CPU draws the clock frequency signal its control unit, thereby plays the effect that sequential is distributed.

Cause the synchronizing signal output control switch of synchronous generator from the off hook signal of simplex unit master cpu by the simplex unit interface, it is actually the switch of setting with single worker's handset compatibility in the communication.There is the simplex unit of establishing CPU the enabling signal that the mode of high potential replaces off hook line to transmit to be set with starting switch.

Be not difficult to find out according to above analysis, according to the made full duplex conversion equipment of above structural framing, can link to each other with its motherboard by the simplex unit interface, and by to generating digitized voice signal after the voice signal analog-to-digital conversion, storage and reading of two times of speed by standard speed are realized the digital signal compression, obtain compressed analog signal through digital-to-analogue conversion again, this moment, signal frequency should be between 600HZ-8KHZ.Control the modulation input stage of simplex unit with this compressed analog signal, wireless transmission is actually compressed analog signal like this.Realize respectively accounting for 1/2 cycle exchange both sides' voice messaging by 60 fractional frequency signals control PTT conversion with signal.The compressed analog signal of receiving is a compression digital signal through analog-to-digital conversion again, writes memory under the twice standard speed, reads with standard speed again, obtains restoring digital signal, is reduced into standard analog signal through digital-to-analogue conversion again and sends into simplex unit SP mouth and emit.Its shared time also was 1/2 cycle.Though its process complexity, simultaneous techniques are also difficult, because large scale integrated circuit is very ripe at present, it is not difficult to implement above design.

How further specify goal of the invention of the present utility model below in conjunction with the embodiment accompanying drawing realizes:

Fig. 1 has novel structured flowchart for this reality.

Fig. 2 is the electric principle schematic of synchronous generator.

Fig. 3 is the electric principle schematic of logic chip select circuit.

Fig. 4 is the electric principle schematic of standard playback circuitry.

Fig. 5 is the electric principle schematic of frequency multiplication playback circuitry.

Fig. 6 is the electric principle schematic of distributor group.

Wherein 1 represent the simplex unit interface, the Mic mouth of 101 pin order worker machine host plates wherein, 102 pin connect the SP mouth of simplex unit, 103 pin connect simplex unit ptt switch control end, 104 pin connect the ACL pin of simplex unit master cpu or connect the high potential that simplex unit is set, 105 pin are connected to the modulation input of simplex unit, and 106 pin connect the final stage output of simplex unit frequency discriminator, and 107 pin connect the off hook signal output part of simplex unit master cpu or connect the hot end that simplex unit (not having CPU's) switch is provided with.2 represent synchronous generator, wherein 201 represent phase controller, and 202 represent synclator, and 203 represent frequency dividing circuit, and 204 represent delay circuit, and 205 represent frequency-halving circuit.3 represent the logic chip select circuit.4 represent the standard playback circuitry, wherein 401 represent a writing controller, 402 a representative Read Controller, and 403 represent filter, and 404 represent audio amplifier circuit.5 represent the frequency multiplication playback circuitry, wherein 501 represent frequency multiplication recording playback controller, and 502 represent filter, and 503 represent trapper, and 504 represent the frequency division phase shifter.6 represent the distributor group, and wherein 601-604 represents static storage.IC1-IC21 represents integrated circuit block.Related CE among the figure, OE, WE, it is effective that the WR mouth is negative potential.

From structured flowchart of the present utility model and given example electrical schematic diagram as can be seen:

Synchronous generator (2) is by phase controller (201), synclator (202), and frequency dividing circuit (203), delay circuit (204) and frequency-halving circuit (205) are formed.Because the design's purpose is the communication pattern that simplex unit will be converted into full duplex, so will 1/2 time see the voice messaging of both call sides (compressed analog signal) respectively off with preceding 1/2 time and back in the cycle of regulation, this just needs " receipts ", " sending out " strictness anti-phase synchronous of communicating pair.Consider audiorange 300-4KHZ, after the frequency multiplication 600-8KHZ, if sending and getting 200ms is that " receipts " " send out " conversion interval, the voice messaging amount that needs so to transmit is 400ms, synchronizing signal should be chosen between the audio frequency lower limit 280HZ-360HZ, the present embodiment reference value is 300HZ, is easy to separate with the compressed analog signal mixed transport time.Phase controller (201) promptly is designed according to above design.Receive phase controller (201) from the phase locator qualification signal that the external synchronization signal and the synclator (202) of simplex unit interface (1) 105 pin sends, limit the strict anti-phase relation of external synchronization signal and local synchronous signal with this.By phase controller (201) draw anti-phase (with external synchronization signal comparatively speaking) signal transports to the adjusting control end of synclator (202), its purpose is that 300HZ synchronizing signal and the external synchronization signal of forcing this machine to produce are anti-phase.The oscillation signals according that synclator (202) is produced can be very fast anti-phase synchronously with the other side's synchronizing signal.This signal opens synclator (202) output and delivers to respectively: 1. 105 pin of simplex unit interface (1), and its effect is the modulation input that causes single worker's mobile phone, mixes with compressed analog signal and issues the other side's mobile phone; 2. frequency dividing circuit (203), its purpose are with the local synchronous signal to be the timing management signal that benchmark obtains other circuit of control.Clock signal through frequency dividing circuit (203) frequency division gained is delivered to respectively: 1. 103 pin of simplex unit interface (1), its effect is the conversion of control ptt switch, as get the 300HZ synchronizing signal, and can obtain the clock signal of 50HZ behind 60 frequency divisions, the every 200ms conversion of decision ptt switch is once; 2. logic chip select circuit (3), its effect are to produce gating signal as clock signal; 3. the reading and writing control end of frequency multiplication playback circuitry (5), its effect are that the every 200ms of control two-forty state " reading " and " writing " down changes once.Institute's frequency division clock signal also will be done through delay circuit (204) from 203 outputs and deliver to frequency-halving circuit (205) after phase shift is handled.With frequency-halving circuit (205), the signal of output is delivered to another control end (CK0) of logic chip select circuit (3) again.The trailing edge time of occurrence that the effect of delay circuit (204) is to use the synchronizing signal of the 400ms that two divided-frequency comes out and 200ms synchronizing signal at interval, to guarantee the reasonable distribution of entire circuit work schedule.

2 embodiment that provide can further find out with reference to the accompanying drawings, and the phase controller (201) in the synchronous generator (2) is made up of the low-pass filtering limiting amplifier of operational amplifier (IC3:A), diode D2, voltage-stabiliser tube D1 and peripheral Resistor-Capacitor Unit formation and the phase-shift discriminator that NAND gate (IC18:D) constitutes.External synchronization signal passes through capacitor C 29 from 106 pin of simplex unit interface (1), resistance R 29, the compressing audio signal of the low pass filter elimination 600-8KH Z that operational amplifier (IC3:A) is formed, detect the input that the 300HZ external synchronization signal send big NAND gate (IC18:D), the phase locator qualification signal that comes autosynchronized oscillator (202) (being the inversion signal of local synchronous signal) that another input of NAND gate (IC18:D) is sent into.Above structure can be exported a negative pulse at local synchronous signal and external synchronization signal with phase time, forces the local signal phase shift.Phase synchronization signal exports synclator (202) to from NAND gate (IC18:D), and its result's formation forces anti-phase synchronous.It is anti-phase synchronous that the local synchronous signal that is sent makes the other side force again, can realize the strict anti-phase synchronous of communicating pair like this in very short time.Synclator (202) is by triode BG1, and the phase-adjusting circuit that the oscillating circuit that two collection utmost point diode BG2 and peripheral Resistor-Capacitor Unit are barricaded as and three NAND gate (IC18:ABC) are barricaded as is formed.The 300HZ local synchronous signal that oscillator (202) produces send in 105 pin of simplex unit interface (1) through capacitor C 22, and this signal can send to the other side and do external synchronization signal.Cause the input of NAND gate (IC18:D) with the anti-phase signal of locator qualification mutually of local synchronous signal, also deliver to frequency dividing circuit (203) simultaneously.Seal in an electronic analog swtich (IC16:A) in the output of IC18:A and the input of IC18:C, its objective is and eliminate synchronous noise when being convenient to change single worker's pattern.The control end of electronic switch (IC16:A) is connected on 107 pin of simplex unit interface (1), the off hook signal controlling that taken place by the simplex unit master cpu.Frequency dividing circuit (203) is by two integrated circuit 74LS90 (IC14, one 60 frequency divider that IC15) is barricaded as.60 fractional frequency signals that it generated are benchmark clock signals of this machine work, and it delivers to 103 pin and the delay circuit (204) of frequency multiplication playback circuitry (5), logic chip select circuit (3), simplex unit interface (1) respectively.The setting of delay circuit (204) is to come from the needs that the design's sequential is distributed.Concrete this circuit is by comparison amplifier (IC21:A), diode D3, potentiometer W2, the phase shifter that W3 and Resistor-Capacitor Unit are barricaded as.The timing control signal of 60 frequency divisions is delivered to frequency-halving circuit (205) through the delay of 0.5-1ms.Frequency-halving circuit (205) is by integrated package 74LS74 (IC17:A, B) frequency divider that is barricaded as, its 120 frequency division time delayed signals that generate local synchronous signal are delivered to another control end (CK0) that logic chip send circuit (3), this deration of signal is 400ms, is used for the timing control signal as logic chip circuit (3).

That accompanying drawing 3 is given is the embodiment of the utility model logic chip select circuit (3).Specifically be by 10 not gates (IC9, IC10:A, B, C, D), 8 NAND gate (IC11, IC12) and four NOR gate (ICB:A, B, C, a sequential that D) is barricaded as is sent the messenger generator.The frequency dividing circuit (203) of sheet gating timing control signal motor synchronizing signal generator (2) and frequency-halving circuit (205) cause this circuit input (CK1, CK0).State control signal is reaction normal playback circuitry (4), or the reading and writing of frequency multiplication playback circuitry (5) requirement.State control signal is introduced the State Control end of this circuit from standard playback circuitry (4) and frequency multiplication playback circuitry (5).Requiring to carry out logical combination according to sequential, state produces slice and send messenger can guarantee that the data timesharing in the distributor group (6) transmits data in different reading and writing slice, thin pieces.The sheet gating signal that is produced causes the gating signal input of distributor (6) from four NOR gate (IC13) output.Because the setting of delay circuit (204) and frequency division delay circuit (504) makes the sequential that 2-2.5us is arranged between the sheet gating signal can fully guarantee the sequential distribution of common data bus under many reading and writing state at interval.

What accompanying drawing 4 was given is the electric principle schematic of embodiment standard playback circuitry (4).Standard record Power Generation Road (4) is made up of 4 parts among the embodiment: a writing controller (401), a Read Controller (402), filter (403) and audio frequency amplifier (404).Mic signal from simplex unit interface (1) 101 pin is introduced a writing controller (401), the Mic signal of an input writing controller (401) becomes digitized voice signal through analog-to-digital conversion therein, and then exports a certain appointed slice, thin piece in the distributor (6) to.The speed that write this moment is standard setting speed, and the shared time is identical with the time of giving orders or instructions, but one of every 400ms conversion has the storage slice, thin piece, to guarantee when the slice, thin piece that has write is read out, does not influence the signal storage under the full-time preface.Because this circuit is in full-time preface and " writes " state, so be called a writing controller.A Read Controller (402) is in full-time preface and " reads " state at the same time.Deposit in a certain slice, thin piece of distributor group (6) after the compressed analog signal digitlization that communication counterpart is received, the memory space that it occupied is identical.Import a Read Controller (402) from the compressed digital voice signal that distributor (6) extracts, take standard speed because of reading in, be the standard digital voice signal so the signal of an input Read Controller (402) just restores naturally, after its digital-to-analogue conversion, form simulated audio signal input filter (403).Remove owing to deliver to amplification in the audio amplifier circuit (404) behind the quantization noise that processing procedure causes again, deliver to 102 pin of simplex unit interface (1) again, promptly lead to simplex unit SP mouth, standard playback circuitry (4) role as can be seen, be digitization of speech signals to be stored to get off with selected standard speed, or the digital speech signal received read with standard speed, expansion being recovered to the normal voice signal.What be to guarantee that " receipts " " send out " hockets, and it is divided into two unit distinguishes full-time prefaces and " reads " or " writing ", and each cycle (400ms) is changed the storage slice, thin piece that docks.From the electrical schematic diagram as can be seen a writing controller (401) and a Read Controller (402) all adopt digital recorder integrated package TC8830F (IC1, IC2), the WR ground connection of the former (401), the RD pin is put high potential, has so just guaranteed that it is in " writing " state forever.The latter's (402) RD ground connection, WR puts high potential, has so just guaranteed that it is in " reading " state forever.The WE pin of memory (6) in the middle of the reading and writing control signal (R/W) of the two is delivered to, the OE that sends into the corresponding slice, thin piece of distributor (6) through the read-write control signal of inverter (IC21:C) holds.The ACL line in the ACL line of the two and the frequency multiplication playback circuitry (5) and the ACL line of simplex unit master cpu link to each other.The clock frequency of two integrated packages determines its sampling rate, so the clock frequency between frequency multiplication playback circuitry (5) and the standard playback circuitry (4) should be 2 times of relations.Can take two frequencys multiplication, also can take the mode of two divided-frequency to solve.What present embodiment provided is the two divided-frequency scheme.So (frequency division that IC1, clock frequency input pin (XIN) IC2) are connected on frequency multiplication playback circuitry (5) is respectively shifted to two outputs of phase device (504) to these two integrated packages.Embodiment median filter (403) is by R6, the low-pass filter circuit that C5 forms, audio amplifier circuit (404) then is barricaded as by operational amplifier (IC3:D) and peripheral Resistor-Capacitor Unit, is connected to 102 pin of simplex unit interface (1) after filtering is amplified from the audio signal of the DAO pin of a Read Controller (404).

Frequency multiplication playback circuitry (5) is by frequency multiplication recording playback control device (501), and filter (502) trapper (503) and frequency division phase shifter (504) are formed.Deliver to frequency multiplication recording playback controller (501) from the digitized voice signal of middle memory sets (6).This signal that it took out just a writing controller (401) in the information of a last 400ms typing.It is so big that the amount of information of being taken out remains, and only the sampling rate of frequency multiplication recording playback controller (501) is the twice of writing rate, promptly all takes out with 200 milliseconds of times.Realized the compression of digital signal in fact.Promptly form 200 milliseconds compression analog voice signal after the compression again through digital-to-analogue conversion, after it removes quantization noise by filter (502), deliver to 105 pin of simplex unit interface (1), this just becomes the modulation signal of simplex unit, so the voice of 400ms, time that can 200 milliseconds launches.At next 200 milliseconds promptly is the received signal sequential of this machine.Draw by 106 pin of simplex unit interface (1) and deliver to frequency multiplication recording playback controller (501) after the compressed analog signal of receiving is removed the 300HZ synchronizing signal by trapper (503) this moment.This moment, ptt switch transferred " receipts " state synchronously to, and 501 also become " writing " state from " reading " state synchronized.Signal is after 501 process analog-to-digital conversion, and compressed analog signal becomes digital signal, and this digital signal is delivered in the slice, thin piece of a certain gating of distributor (6).Be subjected to the qualification of clock work frequency, its writing speed is identical with this circuit reading speed, finishes writing of 400 milliseconds of speech volume so equally in 200ms.The digital information of being stored is read with standard speed by a Read Controller (402) in one 400 millisecond period, and reaches the SP mouth and emit, and has so just realized the exchange of both sides' language message under the full-time preface fully, promptly realizes the mode of operation of full duplex.In order to guarantee that sequential is distributed and strict synchronized relation, draw the clock work frequency signal by frequency multiplication recording playback controller (501), deliver to frequency division phase shifter (504), clock frequency signal behind secondary time-delay and frequency division is transported to two control units (401 of standard playback circuitry respectively, that 402) 1/2 signal such as frequency multiplication playback circuitry (5) are taked is 1024KHZ, and then 401 and 402 clock work frequency is 512KHZ.The purpose of secondary time-delay is to distribute for " reading " of guaranteeing three control units (501,401,402) " writes " sequential, guarantees under arbitrary " reading " or " writing " state the corresponding relation with institute's gating memory, effective use of assurance data/address bus.In fact delay circuit (204) and frequency division phase shifter (504) and logic chip select circuit (3) altogether role be timing distributor in this circuit, decide memory and " reading " " to write " cooperation of state and the right to use of distribution bus.This part hardware circuit can save, realize the sequential distribution with the method for rewriting the TC8830F internally stored program, also can not select the TC8830F integrated package for use, and adopt unified single chip computer architecture, the centre adds A/D, the mode of D/A converter is finished compression, the recovery of data, and processing such as the compression of analog signal and recovery can realize the communication pattern of full duplex equally.Yet as not reopening the integrated circuit slice, thin piece, volume can't guarantee that reliability also is difficult to realize that its basic design concept is still within category of the present utility model.Among the embodiment of frequency multiplication playback circuitry (5), frequency multiplication recording playback controller (501) also adopts digital recorder integrated package TC8830F, external crystal frequency 1024KHZ reads (RD) and writes (WR) signal end is connected to synchronous generator (2) by a rp-drive (IC10:E) frequency dividing circuit (203) output.Read-write control signal (R/W) is sent into the WE pin of distributor (6), and delivers to the OE pin of the corresponding slice, thin piece of distributor (6) by inverter (IC21:B).It among the embodiment 601,601 OE pin.The T type low pass filter that filter (502) is made up of R3, R14 and C9, this filter (501) are connected between 105 pin of the DAO pin of frequency multiplication recording playback controller (501) and simplex unit interface (1).Trapper (503) is by two operational amplifier (IC3:B, C), potentiometer W1, reach the 600-8KHZ band pass filter that peripheral Resistor-Capacitor Unit is barricaded as, the synchronizing signal of 300HZ can not be passed through, make the compressed voice signal of the Micn pin of transporting to frequency multiplication recording playback controller (501) remove synchronization noise, improved communication quality.Frequency division phase shifter (504) be by integrating circuit (R33, C30) and a rp-drive (IC10:F), four NAND gate of a reverse trigger (IC21:A) and two the three secondary time-delay frequency dividing circuits that NAND gate is barricaded as.IC10:F can select 74LS06 for use, and IC21:A selects 74LS14 for use, control delay time 0.5us, and the clock signal of transporting to standard playback circuitry (4) the like this phase bit that just staggered, what remaining NAND gate was barricaded as is an odd even pulse separator.Just staggered under the crystal oscillator signal controlling sequential of 0.5-1us of clock in such 501,401,402 3 integrated packages, this will guarantee the reasonability on the bus assignment.Draw the input that clock frequency signal is connected to this circuit rp-drive (IC10:F) from the XOUT pin of frequency multiplication recording playback controller (501).(IC20:A B) draws the outer clock frequency pin (XIN) that draws of delivering to a writing controller (401) and a Read Controller (402) to the time-delay fractional frequency signal of gained from two three NAND gate respectively after handling.

The amount of information size that each cycle stores is mainly depended in the selection of distributor group (6).With big storage capacity device add the program area management perhaps a memory just can finish.The given situation of present embodiment is the cycle of taking 400ms, and the inversion frequency of 20ms when the standard time clock frequency of 512KHZ and the frequency multiplication recording playback of 1024KHZ are operated, can not add any software in addition and participate in, and the distributor group of configuration.According to the technical characteristic of TC8830F slice, thin piece, add that suitable support circuit can only use 2 or 3 memories, get 4 static random memories for well but consider that various kind property are sent.Particularly select the HM62256LP sheet period of the day from 11 p.m. to 1 a.m for use, the circuitry that its storage capability and the utility model embodiment provide is more supporting, so distributor group (6) can be made up of 2-4 static storage, to get 4 slice, thin pieces be example to send, and the gating signal control end of each slice, thin piece is connected to the corresponding control pin of logic chip select circuit (3).The bus of memory links to each other with the bus of standard playback circuitry (4) with frequency multiplication playback circuitry (5), and the WE pin of all slice, thin pieces (601-604) links to each other with standard playback circuitry (4) (R/W) pin with letter frequency playback circuitry (5).The OE pin of 601,602 slice, thin pieces is accepted the control signal from 501, and 603,604 OE pin is accepted the control signal from 401,402.Only write 601,602,402 from 603,604 reading of data from 401 data in fact, 501 read from 601,602, write to 603,604.

For after technical scheme that the utility model proposes is implemented can and common simplex unit compatibility, can in frequency multiplication recording playback controller (501), preset specific DTMF duplex control code data, and the P0-P3 mouth of this slice, thin piece directly linked to each other with the data/address bus of simplex unit master cpu, when this machine sends the DTMF address code and carries out paging, in succession specific DTMF duplex control data sign indicating number is sent, and put this machine simultaneously in the diplex operation state.Should in this device, set up a decoder simultaneously.When being exhaled simplex unit to receive selective call signal and after the sign indicating number that solved by decoder confirmed by the simplex unit master cpu, automatically will be placed the diplex operation state by pager, notify the user to start shooting, and off hook signal takes place simultaneously local synchronous signal is produced and send and send out the duplex sign indicating number to the main simplex unit of exhaling, lead exhales duplexer to confirm after the duplex communication mode set up.If both sides have one to be simplex unit, the master cpu of simplex unit can not place simplex unit the single-simplex operation mode automatically when having specific DTMF duplex control code input, and both sides still can continue communication under simplex mode.Consider that some simplex unit does not possess CPU, then can add a 300HZ synchronizing signal identifier and an Auto-delay switch circuit at this device.The input of 300HZ synchronizing signal identifier is connected on the output of IC3:A, and can lock Auto-delay switch can under numerical time, receive the 300HZ signal continuously the time, as the synchronizing signal that can not receive 300HZ surpass the regulation delay time then Auto-delay switch can automatically duplexer be placed single-simplex operation state this moment in this way the conversation between the duplexer can guarantee locked with automatic switch, either party is that the simplex unit duplexer of all can resetting is a simplex state, can realize compatible communication easily like this.

In sum, use this device can make the simplex mode be converted to the communication mode of full duplex, it is a desirable feasible program that realizes analog signal compression timesharing transmission by digital processing technology, its single channel frequency range is lower than 8KHz, does not influence the principle of U/V channel division, has fundamentally overcome the defective of conventional art, complete through its message transmission of analogue test, the distortion factor is little, and communication quality can be beautiful with portable phone effect ratio, is a new solution that is worthy of popularization.

Claims (10)

1, a kind of simplex unit full duplex conversion equipment comprises simplex unit interface (1) and ptt switch conversion control circuit part in the structure, it is characterized in that:

Also comprise synchronous generator (2) in a, the structure, logic chip select circuit (3), standard playback circuitry (4), frequency multiplication playback circuitry (5) and distributor group (6),

B, deliver to synchronous generator (2) from the external synchronization signal of simplex unit interface (1) 106 pin, be connected to the emission modulation input of simplex unit by 105 pin of simplex unit interface (1) from the local synchronous signal of synchronous generator (2) generation, 103 pin that 60 fractional frequency signals that produced are delivered to simplex unit interface (1) respectively connect the ptt switch control end, the CK1 end of logic chip select circuit (3) and reading of frequency multiplication playback circuitry (5), write control end, 120 fractional frequency signals that generated from synchronous generator (2) are delivered to the CKO end of logic chip select circuit (3)

The gating signal input of c, logic chip select circuit (3) is connected to the status signal output (E1-E4) of standard playback circuitry (4) and frequency multiplication playback circuitry (5) respectively, and its sheet gating control signal is transported to distributor (6),

D, the bus of standard playback circuitry (4) and frequency multiplication typing circuit (5) links to each other with distributor (6), the ACL line of its CPU links to each other with the ACL line of simplex unit master cpu, standard playback circuitry (4) is introduced audio signal from MIC from 101 pin of simplex unit interface (1), simultaneously the audio signal that receives is introduced the SP mouth by 102 pin of simplex unit interface (1), 105 pin of receiving simplex unit interface (1) from the compressed analog signal of frequency multiplication playback circuitry (5) output cause the modulation input of simplex unit, send into frequency multiplication playback circuitry (5) from the compressed analog signal that the simplex unit frequency discriminator sends through 106 pin of simplex unit interface (1)

E, cause the synchronizing signal output switch of synchronous generator (2) by 107 pin of simplex unit interface (1), or 107 pin high potentials be set by the simplex unit starting switch from the off hook signal of simplex unit master cpu,

F, by the frequency division phase shift clock signal of frequency multiplication playback circuitry (5) output to standard playback circuitry (4).

2, according to the said full duplex conversion equipment of claim 1, it is characterized in that synchronous generator (2) is by phase controller (201), synclator (202), frequency dividing circuit (203), delay circuit (204) and frequency-halving circuit (205) are formed, the phase locator qualification signal that sends from the external synchronization signal and the synclator (202) of simplex unit interface (1) 105 pin is connected to phase controller (201), the anti-phase synchronizing signal that phase controller (201) is drawn is to the regulation and control end of synclator (202), deliver to 105 pin and the frequency dividing circuit (203) of simplex unit interface (1) respectively by the local synchronous signal of synclator (202) output, with frequency division gained clock signal deliver to respectively simplex unit interface (1) 103 to the ptt switch control end, a control end (CK1) (3) of logic chip select circuit and reading of frequency multiplication playback circuitry (5), write control end, fractional frequency signal is delivered to frequency-halving circuit (205) from 203 outputs after delay circuit (204) phase shift is handled, the control signal of frequency-halving circuit (205) output is delivered to another control end (CK0) of logic chip select circuit (3).

3, according to the said full duplex conversion equipment of claim 2, it is characterized in that:

A, phase controller (201) are made up of the low-pass filtering limiting amplifier of operational amplifier (IC3:A), diode D2, voltage-stabiliser tube D1 and peripheral Resistor-Capacitor Unit formation and the phase-shift discriminator that NAND gate (IC18:D) constitutes, phase synchronization signal exports synclator (202) to from not gate (IC18:D)

B, synclator (202) are triode BG1; The phase-adjusting circuit that the oscillating circuit that two collector diode BG2 and peripheral Resistor-Capacitor Unit are barricaded as and three NAND gates (IC18:ABC) are barricaded as forms; The local synchronous signal that produces is delivered to 105 pin of simplex unit interface (1); Deliver to input and the frequency dividing circuit (203) of NAND gate (IC18:D) with the anti-phase signal of local synchronous signal; The control end of electronic switch (IC16:A) connects 107 pin of simplex unit interface (1); Seal in synchronizing signal output control switch (IC16:A) in the phase-adjusting circuit

C, frequency dividing circuit (203) be by two integrated package 74LS90 (IC14, the frequency divider that IC15) is barricaded as specifically can be 60 frequency dividers, and 60 fractional frequency signals that generated are delivered to frequency multiplication playback circuitry (5), logic chip select circuit (3) and delay circuit (204) respectively,

D, delay circuit (204) they are by comparison amplifier (IC21:A), diode D3, and potentiometer W2, the phase shifter that W3 and Resistor-Capacitor Unit are barricaded as is delivered to frequency-halving circuit (205) through 60 fractional frequency signals of time-delay,

E, frequency-halving circuit (205) are that (its 120 frequency division time delayed signals that generate local synchronous signal are delivered to another control end (CK0) of logic chip select circuit (3) for IC17:A, the frequency divider that B) is barricaded as by integrated package 74LS74.

4, according to the said full duplex conversion equipment of claim 1, it is characterized in that logic chip select circuit (3) is specifically by 10 not gate (IC9, IC10:ABCD), 8 NAND gate (IC11, IC12) and four NOR gate (IC13:ABCD) be barricaded as a sequential strobe generator, the frequency dividing circuit (203) of sheet gating timing control signal motor synchronizing signal generator (2) and frequency-halving circuit (205) cause the input (CK1 of this circuit, CK0), state control signal is recorded the State Control end that Power Generation Road (4) and frequency multiplication playback circuitry (5) are introduced this circuit from standard, and the sheet gating signal that is generated is drawn in the gating signal input of distributor (6) from four NOR gate outputs.

5, according to the said full duplex conversion equipment of claim 1, it is characterized in that standard playback circuitry (4) is by a writing controller (a 401) Read Controller (402), filter (403), audio frequency amplifier (404) is formed, Mic signal from simplex unit interface (1) 101 pin causes a writing controller (401), after its digitized processing, export distributor (6) to, import a Read Controller (402) from the compressed digital voice signal that distributor (6) extracts, after its digital-to-analogue conversion, form simulated audio signal input filter (403), cause audio amplifier circuit (404) from filter (403) after removing quantization noise, go to 102 pin of simplex unit interface (1) again.

6, according to the said full duplex conversion equipment of claim 5, it is characterized in that a writing controller (401) and a Read Controller (402) can adopt digital recorder integrated package TC8830F (IC1, IC2), the WR pin ground connection of the former (401), the RD pin is put high potential, the latter's (402) RD pin ground connection, the WR pin connects high potential, the read-write control signal of the two (R/W) is delivered to the WE pin of distributor (6), and deliver to distributor (603 through inverter (IC21:C), 604) OE pin, the ACL in the ACL pin of the two and the frequency multiplication playback circuitry (5) and the ACL of simplex unit master cpu link to each other, and the clock frequency input pin (XIN) of the two is connected on frequency division phase shifter (504) output of frequency multiplication playback circuitry (5) respectively.

7, according to the said full duplex conversion equipment of claim 5, it is characterized in that filter (403) is R6, the low-pass filter circuit that C5 forms, audio amplifier circuit (404) is barricaded as by operational amplifier (IC3:D) and peripheral Resistor-Capacitor Unit, through filtering, deliver to 102 pin of simplex unit interface (1) from the audio signal of the DAO pin of a Read Controller (403) after the amplification.

8, according to the said full duplex conversion equipment of claim 1, it is characterized in that frequency multiplication playback circuitry (5) is by frequency multiplication recording playback controller (501), filter (502), trapper (503) and frequency division phase shifter (504) are formed, deliver to frequency multiplication recording playback controller (501) from the digital audio signal of distributor group (6), digital-to-analogue conversion after compression forms compressed analog signal is delivered to simplex unit interface (1) by filter (502) 105 pin, after removing synchronous noise by trapper (503), the compressed analog signal that 106 pin by simplex unit interface (1) are introduced delivers to frequency multiplication recording playback controller (501), digital signal after the analog-to-digital conversion is delivered to distributor (6), draw the clock work frequency signal by frequency multiplication recording playback controller (501) and deliver to frequency division phase shifter (504), transport to two control units (401) of standard playback circuitry (4) through the clock frequency signal of frequency division and secondary time-delay respectively, (402) the outer clock frequency end (XIN) that draws.

9, said according to Claim 8 full duplex conversion equipment, it is characterized in that frequency multiplication recording playback controller (501) also adopts TC8830F digitlization recording playback integrated package, external crystal frequency is 1024KHZ, read (RD), write (WR) signal pins is connected to synchronous generator (2) by a not gate (IC10:E) frequency dividing circuit (203) output, read-write control signal (R/W) is sent into the WE pin of distributor (6), and connect in the distributor (6) 601 and 602 OE pin by inverter (IC21:B), filter (502) is bent R13, the T type low pass filter that R14 and C19 form, be connected between 105 pin of the DAO pin of frequency multiplication recording playback controller (501) and simplex unit interface (1), trapper (503) is two operational amplifiers (IC3:BC), potentiometer W1, reach the 600-8KHZ band pass filter that peripheral Resistor-Capacitor Unit is barricaded as, the compressing audio signal that draws from 106 pin of simplex unit interface (1) is sent into the Micn pin of frequency multiplication recording playback controller (501) behind trapper (503) elimination 300HZ synchronization noise, frequency division phase shifter (504) is by a reverse driven (IC10:F), a reverse trigger (IC21:A), four NAND gate (IC19), two three NAND gate (IC20:AB) and integrating circuit R33, C30 is barricaded as secondary time-delay frequency dividing circuit, draw the input of clock frequency signal to inverter (IC10:F) from the XOUT pin of frequency multiplication recording playback controller (501), the time-delay sub-frequency clock signal is drawn the outer clock frequency pin (XIN) that draws of delivering to a writing controller (401) and a Read Controller (402) from two or three NAND gate (IC20:AB) respectively.

10, according to the said full duplex conversion equipment of claim 1, it is characterized in that distributor group (6) can be made up of 2-4 static storage, the sheet gating signal control termination logic chip of each memory selects the corresponding control pin of circuit (3), its data/address bus links to each other with the bus of standard playback circuitry (4) with frequency multiplication playback circuitry (5), static storage specifically can be selected HM622564 for use, choose 4 static storages (601-604) for well this moment, the WE pin of all slice, thin pieces (601-604) links to each other with the R/W pin of standard playback circuitry (4) with frequency multiplication playback circuitry (5) when choosing 4 memories, 601,602 OE pin fetches the inversion signal from the 501R/W pin, and 603 and 604 fetch from 401 and the inversion signal of 402R/W pin.

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