CN220586278U - 10-bit parallel synchronous scrambling circuit - Google Patents
10-bit parallel synchronous scrambling circuit Download PDFInfo
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- CN220586278U CN220586278U CN202223497558.4U CN202223497558U CN220586278U CN 220586278 U CN220586278 U CN 220586278U CN 202223497558 U CN202223497558 U CN 202223497558U CN 220586278 U CN220586278 U CN 220586278U
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- 230000005540 biological transmission Effects 0.000 abstract description 9
- 230000003287 optical effect Effects 0.000 abstract description 4
- 239000013307 optical fiber Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000000605 extraction Methods 0.000 description 2
- 230000008929 regeneration Effects 0.000 description 2
- 238000011069 regeneration method Methods 0.000 description 2
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Abstract
The utility model discloses a 10-bit parallel synchronous scrambling circuit, which comprises 10-bit parallel signals without interference and pseudo-random sequence generators, wherein the number of the pseudo-random sequence generators is two, each pseudo-random sequence generator comprises five taps, each tap generates a pseudo-random sequence, and the 10-bit parallel signals without interference are respectively xored with ten pseudo-random sequences with different phases to generate scrambling signals, and compared with the prior art, the utility model has the advantages that: the 10-bit parallel synchronous scrambling circuit occupies little logic resource, has good transmission performance, is used on various optical transmission equipment at present, and has higher popularization and application values.
Description
Technical Field
The utility model relates to the technical field of optical fiber transmission, in particular to a 10-bit parallel synchronous scrambling circuit.
Background
The current high-speed optical fiber transmission equipment is generally realized by adopting an FPGA+SERDES chip+optical module, and the high-speed optical fiber transmission equipment is shown in figure 1. The FPGA mainly completes the functions of adaptation, multiplexing and the like of various service interfaces, the SERDES mainly completes the functions of serial/parallel conversion, parallel/serial conversion, clock extraction, signal code regeneration and the like, and the optical module completes the photoelectric conversion function. The conventional more serdes chips are provided with TLK2201 and the like, the chips are commonly used with 10-bit parallel interfaces, in order to avoid generating longer continuous 0 or continuous 1 signals in serial/parallel converted high-speed serial signals, the serdes receiving part is convenient for clock extraction and signal code regeneration, the parallel signals need to be processed, the conventional chips are commonly used with 8B/10B codes, and the serial 0 and the serial 1 on the serial lines can be reduced to less than 5. But the transmission efficiency of 8B/10B coding is lower, 1/5 of bandwidth is wasted, and on the other hand, the circuit is complex, and more resources are occupied.
Disclosure of Invention
The utility model provides a 10-bit parallel synchronous scrambling circuit for solving various problems.
In order to solve the technical problems, the technical scheme of the utility model is as follows: a10-bit parallel synchronous scrambling circuit comprises undisturbed 10-bit parallel signals and pseudo-random sequence generators, wherein the number of the pseudo-random sequence generators is two, each pseudo-random sequence generator comprises five taps, and ten taps generate ten pseudo-random sequences which are different in phase from the undisturbed 10-bit parallel signals or generate scrambling signals.
Further, the pseudo random sequence generator period is 127 bits.
Further, the set signals of the two pseudo-random sequence generators are the same, the period is 64 clock cycles, namely, 1 set low level signal is generated every 64 clock cycles, and the other 63 clock cycles are all high level signals.
Further, the set initial values of the two pseudo-random sequence generators are different.
Compared with the prior art, the utility model has the advantages that: the 10-bit parallel synchronous scrambling circuit occupies little logic resource, has good transmission performance, is used on various optical transmission equipment at present, and has higher popularization and application values.
Drawings
Fig. 1 is a schematic structural view of a conventional optical fiber transmission apparatus.
Fig. 2 is a schematic circuit diagram of a 10-bit parallel synchronous scrambling circuit according to the present utility model.
As shown in the figure: D0-D9, unscrambled 10-bit parallel signals; D00-D09, and outputting the scrambled signal.
Detailed Description
The present utility model will be described in further detail with reference to the accompanying drawings.
Examples
A10-bit parallel synchronous scrambling circuit comprises an undisturbed 10-bit parallel signal and two pseudo-random sequence generators, wherein each pseudo-random sequence generator comprises five taps, each tap generates a pseudo-random sequence, and the undisturbed 10-bit parallel signal is respectively xored with ten pseudo-random sequences with different phases to generate a scrambling signal
Referring to fig. 2, D0 to D9 are unscrambled 10-bit parallel signals, and D00 to D09 are scrambled signal outputs. D0 to D9 are exclusive-ored with pseudo-random sequences of different phases, respectively, to generate scrambling signals.
The period of the pseudo-random sequence generator is 127 bits, 5 outputs of the pseudo-random sequence generator respectively correspond to 5 taps, and the 5 output pseudo-random sequences are respectively exclusive-ored with 5 paths of input parallel data signals to generate 5 paths of scrambling signals. Two pseudo-random sequence generators scramble 5 paths of data respectively. The set signals of the two pseudo-random sequence generators are the same, the period is 64 clock periods, namely, 1 set low level signal is generated every 64 clock periods, and the other 63 clock periods are all high level signals. In addition, the set initial values of the two pseudo-random sequence generators are different, so that the randomness of the 10-bit output signal can be further ensured.
The utility model and its embodiments have been described above with no limitation, and the actual construction is not limited to the embodiments of the utility model as shown in the drawings. In summary, if one of ordinary skill in the art is informed by this disclosure, a structural manner and an embodiment similar to the technical solution should not be creatively devised without departing from the gist of the present utility model.
Claims (4)
1. A 10-bit parallel synchronous scrambling circuit comprising an undisturbed 10-bit parallel signal and a pseudorandom sequence generator, characterized in that: the number of the pseudo-random sequence generators is two, each pseudo-random sequence generator comprises five taps, and ten taps generate ten pseudo-random sequences which are different in phase and different from the 10-bit parallel signals without interference or generate scrambling signals respectively.
2. A 10-bit parallel synchronous scrambling circuit as recited in claim 1, wherein: the pseudo-random sequence generator period is 127 bits.
3. A 10-bit parallel synchronous scrambling circuit as recited in claim 1, wherein: the set signals of the two pseudo-random sequence generators are the same, the period is 64 clock periods, namely, 1 set low level signal is generated every 64 clock periods, and the other 63 clock periods are all high level signals.
4. A 10-bit parallel synchronous scrambling circuit as recited in claim 1, wherein: the set initial values of the two pseudo-random sequence generators are different.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223497558.4U CN220586278U (en) | 2022-12-27 | 2022-12-27 | 10-bit parallel synchronous scrambling circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223497558.4U CN220586278U (en) | 2022-12-27 | 2022-12-27 | 10-bit parallel synchronous scrambling circuit |
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| Publication Number | Publication Date |
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| CN220586278U true CN220586278U (en) | 2024-03-12 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202223497558.4U Active CN220586278U (en) | 2022-12-27 | 2022-12-27 | 10-bit parallel synchronous scrambling circuit |
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| CN (1) | CN220586278U (en) |
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- 2022-12-27 CN CN202223497558.4U patent/CN220586278U/en active Active
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