CN220382790U - Intelligent charging control circuit and electronic equipment - Google Patents
Intelligent charging control circuit and electronic equipment Download PDFInfo
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- CN220382790U CN220382790U CN202321797507.5U CN202321797507U CN220382790U CN 220382790 U CN220382790 U CN 220382790U CN 202321797507 U CN202321797507 U CN 202321797507U CN 220382790 U CN220382790 U CN 220382790U
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Abstract
The utility model discloses an intelligent charging control circuit and an electronic device, which are used for intelligently distributing charging currents of a host and a battery under the condition that an adapter is not overloaded, wherein the circuit comprises: the sampling unit is used for collecting charging current; the data processing unit is connected with the sampling unit and used for processing the charging current; a charge control unit connectable with the host, the battery, and the adapter; and the main control unit is connected with the data processing unit and the battery charging control unit and is used for controlling the battery charging current through the charging control unit according to the processed charging current. By implementing the utility model, the effect of intelligently distributing the charging currents of the host and the battery can be realized under the condition that the adapter is not overloaded, and the charging efficiency is effectively improved.
Description
Technical Field
The present utility model relates to the field of battery charging technologies, and in particular, to an intelligent charging control circuit and an electronic device.
Background
In the current scheme of simultaneously providing a host (including a mobile phone, a handheld fan, etc.) and a battery, in order not to exceed the nominal output current of the adapter, the charging current of the host and the charging current of the battery are generally set to smaller values, which results in low charging efficiency. While it is also possible to increase the charging efficiency by increasing the nominal current of the adapter, this increases the cost and some customers may specify an adapter that uses a set current, making it difficult to meet both cost and charging efficiency requirements.
Disclosure of Invention
The utility model aims to solve the technical problem of providing an intelligent charging control circuit and electronic equipment.
The technical scheme adopted for solving the technical problems is as follows: an intelligent charge control circuit is configured for intelligently distributing charge current of a host and a battery without overload of an adapter, comprising:
the sampling unit is used for collecting the charging current;
the data processing unit is connected with the sampling unit and is used for processing the charging current;
a charge control unit connectable with the host, the battery, and the adapter; and
and the main control unit is connected with the data processing unit and the battery charging control unit and is used for controlling the battery charging current through the charging control unit according to the processed charging current.
Preferably, the intelligent charging control circuit further comprises a host charging interface, and a first charging interface and a second charging interface which can be accessed to the adapter;
the first end of the first charging interface is connected with the charging control unit, and the charging control unit is connected with the second end of the host charging interface;
the first end and the second end of the second charging interface are sequentially connected with the first end and the third end of the host charging interface in parallel, and the first end of the host charging interface is also connected with the charging control unit;
the third end of the host charging interface is also connected with the data processing unit and the first end of the sampling unit, and the second end of the sampling unit is grounded.
Preferably, the data processing unit includes:
the forward amplification unit is connected with the sampling unit and is used for forward amplifying the charging current to output a first analog signal;
the reverse amplifying unit is connected with the sampling unit and used for reversely amplifying the charging current to output a second analog signal;
the comparison unit is connected with the forward amplification unit, the reverse amplification unit and the main control unit and is used for comparing the magnitudes of the first analog signal and the second analog signal to input a type indication signal which can indicate that the charging current type is a host charging current or a battery charging current to the main control unit; and
the analog switch unit is connected with the forward amplification unit, the reverse amplification unit, the comparison unit and the main control unit and is used for inputting a charging current analog signal which can represent the charging current corresponding to the type to the main control unit according to the type indication signal, the first analog signal and the second analog signal.
Preferably, the forward amplifying unit includes a fourteenth resistor R14, a first operational amplifier U7, a seventeenth resistor R17, a sixteenth resistor R16, and an eighteenth resistor R18;
the first end of the sampling unit is connected to the non-inverting input end of the first operational amplifier U7 through the fourteenth resistor R14, the non-inverting input end of the first operational amplifier U7 is also connected to the ground through the seventeenth resistor R17, the second end of the sampling unit is connected to the inverting input end of the first operational amplifier U7 through the sixteenth resistor R16, two ends of the eighteenth resistor R18 are connected with the inverting input end and the output end of the first operational amplifier U7 in parallel, and the output end of the first operational amplifier U7 outputs the first analog signal.
Preferably, the inverting amplification unit includes a second operational amplifier U9, a nineteenth resistor R19, and a twentieth resistor R20;
the non-inverting input end of the second operational amplifier U9 is connected with the second end of the sampling unit, the first end of the sampling unit is connected to the inverting input end of the second operational amplifier U9 through the nineteenth resistor R19, the two ends of the twentieth resistor R20 are connected with the inverting input end and the output end of the second operational amplifier U9 in parallel, and the output end of the second operational amplifier U9 outputs the second analog signal.
Preferably, the comparing unit comprises a comparator U6, and the analog switching unit comprises an analog switch U8;
the non-inverting input end of the comparator U6 is connected with the first analog signal, the inverting input end of the comparator U6 is connected with the second analog signal, and the output end of the comparator U6 outputs the type indication signal;
the normal open end of the analog switch U8 is connected with the first analog signal, the normal closed end of the analog switch U8 is connected with the second analog signal, the open-close control end of the analog switch U8 is connected with the type indication signal, and the public output end of the analog switch U8 outputs the charging current analog signal.
Preferably, the charge control unit includes:
an anti-reflection unit connected with the first charging interface;
the priority selection unit is connected with the second charging interface and the anti-reflection unit and used for controlling the disconnection of the anti-reflection unit when the first charging interface and the second charging interface are both connected with the adapter; and
and the charging management unit is connected with the anti-reflection unit and the priority selection unit and is used for controlling the charging current of the battery.
Preferably, the anti-reflection unit comprises a first PMOS tube Q1, a third resistor R3, a first switch tube Q3, a second resistor R2 and a second PMOS tube Q2;
the drain electrode of the first PMOS tube Q1 is connected with the first end of the first charging interface, the drain electrode of the first PMOS tube Q1 is further connected to the control end of the first switch tube Q3 and the priority selection unit through the third resistor R3, the grid electrode of the first PMOS tube Q1 is connected with the first end of the first switch tube Q3, the second end of the second resistor R2 and the grid electrode of the second PMOS tube Q2, the second end of the first switch tube Q3 is grounded, the source electrode of the first PMOS tube Q1 is connected with the first end of the second resistor R2 and the source electrode of the second PMOS tube Q2, and the drain electrode of the second PMOS tube Q2 is connected with the power input end of the charging management unit and the second end of the host charging interface.
Preferably, the priority selection unit includes a second switching tube Q4 and a ninth resistor R9;
the first end of the second switching tube Q4 is connected to the control end of the first switching tube Q3, the second end of the second switching tube Q4 is grounded, and the control end of the second switching tube Q4 is connected to the first end of the second charging interface and the drain electrode of the second PMOS tube Q2 through the ninth resistor R9.
The utility model also constructs an electronic device which comprises the intelligent charging control circuit provided by the embodiment of the utility model.
The utility model has the following beneficial effects: providing an intelligent charging control circuit; the charging current is collected through the sampling unit, then the charging current is processed through the data processing unit, and finally the battery charging current is controlled through the main control unit according to the processed charging current to control the work of the charging control unit, so that the effect of intelligently distributing the charging current of the host and the battery under the condition that the adapter is not overloaded is achieved, the safety of a charging loop is guaranteed, and the charging efficiency is effectively improved.
Drawings
The utility model will be further described with reference to the accompanying drawings and examples, in which:
FIG. 1 is a circuit block diagram of a smart charge control circuit in some embodiments of the utility model;
FIG. 2 is a circuit diagram of a smart charge control circuit in accordance with further embodiments of the present utility model;
FIG. 3 is a circuit diagram of a data processing unit in some embodiments of the utility model;
FIG. 4 is a circuit block diagram of a forward amplifying unit in some embodiments of the utility model;
FIG. 5 is a circuit block diagram of an inverting amplification unit in some embodiments of the utility model;
FIG. 6 is a circuit block diagram of a comparison unit in some embodiments of the utility model;
FIG. 7 is a circuit block diagram of an analog switching unit in some embodiments of the utility model;
fig. 8 is a circuit configuration diagram of a charge control unit in some embodiments of the present utility model;
FIG. 9 is a circuit block diagram of an anti-reflection unit and a first charging interface in some embodiments of the utility model;
fig. 10 is a circuit configuration diagram of a charge management unit in some embodiments of the present utility model;
FIG. 11 is a circuit block diagram of a sampling unit, a host charging interface, and a second charging interface in some embodiments of the present utility model;
fig. 12 is a circuit configuration diagram of a master unit in some embodiments of the utility model.
Detailed Description
For a clearer understanding of technical features, objects and effects of the present utility model, a detailed description of embodiments of the present utility model will be made with reference to the accompanying drawings.
Referring to fig. 1, the present utility model provides an intelligent charge control circuit. The circuit is used for intelligently distributing the charging current of the host and the battery under the condition that the adapter is not overloaded. The control circuit includes:
a sampling unit 1 for collecting a charging current;
a data processing unit 2 connected to the sampling unit 1 for processing the charging current;
a charge control unit 3 connectable with the host, the battery, and the adapter; and
and a main control unit 4 connected with the data processing unit 2 and the battery charging control unit 3 for controlling the battery charging current through the charging control unit 3 according to the processed charging current.
It should be noted that the adapter is a power adapter, and is used to provide electric energy for charging the host and the battery.
In this embodiment, the sampling unit 1 collects the charging current, the data processing unit 2 processes the charging current and transmits the processed charging current to the main control unit 4, and the main control unit 4 knows the charging conditions of the host and the battery according to the processed charging current and also controls the charging current of the battery by controlling the charging control unit 3, so that the effect of intelligently distributing the charging current of the host and the battery under the condition that the adapter is not overloaded is achieved, the safety of a charging loop is ensured, and the charging efficiency is effectively improved.
In some embodiments, as shown in fig. 2, 9 and 11, the intelligent charging control circuit further comprises a host charging interface 5 and a battery charging interface 6, and a first charging interface 7 and a second charging interface 8 accessible to the adapter.
The first end of the battery charging interface 6 is connected to the charging control unit 3, and the second end of the battery charging interface 6 is connectable to a battery. The first end of the first charging interface 7 is connected to the charging control unit 3, and the charging control unit 3 is connected to the second end of the host charging interface 5, so that the adapter can be communicated to the charging control unit 3 via the first charging interface 7. The first end and the second end of the second charging interface 8 are sequentially connected with the first end and the third end of the host charging interface 5 in parallel, and the first end of the host charging interface 5 is also connected with the charging control unit 3, so that the adapter can be communicated to the charging control unit 3 through the second charging interface 8 and the host charging interface 5. The third terminal of the host charging interface 5 is also connected to the data processing unit 2 and the first terminal of the sampling unit 1, and the second terminal of the sampling unit 1 is grounded.
In some embodiments, as shown in fig. 3, the data processing unit 2 comprises: a forward amplification unit 21 connected to the sampling unit 1 for forward amplifying the charging current to output a first analog signal; an inverting amplification unit 22 connected to the sampling unit 1 for inverting-amplifying the charging current to output a second analog signal; a comparing unit 23 connected to the forward amplifying unit 21, the reverse amplifying unit 22 and the main control unit 4 for comparing the magnitudes of the first and second analog signals to input a type indicating signal indicating whether the charging current type is a main charging current or a battery charging current to the main control unit 4, the comparing unit 23 being connected; and an analog switching unit 24 connected to the forward amplification unit 21, the reverse amplification unit 22, the comparison unit 23, and the main control unit 4 for inputting a charge current analog signal, which can characterize a charge current magnitude corresponding to a type, to the main control unit 4 according to the type indication signal, the first analog signal, and the second analog signal.
In some embodiments, as shown in fig. 4, the forward amplification unit 21 includes a fourteenth resistor R14, a first operational amplifier U7, a seventeenth resistor R17, a sixteenth resistor R16, and an eighteenth resistor R18. The first end of the sampling unit 1 is connected to the non-inverting input end of the first operational amplifier U7 through a fourteenth resistor R14, the non-inverting input end of the first operational amplifier U7 is also connected to the ground through a seventeenth resistor R17, the second end of the sampling unit 1 is connected to the inverting input end of the first operational amplifier U7 through a sixteenth resistor R16, two ends of the eighteenth resistor R18 are connected in parallel with the inverting input end and the output end of the first operational amplifier U7, and the output end of the first operational amplifier U7 outputs a first analog signal.
It can be understood that the fourteenth resistor R14, the first operational amplifier U7, the seventeenth resistor R17, the sixteenth resistor R16 and the eighteenth resistor R18 form a forward amplifying loop to amplify the voltage difference between the first end and the second end of the sampling unit 1 in the same direction. In addition, the forward amplification factor can be adjusted by adjusting the resistance values of the fourteenth resistor R14, the seventeenth resistor R17, the sixteenth resistor R16, and the eighteenth resistor R18.
Further, in some embodiments, the forward amplifying unit 21 further includes an eleventh capacitor C11, a fifteenth resistor R15, and a fourteenth capacitor C14. The power supply end of the first operational amplifier U7 is connected to a set dc voltage and is connected to ground through an eleventh capacitor C11, the output end of the first operational amplifier U7 is connected to the first end of a fifteenth resistor R15, the second end of the fifteenth resistor R15 outputs a first analog signal, and the second end of the fifteenth resistor R15 is also connected to ground through a fourteenth capacitor C14. The fifteenth resistor R15 and the fourteenth capacitor C14 form a filtering circuit for filtering and limiting the first analog signal.
It should be noted that the set dc voltage may be obtained by converting the input voltage of the adapter through a voltage converting circuit or module commonly used in the prior art.
In some embodiments, as shown in fig. 5, the inverting amplification unit 22 includes a second operational amplifier U9, a nineteenth resistor R19, a twentieth resistor R20, a fifteenth capacitor C15, and a sixteenth capacitor C16. The non-inverting input end of the second operational amplifier U9 is connected with the second end of the sampling unit 1, the first end of the sampling unit 1 is connected to the inverting input end of the second operational amplifier U9 through a nineteenth resistor R19, two ends of the twentieth resistor R20 are connected with the inverting input end and the output end of the second operational amplifier U9 in parallel, the output end of the second operational amplifier U9 outputs a second analog signal, the power supply end of the second operational amplifier U9 is connected with a set direct current voltage and is connected to the ground through a fifteenth capacitor C15, and the output end of the second operational amplifier U9 is also connected to the ground through a sixteenth capacitor C16. Wherein the sixteenth capacitor C16 is used for filtering the second analog signal.
It can be appreciated that the second operational amplifier U9, the nineteenth resistor R19 and the twentieth resistor R20 form an inverting amplifying circuit to reversely amplify the voltage difference between the first terminal and the second terminal of the sampling unit 1. In addition, the reverse amplification factor can be adjusted by adjusting the resistance values of the nineteenth resistor R19 and the twentieth resistor R20.
In some embodiments, as shown in fig. 6, the comparison unit 23 includes a comparator U6, an eleventh capacitance C12, a thirteenth capacitance C13, and a thirteenth resistance R13. The non-inverting input end of the comparator U6 is connected with a first analog signal, the inverting input end of the comparator U6 is connected with a second analog signal, the output end of the comparator U6 outputs a type indication signal, the power supply end of the comparator U6 is connected with a set direct-current voltage and is connected to the ground through an eleventh capacitor C12, a thirteenth capacitor C13 is connected with the eleventh capacitor C12 in parallel, and the output end of the comparator U6 is also connected to the set direct-current voltage through a thirteenth resistor R13. Wherein the thirteenth resistor R13 acts as a pull-up.
In some embodiments, as shown in fig. 7, the analog switch unit 24 includes an analog switch U8. The normally open end of the analog switch U8 is connected with a first analog signal, the normally closed end of the analog switch U8 is connected with a second analog signal, the opening and closing control end of the analog switch U8 is connected with a type indication signal, and the public output end of the analog switch U8 outputs a charging current analog signal.
Alternatively, the chip model of the analog switch unit 24 may be SGM3157YC6.
In some embodiments, as shown in fig. 8, the charge control unit 3 includes: an anti-reflection unit 31 connected to the first charging interface 7; a priority selection unit 32 connected to the second charging interface 8 and the anti-reflection unit 31 for controlling disconnection of the anti-reflection unit 31 when both the first and second charging interfaces 8 are connected to the adapter; and a charge management unit 33 connected to the anti-reflection unit 31 and the priority selection unit 32 for controlling the magnitude of the battery charging current.
In some embodiments, as shown in fig. 9, the anti-reflection unit 31 includes a first PMOS transistor Q1, a first capacitor C1, a third resistor R3, a first switch transistor Q3, a second resistor R2, and a second PMOS transistor Q2. The drain electrode of the first PMOS transistor Q1 is connected to the first end of the first charging interface 7, the drain electrode of the first PMOS transistor Q1 is connected to ground through a first capacitor C1, the drain electrode of the first PMOS transistor Q1 is further connected to the control end of the first switch transistor Q3 and the priority selecting unit 32 through a third resistor R3, the gate electrode of the first PMOS transistor Q1 is connected to the first end of the first switch transistor Q3, the second end of the second resistor R2 and the gate electrode of the second PMOS transistor Q2, the second end of the first switch transistor Q3 is grounded, the source electrode of the first PMOS transistor Q1 is connected to the first end of the second resistor R2 and the source electrode of the second PMOS transistor Q2, and the drain electrode of the second PMOS transistor Q2 is connected to the power input end of the charging management unit 33 and the second end of the host charging interface 5.
In some embodiments, as shown in fig. 9, the priority selection unit 32 includes a second switching transistor Q4, a ninth resistor R9, and a ninth capacitor C9. The first end of the second switching tube Q4 is connected with the control end of the first switching tube Q3, the second end of the second switching tube Q4 is grounded, the control end of the second switching tube Q4 is connected to the first end of the second charging interface 8 and the drain electrode of the second PMOS tube Q2 through a ninth resistor R9, and the second end of the ninth resistor R9 is also connected to the ground through a ninth capacitor C9. Wherein the ninth capacitor C9 acts as a filter.
Optionally, the first switching tube Q3 and the second switching tube Q4 are NPN transistors, the first ends of the first and second switching tubes correspond to collectors of the NPN transistors, the second ends of the first and second switching tubes correspond to emitters of the NPN transistors, and the control ends of the first and second switching tubes correspond to bases of the NPN transistors. Alternatively, the first switching tube Q3 and the second switching tube Q4 may be NMOS tubes.
In some embodiments, as shown in fig. 10, the charging management unit 33 includes a charging management chip U3 with a chip type of ETA6963, and peripheral electronic components (including a fourth resistor R4, a first inductor L1, etc.) associated with the charging management chip U3, which are specifically referred to in fig. 10 and will not be described herein. In addition, pins 1 and 24 of the charge management chip U3 correspond to power supply inputs of the charge management unit 33; pins 13 and 14 of the charging management chip U3 are used as battery charging current output ends and are connected with the battery charging interface 6; the 11 th pin of the charging management chip U3 is used as a temperature acquisition end to be connected with the battery charging interface 6, and the resistance state of the thermistor in the battery can be detected through the end.
Because some hosts have multiple interface-type charging interfaces, and the power terminals of these charging interfaces are connected in parallel, using this feature, in some embodiments, as shown in fig. 11, the host charging interface 5 includes a second connector CON2 and a first connector CON1 (corresponding to a certain charging interface on the host) disposed on the host. The first connector CON1 includes two branch ports (not shown), one of which can be connected to the host, and the other of which is connected to the second charging interface 8, and then the first connector CON1 and the second connector CON2 can be connected by a connection line. It will be appreciated that, referring to fig. 9 to 11, when the adapter is charging the host, if the adapter outputs a residual current, the first connector CON1 and the second connector CON2 may be connected by the connection line, so that the adapter may supply power to the charging management unit 33 via the first connector CON1 and the second connector CON2, so that the charging management unit 33 may fully utilize the residual current of the adapter to charge the battery, thereby improving the charging efficiency.
In some embodiments, as shown in fig. 11, the sampling unit 1 includes a first resistor R1. The first end and the second end of the first resistor R1 are sequentially corresponding to the first end and the second end of the sampling unit 1.
In some embodiments, as shown in fig. 12, the main control unit 4 includes a processor U5, and specific connection structures of the processor U5 and other units may refer to fig. 7, 10 and 12, which are not described herein.
Referring to fig. 1 to 12, the intelligent charge control circuit operates as follows:
A. when only the first charging interface 7 is connected to the adapter, under the pull-up action of the third resistor R3, the first switching tube Q3 is conducted, so that the first PMOS tube Q1 and the second PMOS tube Q2 are conducted, and the positive end output current of the adapter is input to the host through the second end of the host charging interface 5, flows back to the negative end of the adapter (in this case, the negative end of the adapter is grounded GND) through the charging grounding end of the host and the first resistor R1, and the other path is input to the positive end of the battery through the charging management chip U3 and the battery charging interface 6 and flows back to the negative end of the adapter through the negative end of the battery; therefore, the first end voltage v_ichg_host of the first resistor R1 is greater than the second end voltage GND thereof, and the first analog signal i_ad1 is greater than the second analog signal i_ad2 under the forward amplification of the forward amplifying unit 21 and the reverse amplification of the reverse amplifying unit 22, so that the type indication signal i_logic output from the output end of the comparator U6 is at a high level and indicates that the HOST charging current is collected by the collecting unit 1, so that the normal end of the analog switch U8 is closed with the common output end, i.e., the charging current analog signal i_ad corresponds to the first analog signal i_ad1; after the processor U5 acquires the type indication signal I_LOGIC and the charging current analog signal I_AD, the current host charging current is obtained according to the charging current analog signal I_AD, and then a related instruction is sent to the charging management chip U3, so that the battery charging current output by the charging management chip U3 is controlled;
B. when only the second charging interface 8 is connected to the adapter, one path of current output by the positive end of the adapter is input to the host through the first end vin_pogo of the host charging interface 5, the priority selection unit 32 and the second end of the host charging interface 5, and flows back to the negative end of the adapter from the charging ground end of the host (in this case, the negative end of the adapter is connected to the charging ground end vin_dc_gnd of the host), and the other path of current is input to the positive end of the battery through the first end vin_pogo of the host charging interface 5, the priority selection unit 32, the electric management chip U3 and the battery charging interface 6, and flows back to the negative end of the adapter through the positive end of the battery, the ground GND and the first resistor R1; therefore, the first end voltage v_ichg_host of the first resistor R1 is smaller than the second end voltage GND thereof, the first analog signal i_ad1 is smaller than the second analog signal i_ad2 under the forward amplification of the forward amplifying unit 21 and the reverse amplification of the reverse amplifying unit 22, and therefore the type indication signal i_logic output from the output end of the comparator U6 is at a low level and indicates that the battery charging current is collected by the collecting unit 1, so that the normally-closed end of the analog switch U8 is closed with the common output end, that is, the charging current analog signal i_ad corresponds to the second analog signal i_ad2; after the processor U5 obtains the type indication signal I_LOGIC and the charging current analog signal I_AD, the current battery charging current is known according to the charging current analog signal I_AD, and the battery charging current is limited to be smaller than the difference value of the nominal output current of the adapter minus the nominal charging current of the host by sending a related instruction to the charging management chip U3;
C. when the first charging interface 7 and the second charging interface 8 are connected to the adapter at the same time, the first end vin_pogo of the host charging interface 5 is at a high level, and under the pull-up action of the ninth resistor R9, the second switching tube Q4 is turned on, so that the first switching tube Q3 is kept turned off due to the control end thereof being locked at a low level, and the second PMOS tube Q2 is kept turned off, that is, the adapter connected to the first charging interface 7 cannot form a path with the charging control unit 3, that is, in this case, the adapter connected to the second charging interface 8 provides charging electric energy for the host and the battery.
It should be noted that the processor U5 may learn the nominal charging currents of the host and the battery, and the nominal current of the adapter through a pre-stored or communication (such as a serial port, etc.).
The utility model also provides electronic equipment comprising the intelligent charging control circuit provided by the embodiment of the utility model.
It is to be understood that the above examples only represent preferred embodiments of the present utility model, which are described in more detail and are not to be construed as limiting the scope of the utility model; it should be noted that, for a person skilled in the art, the above technical features can be freely combined, and several variations and modifications can be made without departing from the scope of the utility model; therefore, all changes and modifications that come within the meaning and range of equivalency of the claims are to be embraced within their scope.
Claims (10)
1. An intelligent charge control circuit for intelligently distributing charge current of a host and a battery without overload of an adapter, comprising:
a sampling unit (1) for acquiring the charging current;
a data processing unit (2) connected to the sampling unit (1) for processing the charging current;
a charge control unit (3) connectable with the host, battery and adapter; and
and the main control unit (4) is connected with the data processing unit (2) and the battery charging control unit (3) and is used for controlling the battery charging current through the charging control unit (3) according to the processed charging current.
2. The intelligent charging control circuit according to claim 1, further comprising a host charging interface (5), and a first charging interface (7) and a second charging interface (8) accessible to the adapter;
the first end of the first charging interface (7) is connected with the charging control unit (3), and the charging control unit (3) is connected with the second end of the host charging interface (5);
the first end and the second end of the second charging interface (8) are sequentially connected with the first end and the third end of the host charging interface (5) in parallel, and the first end of the host charging interface (5) is also connected with the charging control unit (3);
the third end of the host charging interface (5) is also connected with the data processing unit (2) and the first end of the sampling unit (1), and the second end of the sampling unit (1) is grounded.
3. Intelligent charge control circuit according to claim 2, characterized in that the data processing unit (2) comprises:
a forward amplification unit (21) connected to the sampling unit (1) for forward amplifying the charging current to output a first analog signal;
an inverting amplification unit (22) connected to the sampling unit (1) for inverting the charging current to output a second analog signal;
a comparing unit (23) connected with the forward amplifying unit (21), the reverse amplifying unit (22) and the main control unit (4) and used for comparing the magnitudes of the first analog signal and the second analog signal so as to input a type indicating signal capable of indicating the type of charging current as a host charging current or a battery charging current to the main control unit (4), wherein the comparing unit (23) is connected; and
and the analog switch unit (24) is connected with the forward amplification unit (21), the reverse amplification unit (22), the comparison unit (23) and the main control unit (4) and is used for inputting a charging current analog signal which can represent the charging current magnitude corresponding to the type to the main control unit (4) according to the type indication signal, the first analog signal and the second analog signal.
4. The intelligent charge control circuit according to claim 3, wherein the forward amplification unit (21) includes a fourteenth resistor R14, a first operational amplifier U7, a seventeenth resistor R17, a sixteenth resistor R16, and an eighteenth resistor R18;
the first end of the sampling unit (1) is connected to the non-inverting input end of the first operational amplifier U7 through the fourteenth resistor R14, the non-inverting input end of the first operational amplifier U7 is also connected to the ground through the seventeenth resistor R17, the second end of the sampling unit (1) is connected to the inverting input end of the first operational amplifier U7 through the sixteenth resistor R16, two ends of the eighteenth resistor R18 are connected with the inverting input end and the output end of the first operational amplifier U7 in parallel, and the output end of the first operational amplifier U7 outputs the first analog signal.
5. A smart charge control circuit according to claim 3, wherein the inverting amplification unit (22) comprises a second operational amplifier U9, a nineteenth resistor R19 and a twentieth resistor R20;
the non-inverting input end of the second operational amplifier U9 is connected with the second end of the sampling unit (1), the first end of the sampling unit (1) is connected to the inverting input end of the second operational amplifier U9 through the nineteenth resistor R19, the two ends of the twentieth resistor R20 are connected with the inverting input end and the output end of the second operational amplifier U9 in parallel, and the output end of the second operational amplifier U9 outputs the second analog signal.
6. An intelligent charge control circuit according to claim 3, characterized in that the comparison unit (23) comprises a comparator U6, and the analog switch unit (24) comprises an analog switch U8;
the non-inverting input end of the comparator U6 is connected with the first analog signal, the inverting input end of the comparator U6 is connected with the second analog signal, and the output end of the comparator U6 outputs the type indication signal;
the normal open end of the analog switch U8 is connected with the first analog signal, the normal closed end of the analog switch U8 is connected with the second analog signal, the open-close control end of the analog switch U8 is connected with the type indication signal, and the public output end of the analog switch U8 outputs the charging current analog signal.
7. The intelligent charge control circuit according to any one of claims 2 to 6, characterized in that the charge control unit (3) comprises:
an anti-reflection unit (31) connected with the first charging interface (7);
a priority selection unit (32) connected to the second charging interface (8) and the anti-reflection unit (31) for controlling disconnection of the anti-reflection unit (31) when both the first and second charging interfaces (8) are connected to an adapter; and
and a charge management unit (33) connected with the anti-reflection unit (31) and the priority selection unit (32) and used for controlling the magnitude of the battery charging current.
8. The intelligent charge control circuit according to claim 7, wherein the anti-reflection unit (31) comprises a first PMOS transistor Q1, a third resistor R3, a first switch transistor Q3, a second resistor R2, and a second PMOS transistor Q2;
the drain electrode of the first PMOS tube Q1 is connected with the first end of the first charging interface (7), the drain electrode of the first PMOS tube Q1 is further connected to the control end of the first switch tube Q3 and the priority selection unit (32) through the third resistor R3, the grid electrode of the first PMOS tube Q1 is connected with the first end of the first switch tube Q3, the second end of the second resistor R2 and the grid electrode of the second PMOS tube Q2, the second end of the first switch tube Q3 is grounded, the source electrode of the first PMOS tube Q1 is connected with the first end of the second resistor R2 and the source electrode of the second PMOS tube Q2, and the drain electrode of the second PMOS tube Q2 is connected with the power input end of the charging management unit (33) and the second end of the host charging interface (5).
9. The intelligent charge control circuit according to claim 8, wherein the priority selection unit (32) includes a second switching tube Q4 and a ninth resistor R9;
the first end of the second switching tube Q4 is connected with the control end of the first switching tube Q3, the second end of the second switching tube Q4 is grounded, and the control end of the second switching tube Q4 is connected to the first end of the second charging interface (8) and the drain electrode of the second PMOS tube Q2 through the ninth resistor R9.
10. An electronic device comprising an intelligent charge control circuit as claimed in any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321797507.5U CN220382790U (en) | 2023-07-07 | 2023-07-07 | Intelligent charging control circuit and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321797507.5U CN220382790U (en) | 2023-07-07 | 2023-07-07 | Intelligent charging control circuit and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220382790U true CN220382790U (en) | 2024-01-23 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321797507.5U Active CN220382790U (en) | 2023-07-07 | 2023-07-07 | Intelligent charging control circuit and electronic equipment |
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| Country | Link |
|---|---|
| CN (1) | CN220382790U (en) |
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2023
- 2023-07-07 CN CN202321797507.5U patent/CN220382790U/en active Active
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