CN220064295U - Test circuit and circuit board - Google Patents

Abstract

The utility model discloses a test circuit and a circuit board, wherein the test circuit at least comprises a first voltage current source, a second voltage current source, a differential measurement circuit, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit, a sixth switch unit, a seventh switch unit and an eighth switch unit; the differential measurement circuit can improve the current output of the test circuit under the condition that a voltage current source is not additionally arranged, and can realize differential measurement of any two pins in the tested chip only by one differential measurement circuit, can meet the test requirements of different chips, and has the advantages of low cost, wide application range and simple and easy operation.

Description

Test circuit and circuit board

Technical Field

The present utility model relates to the field of testing technologies for integrated circuits, and in particular, to a testing circuit and a circuit board.

Background

In integrated circuit testing, the current capability of a single channel is generally improved in response to the demand for greater current capability of a chip under test. But is limited by the area of the board card, the driving capability of a single power amplifier, heat dissipation and other problems, the current driving capability of a single channel is required to be greatly improved, and the difficulty is high. And the single-channel current capacity is improved by sacrificing the number of single-board channels, so that under the same test requirement, a user needs to configure more boards to realize the test purpose, and the test cost of the user is increased.

In addition, in the prior art, when differential measurement is performed on multiple pairs of pins of a tested chip, multiple pairs of differential measurement modules are generally required to perform differential measurement, so that the test cost of the tested chip is increased.

Disclosure of Invention

The utility model provides a test circuit and a circuit board, which are used for improving the output capability of test current and reducing the cost.

According to an aspect of the present utility model, there is provided a test circuit including at least: the switching device comprises a first voltage current source, a second voltage current source, a differential measurement circuit, a first switching unit, a second switching unit, a third switching unit, a fourth switching unit, a fifth switching unit, a sixth switching unit, a seventh switching unit and an eighth switching unit;

the first switch unit and the second switch unit are connected in series to a first node, and the power end of the first voltage current source is electrically connected to a first test pin of the chip to be tested through the first switch unit and the second switch unit which are sequentially connected in series;

the third switch unit and the fourth switch unit are connected in series to the second node, and the power end of the second voltage current source is electrically connected to a second test pin of the tested chip through the third switch unit and the fourth switch unit which are sequentially connected in series;

The first end of the fifth switch unit is electrically connected with the first node; the first end of the sixth switch unit is electrically connected with the second node; the second end of the fifth switch unit is electrically connected with the second end of the sixth switch unit;

the first end of the seventh switch unit is electrically connected with the first node, and the first end of the eighth switch unit is electrically connected with the second node; the second end of the seventh switching unit and the second end of the eighth switching unit are electrically connected with the high-end input end of the differential measurement circuit; the third end of the seventh switching unit and the third end of the eighth switching unit are electrically connected with the low-end input end of the differential measurement circuit.

Optionally, the first switch unit includes a first driving switch; the second switch unit comprises a second driving switch; the third switch unit comprises a third driving switch; the fourth switch unit comprises a fourth driving switch; the fifth switching unit includes a fifth driving switch; the sixth switch unit comprises a sixth driving switch;

the first node comprises a first sub-node, and the first driving switch and the second driving switch are connected in series to the first sub-node; the power end of the first voltage current source is electrically connected to a first test pin of the chip to be tested through a first drive switch and a second drive switch which are sequentially connected in series;

The second node comprises a second sub-node, and the third driving switch and the fourth driving switch are connected in series with the second sub-node; the power end of the second voltage current source is electrically connected to a second test pin of the tested chip through a third driving switch and a fourth driving switch which are sequentially connected in series;

the first end of the fifth driving switch is electrically connected with the first sub-node; the first end of the sixth driving switch is electrically connected with the second sub-node; the second end of the fifth driving switch is electrically connected with the second end of the sixth driving switch.

Optionally, the first switch unit further comprises a first test switch; the second switch unit further comprises a second test switch; the third switch unit further comprises a third test switch; the fourth switch unit further comprises a fourth test switch;

the first test switch and the second test switch are connected in series with the test end of the first voltage current source and the first test pin of the tested chip; the third test switch and the fourth test switch are connected in series with the test end of the second voltage current source and the second test pin of the tested chip.

Optionally, the seventh switching unit includes a first sub-switch and a second sub-switch; the first ends of the first sub switch and the second sub switch are electrically connected with a first node; the second end of the first sub-switch is electrically connected with the high-end input end of the differential measurement circuit, and the second end of the second sub-switch is electrically connected with the low-end input end of the differential measurement circuit;

The eighth switch unit comprises a third sub switch and a fourth sub switch; the first ends of the third sub-switch and the fourth sub-switch are electrically connected with the second node; the second end of the third sub-switch is electrically connected with the high-end input end of the differential measurement circuit, and the second end of the fourth sub-switch is electrically connected with the low-end input end of the differential measurement circuit.

Optionally, the differential measurement circuit includes: the device comprises a control unit, a differential measurement unit and an analog-to-digital conversion unit;

the high-end input end of the differential measurement unit is electrically connected with the second end of the seventh switch unit and the second end of the eighth switch unit;

the low-end input end of the differential measurement unit is electrically connected with the third end of the seventh switching unit and the third end of the eighth switching unit;

the analog signal input end of the analog-to-digital conversion unit is electrically connected with the output end of the differential measurement unit, and the digital signal output end of the analog-to-digital conversion unit is electrically connected with the input end of the control unit.

Optionally, the test circuit further comprises: a calibration module;

the second ends of the fifth switch unit and the sixth switch unit are also electrically connected with the input end of the calibration module.

Optionally, the fifth switch unit further includes a fifth test switch, and the sixth switch unit further includes a sixth test switch; the first node further comprises a fourth sub-node, and the second node further comprises a fifth sub-node; the first test switch and the second test switch are electrically connected to the fourth sub-node, and the third test switch and the fourth test switch are electrically connected to the fifth sub-node;

The first end of the fifth test switch is electrically connected with the fourth sub-node, the first end of the sixth test switch is electrically connected with the fifth sub-node, and the second end of the fifth test switch and the second end of the sixth test switch are electrically connected with the first input end of the calibration module;

the second end of the fifth driving switch and the second end of the sixth driving switch are also electrically connected with the second input end of the calibration module.

Optionally, the test circuit further comprises: a time measurement module and a first switch;

one end of the time measurement module is electrically connected with a first end of the first switch, and a second end of the first switch is electrically connected with any one of the first node and the second node.

According to a second aspect of the present utility model, there is provided a circuit board comprising the test circuit of any one of the implementations of the first aspect.

The test circuit provided by the embodiment of the utility model is provided with a plurality of voltage current sources corresponding to the requirements of a plurality of test pins of a chip to be tested, two test switches connected in series are arranged between each voltage current source and the corresponding test pin, when the two test switches connected in series are controlled to be in a conducting state, the voltage current sources can output test power supply signals to the corresponding test pins, in addition, a test switch for realizing parallel output is also arranged corresponding to each voltage current source, when the current required by a certain test pin of the chip to be tested is larger, the parallel connection of the two or more voltage current sources can be realized by controlling the on-off state of each test switch, and the current output of the test circuit can be improved under the condition that the voltage current sources are not additionally arranged; the differential measurement circuit is further arranged, any two pins of the tested chip are connected into two input ends of the differential measurement circuit by controlling the on-off state of each switch unit in the test circuit, so that the voltage difference measurement of the two pins is realized, the test requirements of different chips can be met, the cost is low, the application range is wide, the circuit is simple and easy to operate, and the circuit is suitable for wide use.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the utility model or to delineate the scope of the utility model. Other features of the present utility model will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a test circuit according to an embodiment of the present utility model;

FIG. 2 is a schematic diagram of another test circuit according to an embodiment of the present utility model;

FIG. 3 is a schematic diagram of a test circuit according to another embodiment of the present utility model;

fig. 4 is a schematic diagram of a structure of a test circuit according to another embodiment of the present utility model.

Detailed Description

In order that those skilled in the art will better understand the present utility model, a technical solution in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present utility model, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present utility model without making any inventive effort, shall fall within the scope of the present utility model.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present utility model and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the utility model described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Fig. 1 is a schematic structural diagram of a test circuit according to an embodiment of the present utility model, as shown in fig. 1, the test circuit at least includes: a first voltage current source 10, a second voltage current source 20, a first switching unit Q1, a second switching unit Q2, a third switching unit Q3, a fourth switching unit Q4, a fifth switching unit Q5, a sixth switching unit Q6, a seventh switching unit Q7, and an eighth switching unit Q8; the first switch unit Q1 and the second switch unit Q2 are connected in series to the first node a, and the power end of the first voltage current source 10 is electrically connected to the first test Pin Pin1 of the tested chip U1 through the first switch unit Q1 and the second switch unit Q2 which are sequentially connected in series; the third switch unit Q3 and the fourth switch unit Q4 are connected in series to the second node b, and the power end of the second voltage current source 20 is electrically connected to the second test Pin2 of the tested chip U1 through the third switch unit Q3 and the fourth switch unit Q4 which are sequentially connected in series; a first end of the fifth switching unit Q5 is electrically connected to the first node a; the first end of the sixth switch unit Q6 is electrically connected with the second node b; a second terminal of the fifth switching unit Q5 is electrically connected to a second terminal of the sixth switching unit Q6.

In particular, the test circuit may include a plurality of voltage current sources, and the embodiment of the present utility model is only exemplified by the test circuit including two voltage current sources (the first voltage current source 10 and the second voltage current source 20), but is not limited thereto. And each voltage current source may be a voltage current source in the same board card or a voltage current source in a different board card, which is not particularly limited in the embodiment of the present utility model. Each voltage current source is used for outputting a power supply signal to a test pin of the tested chip U1. Each test Pin of the tested chip U1 (the present embodiment only exemplarily shows that the tested chip U1 includes the first test Pin1 and the second test Pin2, but is not limited thereto) is electrically connected to one voltage current source, that is, the first voltage current source 10 may be electrically connected to the first test Pin1 of the tested chip U1, and the second voltage current source 20 may be electrically connected to the second test Pin2 of the tested chip U1. Two switching units may be disposed between each voltage current source and the corresponding test Pin electrically connected in series, for example, a first switching unit Q1 and a second switching unit Q2 may be disposed sequentially and serially connected between the first voltage current source 10 and the first test Pin1 of the chip U1 to be tested, and a third switching unit Q3 and a fourth switching unit Q4 may be disposed sequentially and serially connected between the second voltage current source 20 and the second test Pin2 of the chip U1 to be tested. When a test power signal is required to be provided for a certain test pin, two test switches between the test pin and the voltage current source can be controlled to be in a conducting state, so that the voltage current source can transmit the power signal to the test pin corresponding to the tested chip U1 through the two conducting switch units.

Let the connection node of the first switching unit Q1 and the second switching unit Q2 be the first node a, and the connection node of the third switching unit Q3 and the fourth switching unit Q4 be the second node b. A first end of the fifth switching unit Q5 is electrically connected to the first node a, a first end of the sixth switching unit Q6 is electrically connected to the second node b, and a second end of the fifth switching unit Q5 is commonly connected to a second end of the sixth switching unit Q6. Therefore, when the current required by a certain test pin of the tested chip U1 is larger, at least two voltage current sources can be connected in parallel to the test pin by controlling the on-off state of each switch unit to output a power signal, so that the driving capability of the test circuit is improved. For example, when the current required by the first test Pin1 of the tested chip U1 exceeds the current capability of the first voltage current source 10, the first switch unit Q1, the second switch unit Q2, the third switch unit Q3, the fifth switch unit Q5 and the sixth switch unit Q6 may be controlled to be in the on state, and other test switches may be controlled to be in the off state, which is equivalent to connecting the first voltage current source 10 and the second voltage current source 20 in parallel and then electrically connecting the first test Pin1 of the tested chip U1, i.e. the current received by the first test Pin1 is the sum of the output current of the first voltage current source 10 and the output current of the second voltage current source 20, and the first switch unit Q2, the third switch unit Q3, the fifth switch unit Q5 and the sixth switch unit Q6 may not be replaced by a voltage current source with a larger current output capability. Before the first voltage current source 10 and the second voltage current source 20 are connected in parallel, the first voltage current source 10 and the second voltage current source 20 may be set in a constant current mode, and then the corresponding switch units are controlled to be turned on to realize the parallel connection of the two current sources.

It will be appreciated that when the test circuit includes a plurality of (more than two) voltage current sources, various parallel connection between the current sources may be implemented, taking the test circuit including three voltage current sources as an example, fig. 2 is a schematic structural diagram of another test circuit provided in an embodiment of the present utility model, and as shown in fig. 2, the test circuit may further include a third voltage current source 30, a ninth switching unit Q9, a tenth switching unit Q10, and an eleventh switching unit Q11, where the ninth switching unit Q9 and the tenth switching unit Q10 are serially connected to the third node c, and the ninth switching unit Q9 and the tenth switching unit Q10 are serially connected in sequence between the third voltage current source 30 and the third test Pin3 of the tested chip U1, and a first end of the eleventh switching unit Q11 is electrically connected to the third node c, and a second end of the eleventh switching unit Q11 is electrically connected to a second end of the fifth switching unit Q5 and a second end of the sixth switching unit Q6.

For example, based on the same principle, when the current required by the first test Pin1 of the tested chip U1 exceeds the current capability of the first voltage current source 10, the first voltage current source 10 may be connected in parallel with the third voltage current source 30, where the first switching unit Q1, the second switching unit Q2, the ninth switching unit Q9, the fifth switching unit Q5 and the eleventh switching unit Q11 are all turned on, and the other switches are all turned off. Alternatively, the first voltage current source 10, the second voltage current source 20 and the third voltage current source 30 may be connected in parallel, and at this time, the first switch unit Q1, the second switch unit Q2, the third switch unit Q3, the ninth switch unit Q9, the fifth switch unit Q5, the sixth switch unit Q6 and the eleventh switch unit Q11 are all turned on, and the other switches are all turned off. The number of the parallel voltage current sources can be set according to the required current of the first test Pin1 of the tested chip U1. And when the required current of the second test Pin2 or the third test Pin3 is larger, the on-off state of each test switch can be controlled according to the requirement to realize the parallel connection of each voltage current source, so that the test requirement of the tested chip U1 can be met under the condition that the voltage current source with larger current output capability is not required to be replaced.

The voltage current sources may be disposed on a circuit board, a ground end of the circuit board may be electrically connected to the ground end GND1 of the tested chip U1 through the second switch K2, and the ground end GND1 of the tested chip U1 may be grounded through the third switch K3. In this way, the ground terminal of the test circuit and the ground terminal GND1 of the tested chip U1 can be kept the same, for example, both are floating ground terminals, or both are actual ground terminals, and the test circuit follows the ground terminal of the tested chip U1 and keeps consistent with the tested chip.

Referring to fig. 1, the test circuit may further include a differential measurement circuit 40, a seventh switching unit Q7, and an eighth switching unit Q8, a first end of the seventh switching unit Q7 being electrically connected to the first node a, and a first end of the eighth switching unit Q8 being electrically connected to the second node b; the second terminal of the seventh switching unit Q7 and the second terminal of the eighth switching unit Q8 are electrically connected to the high-side input terminal INH of the differential measurement circuit 40; the third terminal of the seventh switching unit Q7 and the third terminal of the eighth switching unit Q8 are electrically connected to the low-side input terminal INL of the differential measurement circuit 40.

Specifically, the differential measurement circuit 40 and the switch units corresponding to the test pins in the tested chip U1 one by one may be further provided, where the differential measurement circuit 40 and the switch units (the seventh switch unit Q7 and the eighth switch unit Q8) are connected by adopting the above electrical connection manner, by controlling the on-off state of each switch unit in the test circuit, two test pins of the tested chip U1 may be connected to the high-end input terminal INH and the low-end input terminal INL of the differential measurement circuit 40 respectively (any pin of the tested chip U1 may be connected to the high-end or the low-end of the differential measurement circuit according to the actual measurement requirement), so that measurement of the voltage difference between two test pins of the tested chip U1 may be achieved through the differential measurement function of the differential measurement circuit 40, and the test flexibility is good.

For example, when the first end and the second end of the seventh switching unit Q7 are controlled to be turned on, the first end and the third end of the eighth switching unit Q8 are controlled to be turned on, and the second switching unit Q2 and the fourth switching unit Q4 are controlled to be turned on, and the other switching units are all turned off, the first test Pin1 of the tested chip U1 is connected to the high-end input terminal INH of the differential measurement circuit 40 through the second switching unit Q2 and the seventh switching unit Q7 connected in series, and the second test Pin2 of the tested chip U1 is connected to the low-end input terminal INL of the differential measurement circuit 40 through the fourth switching unit Q4 and the eighth switching unit Q8 connected in series.

Referring to fig. 2, based on the same principle, when the test circuit includes the third voltage current source 30, the test circuit may further include a twelfth switching unit Q12, where a first terminal of the twelfth switching unit Q12 is electrically connected to the third node c, a second terminal of the twelfth switching unit Q is electrically connected to the high-side input terminal INH of the differential measurement circuit 40, and a third terminal of the twelfth switching unit Q is electrically connected to the low-side input terminal INL of the differential measurement circuit 40. At this time, any two test pins in the tested chip U1 can be controlled to be connected into the differential measurement circuit for differential measurement by controlling the on-off of each switch unit in the test circuit.

According to the test circuit provided by the embodiment of the utility model, a plurality of voltage current sources are arranged corresponding to the requirements of a plurality of test pins of a chip to be tested, two switch units connected in series are arranged between each voltage current source and the corresponding test pin, when the two switch units connected in series are controlled to be in a conducting state, the voltage current sources can output power signals to the corresponding test pins, in addition, the switch units for realizing parallel output are also arranged corresponding to each voltage current source, when the current required by one test pin of the chip to be tested is larger, the parallel connection of two or more voltage current sources can be realized by controlling the on-off state of each switch unit, the current output of the test circuit can be improved under the condition that the voltage current sources with larger current output capacity are not needed, and the differential measurement circuit is also arranged, so that any two pins of the chip to be tested can be connected to two input ends of the differential measurement circuit by controlling the on-off state of each switch unit in the test circuit, the test requirements of different chips can be met, the cost is low, the application range is wide, and the circuit is simple and easy to operate and is suitable for wide use.

Alternatively, referring to fig. 1, the first switching unit Q1 includes a first driving switch B1; the second switching unit Q2 includes a second driving switch B2; the third switching unit Q3 includes a third driving switch B3; the fourth switching unit Q4 includes a fourth driving switch B4; the fifth switching unit Q5 includes a fifth driving switch B5; the sixth switching unit Q6 includes a sixth driving switch B6; the first node a comprises a first sub-node a1, and the first driving switch B1 and the second driving switch B2 are connected in series to the first sub-node a1; the power end of the first voltage current source 10 is electrically connected to a first test Pin Pin1 of the tested chip U1 through a first drive switch B1 and a second drive switch B2 which are sequentially connected in series; the second node B comprises a second sub-node B1, and the third driving switch B3 and the fourth driving switch B4 are connected in series with the second sub-node B1; the power end of the second voltage current source 20 is electrically connected to a second test Pin2 of the tested chip U1 through a third driving switch B3 and a fourth driving switch B4 which are sequentially connected in series; a first end of the fifth driving switch B5 is electrically connected to the first sub-node a1; the first end of the sixth driving switch B6 is electrically connected with the second sub-node B1; a second terminal of the fifth driving switch B5 is electrically connected to a second terminal of the sixth driving switch B6.

Specifically, when the first driving switch B1 and the second driving switch B2 are turned on, the first voltage current source 10 outputs a power signal to the first test Pin1 of the tested chip U1, and when the third driving switch B3 and the fourth driving switch B4 are turned on, the second voltage current source 20 outputs a power signal to the second test Pin2 of the tested chip U1. When the first driving switch B1, the second driving switch B2, the third driving switch B3, the fifth driving switch B5 and the sixth driving switch B6 are turned on, the first voltage current source 10 and the second voltage current source 20 are connected in parallel and output a power signal to the first test Pin1 of the tested chip U1. When the first driving switch B1, the third driving switch B3, the fourth driving switch B4, the fifth driving switch B5 and the sixth driving switch B6 are turned on, the first voltage current source 10 and the second voltage current source 20 are connected in parallel and output a power signal to the second test Pin2 of the tested chip U1.

Referring to fig. 2, the ninth switching unit Q9 includes a ninth driving switch B9, the tenth switching unit includes a tenth driving switch B10, and the eleventh switching unit Q11 includes an eleventh driving switch B11. The third node c includes a third sub-node c1, the ninth driving switch B9 and the tenth driving switch B10 are connected in series to the third sub-node c1, and the ninth driving switch B9 and the tenth driving switch B10 are sequentially connected in series between the power supply terminal of the third voltage current source 30 and the third test Pin3 of the chip under test U1. The first end of the eleventh driving switch B11 is electrically connected to the third sub-node c1, and the second end of the eleventh driving switch B11 is electrically connected to the second end of the fifth driving switch B5 and the second end of the sixth driving switch B6. The on-off state and the effect of each driving switch can be described above, and will not be described herein. One end of the second driving switch B2, the fourth driving switch B4, and the tenth driving switch B10 connected to the tested chip U1 may be a driving signal line high end FH of the kelvin test channel, and one end of the third switch K3 connected to the tested chip U1 may be a driving signal line low end FL of the kelvin test channel.

Optionally, fig. 3 is a schematic structural diagram of another test circuit according to an embodiment of the present utility model, as shown in fig. 3, the first switch unit Q1 further includes a first test switch A1; the second switching unit Q2 further includes a second test switch A2; the third switching unit Q3 further includes a third test switch A3; the fourth switching unit Q4 further includes a fourth test switch A4; the first test switch A1 and the second test switch A2 are connected in series between the test end of the first voltage current source 10 and the first test Pin Pin1 of the tested chip U1; the third test switch A3 and the fourth test switch A4 are connected in series between the test terminal of the second voltage current source 20 and the second test Pin2 of the tested chip U1. Likewise, the ninth switching unit Q9 may include a ninth test switch A9, and the tenth switching unit Q10 may include a tenth test switch a10, and the ninth test switch A9 and the tenth test switch a10 may be connected in series between the test terminal of the third voltage current source 30 and the third test Pin3 of the chip under test U1.

Specifically, the test circuit may further include a test channel formed by a test switch connected in series between the test terminal of the voltage current source and the test pin of the chip under test, so that each voltage current source can directly detect the electrical signal of each test pin through the test terminal, without setting a test device in addition. The driving switch and the testing switch in the same switch unit can be synchronously turned on and off.

Illustratively, the first node a may further include a fourth sub-node a2, the second node b may further include a fifth sub-node b2, and the third node c may further include a sixth sub-node c2. The first test switch A1 and the second test switch A2 are electrically connected to the fourth sub-node A2, the third test switch A3 and the fourth test switch A4 are electrically connected to the fifth sub-node b2, and the ninth test switch A9 and the tenth test switch a10 are electrically connected to the sixth sub-node c2. In a possible embodiment, the first end of the seventh switching unit Q7 may be electrically connected to one of the first sub-node a1 and the fourth sub-node a2, the first end of the eighth switching unit Q8 may be electrically connected to one of the second sub-node b1 and the fifth sub-node b2, and the first end of the twelfth switching unit Q12 may be electrically connected to one of the third sub-node c1 and the sixth sub-node c2, which is not particularly limited in the embodiment of the present utility model. One end of the second test switch A2, the fourth test switch A4, and the tenth test switch a10 connected to the tested chip U1 may be a high end SH of the test signal line of the kelvin test channel, and one end of the second switch K2 connected to the tested chip U1 may be a low end SL of the test signal line of the kelvin test channel.

Illustratively, referring to fig. 1, 2, or 3, the seventh switching unit Q7 includes a first sub-switch 71 and a second sub-switch 72; first ends of the first sub-switch 71 and the second sub-switch 72 are electrically connected to the first node a; a second end of the first sub-switch 71 is electrically connected to the high-side input terminal INH of the differential measurement circuit 40, and a second end of the second sub-switch 72 is electrically connected to the low-side input terminal INL of the differential measurement circuit 40; the eighth switching unit Q8 includes a third sub-switch 81 and a fourth sub-switch 82; the first ends of the third sub-switch 81 and the fourth sub-switch 82 are electrically connected with the second node b; a second terminal of the third sub-switch 81 is electrically connected to the high-side input terminal INH of the differential measurement circuit 40, and a second terminal of the fourth sub-switch 82 is electrically connected to the low-side input terminal INL of the differential measurement circuit. Similarly, the twelfth switching unit Q12 includes a fifth sub-switch 121 and a sixth sub-switch 122; the first ends of the fifth and sixth sub-switches 121 and 122 are electrically connected to the third node c; a second terminal of the fifth sub-switch 121 is electrically connected to the high-side input terminal INH of the differential measurement circuit 40, and a second terminal of the sixth sub-switch 122 is electrically connected to the low-side input terminal INL of the differential measurement circuit 40.

Illustratively, referring to fig. 3, first ends of the first and second sub-switches 71 and 72 are each electrically connected to the first sub-node a1, first ends of the third and fourth sub-switches 81 and 82 are each electrically connected to the second sub-node b1, and first ends of the fifth and sixth sub-switches 121 and 122 are each electrically connected to the third sub-node c 1.

Specifically, the voltage difference between the first test Pin1 and the second test Pin2 in the tested chip U1 is measured as an example. The second driving switch B2, the fourth driving switch B4, the first sub-switch 71 and the fourth sub-switch 82 may be controlled to be turned on, and the other switches are all turned off, at this time, the first test Pin1 is connected to the high-side input terminal INH of the differential measurement circuit 40, the second test Pin2 is connected to the low-side input terminal INL of the differential measurement circuit 40, and the differential measurement circuit 40 can determine the voltage differences V (Pin 1) -V (Pin 2) between the first test Pin1 and the second test Pin2 through the voltage signals received by the high-side input terminal INH and the low-side input terminal INL. Alternatively, the second driving switch B2, the fourth driving switch B4, the second sub-switch 72 and the third sub-switch 81 may be controlled to be turned on, and the other switches are all turned off, so that the voltage difference V (Pin 2) -V (Pin 1) between the second test Pin2 and the first test Pin1 may be determined by the voltage signals received by the high-side input terminal INH and the low-side input terminal INL by the differential measurement circuit 40.

It will be appreciated that in other possible embodiments of the present utility model, the first ends of the first sub-switch 71 and the second sub-switch 72 may be electrically connected to the fourth sub-node a2, the first ends of the third sub-switch 81 and the fourth sub-switch 82 may be electrically connected to the fifth sub-node b2, and the first ends of the fifth sub-switch 121 and the sixth sub-switch 122 may be electrically connected to the sixth sub-node c 2. At this time, the differential measurement of the two test pins of the tested chip U1 can be performed in the same manner as described above, and the description is omitted again.

Optionally, fig. 4 is a schematic structural diagram of another test circuit according to an embodiment of the present utility model, and as shown in fig. 4, the differential measurement circuit 40 includes: the control unit 41, the differential measurement unit 42 and the analog-to-digital conversion unit 43, wherein the high-end input terminal INH of the differential measurement unit 42 is electrically connected with the second end of the seventh switching unit Q7, the second end of the eighth switching unit Q8 and the second end of the twelfth switching unit Q12; the low-side input terminal INL of the differential measurement unit 42 is electrically connected to the third terminal of the seventh switching unit Q7, the third terminal of the eighth switching unit Q8, and the third terminal of the twelfth switching unit Q12; the analog signal input end of the analog-to-digital conversion unit 43 is electrically connected to the output end of the differential measurement unit 42, and the digital signal output end of the analog-to-digital conversion unit 43 is electrically connected to the input end of the control unit 41.

Specifically, the differential measurement unit 42 may be a differential amplifier, and the non-inverting input terminal of the differential amplifier may be the high-side input terminal INH, and the inverting input terminal of the differential amplifier may be the low-side input terminal INL. The differential measurement unit 42 may output the difference between the voltage of the high-side input terminal INH and the voltage of the low-side input terminal INL to the analog-to-digital conversion unit 43. The analog-to-digital conversion unit 43 may convert the analog voltage signal provided by the differential amplifier 42 into a digital voltage signal and output the digital voltage signal to the control unit 41, which may determine the measured voltage difference of the two test pins according to the received digital signal. The control unit 41 may be a microprocessor or a CPU, etc. and can implement signal processing and control functions, and the specific model of the control unit 41 is not particularly limited in the embodiment of the present utility model.

Optionally, referring to fig. 4, the test circuit further comprises a calibration module 50; the second ends of the fifth switching unit Q5 and the sixth switching unit Q6 are electrically connected to the input end of the calibration module 50. In this way, the calibration module 50 can calibrate the differential circuit, calibrate the output power signals of the voltage current sources, and calibrate the signal measurement accuracy of the voltage current sources by controlling the on-off of each signal in the test circuit.

Illustratively, the fifth switching unit Q5 further includes a fifth test switch A5, and the sixth switching unit Q6 further includes a sixth test switch A6; the first end of the fifth test switch A5 is electrically connected with the fourth sub-node a2, the first end of the sixth test switch A6 is electrically connected with the fifth sub-node b2, and the second end of the fifth test switch A5 and the second end of the sixth test switch A6 are electrically connected with the first input end of the calibration module 50; the second terminal of the fifth driving switch B5 and the second terminal of the sixth driving switch B6 are also electrically connected to the second input terminal of the calibration module 50. Similarly, the first end of the eleventh test switch a11 is electrically connected to the sixth sub-node c2, the second end of the eleventh test switch a11 is further electrically connected to the first input terminal of the calibration module 50, and the second end of the eleventh driving switch B11 is further electrically connected to the second input terminal of the calibration module 50.

Specifically, the calibration module 50 may be used to calibrate the differential measurement circuit 40. Illustratively, the differential measurement circuit 40 is calibrated by the first voltage current source 10 and the second voltage current source 20. The first voltage current source 10 and the second voltage current source 20 may be first controlled to be in a constant voltage mode, and the constant voltage value of the first voltage current source 10 is V1, and the constant voltage value of the second voltage current source 20 is V2. The first test switch A1, the third test switch A3, the first sub-switch 71 and the fourth sub-switch 82 may be controlled to be in an on state, and the other switches may be controlled to be all off, so that the actual measurement values V1-V2 of the voltage differences of the first voltage current source 10 and the second voltage current source 20 may be obtained through the differential measurement circuit 40. Then, the first test switch A1 and the fifth test switch A5 are controlled to be turned on, and other switches are controlled to be turned off, so that the calibration module 50 can obtain a measured value V11 of the test end of the first voltage current source 10; and then the third test switch A3 and the sixth test switch A6 are controlled to be turned on, and the calibration module 50 can obtain the measured value V21 of the test end of the second voltage current source 20, so that V11-V22 can be used as the standard value of the voltage difference between the first voltage current source 10 and the second voltage current source 20. By repeating the above operations, a plurality of sets of actual measurement values of the voltage difference and standard values of the voltage difference can be obtained, and the functional relationship between the actual measurement values of the voltage difference and the standard values of the voltage difference can be determined by fitting, so that after the measurement values of the two test pins are measured by the differential measurement module 40, the actual measurement values can be calibrated by the determined functional relationship, and more accurate standard values can be obtained. By adopting the arrangement mode, the calibration of the differential measurement circuit 40 can be realized without additionally adding an external power supply, the cost is greatly reduced, the implementation is simple and easy, and meanwhile, the accuracy of the differential measurement circuit 40 can be effectively improved. The calibration module 50 may be a precision meter, or may be a dedicated calibration module, and the ground end GND2 of the calibration module 50 may be electrically connected to the second switch K2 and the connection node of each voltage current source through a fourth switch K4 switch, and the ground end GND2 of the calibration module 50 may also be grounded through a fifth switch K5.

In a possible embodiment, the test circuit provided by the utility model can calibrate the output voltage and the output current of each voltage current source. As shown in fig. 4, taking the calibration output voltage as an example, the first driving switch B1 and the fifth driving switch B5 may be controlled to be turned on (at this time, the first test switch A1 and the fifth test switch A5 are synchronously turned on), and the other switches are turned off, so that the calibration module 50 may obtain the actual output voltage value of the first voltage current source 10 through the second input end thereof, and may calibrate the output voltage of the first voltage current source in combination with the preset output voltage of the first voltage current source, so that calibration of the output current can be achieved based on the same principle, which is not described herein. It can be understood that, in the same calibration manner, the calibration module 50 can calibrate the output voltage and the output current of the voltage-current source through the test signal of the first voltage-current source 10 obtained at the first input end thereof, which is not described herein.

Optionally, with continued reference to fig. 4, based on the same inventive concept, the calibration of the differential measurement circuit 40 and the calibration of the output signal of the voltage current source can be achieved through the power signal of the power end of each voltage current source, so that the test circuit provided by the embodiment of the utility model has strong expansibility, is more flexible and wide in application, and has more reliable performance.

In addition, a load resistor is usually provided in the calibration module 50, and based on this, the test circuit can calibrate the accuracy of signal measurement of each voltage current source. Taking the calibration output voltage as an example, the first driving switch B1, the fifth driving switch B5, the first test switch A1 and the fifth test switch A5 can be controlled to be turned on, and other switches are turned off, at this time, the calibration module can measure a voltage measurement value v1 of the load resistor through the power supply voltage output by the first voltage current source 10, the first voltage current source 10 can measure a voltage measurement value v2 of the load resistor through a detection signal line (a channel where the first test switch A1 and the fifth test switch A5 are located), multiple sets of v1 and v2 are measured and obtained, and a functional relation between v1 and v2 can be obtained through fitting v1 and v2, so that the calibration of the voltage measurement capability of the first voltage current source can be realized, and in practical use, the voltage current source can more accurately measure the voltage measurement value of the chip pin. Calibration of the current measurement capability can be achieved based on the same principle and will not be described in detail here.

Compared with the prior art that only the voltage current sources are calibrated, the test circuit provided by the embodiment of the utility model needs to be provided with the calibration modules corresponding to each voltage current source one by one, or manually accesses each voltage current source to one calibration for measurement, and only one calibration module is needed for realizing the calibration of each voltage current source, thereby being beneficial to reducing the cost and simplifying the calibration process.

Optionally, with continued reference to fig. 4, the test circuit further includes: a time measurement module 60 and a first switch K1; one end of the time measurement module 60 is electrically connected to a first end of the first switch K1, and a second end of the first switch K1 is electrically connected to any one of the first node a, the second node b, and the third node c.

The second terminal of the first switch K1 may be electrically connected to one of the fourth sub-node a2, the fifth sub-node b2, and the sixth sub-node c 2.

Specifically, the time measurement module 60 is configured to measure a time parameter (e.g. a signal period) of each test pin of the tested chip U1. Taking the first switch K1 as an example, it is electrically connected between the time measurement module 60 and the third node c. At this time, if the time parameter measurement needs to be performed on the third test Pin3 of the tested chip U1, the tenth test switch a10 and the first switch K1 can be controlled to be turned on, and other switches can be controlled to be turned off. If the time parameter measurement needs to be performed on the first test Pin1 of the tested chip U1, the second test switch A2, the fifth test switch A5, the eleventh test switch a11 and the first switch K1 can be controlled to be turned on, and other switches can be controlled to be turned off. Similarly, when the second test Pin2 of the tested chip U1 needs to be measured for a time parameter, the fourth test switch A4, the sixth test switch A6, the eleventh test switch a11 and the first switch K1 can be controlled to be turned on, and other switches can be controlled to be turned off. Compared with the prior art that when the time parameters of the signals of each pin of the tested chip are measured, a plurality of time measurement modules are required to be arranged corresponding to the plurality of test pins one by one, the measurement circuit provided by the embodiment of the utility model can realize the measurement of the signal delay of the plurality of test pins by only one time measurement module, has good test flexibility, greatly reduces test resources and is beneficial to reducing the circuit cost.

For example, in the embodiment of the present utility model, the control unit 41 in the differential measurement circuit 40 may be used to control on or off of each switch involved, and the control unit 41 may be used to control the operation mode (constant current mode or constant voltage mode) of each voltage current source, and the output signal value. In addition, the voltage current sources, the differential measurement circuit, the time measurement module, the calibration module and the like may be in the same board card or in different board cards, and the embodiment of the utility model is not limited in particular.

Based on the same inventive concept, the embodiment of the present utility model further provides a circuit board, which includes the test circuit provided by any embodiment of the present utility model, so that the circuit board provided by any embodiment of the present utility model includes the technical features of the test circuit provided by any embodiment of the present utility model, so that the beneficial effects of the test circuit provided by any embodiment of the present utility model can be achieved, and the same points can be referred to the description of the test circuit provided by any embodiment of the present utility model, which is not repeated herein.

The above embodiments do not limit the scope of the present utility model. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present utility model should be included in the scope of the present utility model.

Claims (9)

1. A test circuit comprising at least: the switching device comprises a first voltage current source, a second voltage current source, a differential measurement circuit, a first switching unit, a second switching unit, a third switching unit, a fourth switching unit, a fifth switching unit, a sixth switching unit, a seventh switching unit and an eighth switching unit;

the first switch unit and the second switch unit are connected in series to a first node, and the power end of the first voltage current source is electrically connected to a first test pin of the chip to be tested through the first switch unit and the second switch unit which are sequentially connected in series;

the third switch unit and the fourth switch unit are connected in series to the second node, and the power end of the second voltage current source is electrically connected to a second test pin of the tested chip through the third switch unit and the fourth switch unit which are sequentially connected in series;

The first end of the fifth switch unit is electrically connected with the first node; the first end of the sixth switch unit is electrically connected with the second node; the second end of the fifth switch unit is electrically connected with the second end of the sixth switch unit;

the first end of the seventh switch unit is electrically connected with the first node, and the first end of the eighth switch unit is electrically connected with the second node; the second end of the seventh switching unit and the second end of the eighth switching unit are electrically connected with the high-end input end of the differential measurement circuit; the third end of the seventh switching unit and the third end of the eighth switching unit are electrically connected with the low-end input end of the differential measurement circuit.

2. The test circuit of claim 1, wherein the first switching unit comprises a first drive switch; the second switch unit comprises a second driving switch; the third switch unit comprises a third driving switch; the fourth switch unit comprises a fourth driving switch; the fifth switching unit includes a fifth driving switch; the sixth switch unit comprises a sixth driving switch;

the first node comprises a first sub-node, and the first driving switch and the second driving switch are connected in series to the first sub-node; the power end of the first voltage current source is electrically connected to a first test pin of the chip to be tested through a first drive switch and a second drive switch which are sequentially connected in series;

The second node comprises a second sub-node, and the third driving switch and the fourth driving switch are connected in series with the second sub-node; the power end of the second voltage current source is electrically connected to a second test pin of the tested chip through a third driving switch and a fourth driving switch which are sequentially connected in series;

the first end of the fifth driving switch is electrically connected with the first sub-node; the first end of the sixth driving switch is electrically connected with the second sub-node; the second end of the fifth driving switch is electrically connected with the second end of the sixth driving switch.

3. The test circuit of claim 2, wherein the first switching unit further comprises a first test switch; the second switch unit further comprises a second test switch; the third switch unit further comprises a third test switch; the fourth switch unit further comprises a fourth test switch;

the first test switch and the second test switch are connected in series with the test end of the first voltage current source and the first test pin of the tested chip; the third test switch and the fourth test switch are connected in series with the test end of the second voltage current source and the second test pin of the tested chip.

4. The test circuit of claim 1, wherein the seventh switching unit comprises a first sub-switch and a second sub-switch; the first ends of the first sub switch and the second sub switch are electrically connected with a first node; the second end of the first sub-switch is electrically connected with the high-end input end of the differential measurement circuit, and the second end of the second sub-switch is electrically connected with the low-end input end of the differential measurement circuit;

The eighth switch unit comprises a third sub switch and a fourth sub switch; the first ends of the third sub-switch and the fourth sub-switch are electrically connected with the second node; the second end of the third sub-switch is electrically connected with the high-end input end of the differential measurement circuit, and the second end of the fourth sub-switch is electrically connected with the low-end input end of the differential measurement circuit.

5. The test circuit of claim 1, wherein the differential measurement circuit comprises: the device comprises a control unit, a differential measurement unit and an analog-to-digital conversion unit;

the high-end input end of the differential measurement unit is electrically connected with the second end of the seventh switch unit and the second end of the eighth switch unit;

the low-end input end of the differential measurement unit is electrically connected with the third end of the seventh switching unit and the third end of the eighth switching unit;

the analog signal input end of the analog-to-digital conversion unit is electrically connected with the output end of the differential measurement unit, and the digital signal output end of the analog-to-digital conversion unit is electrically connected with the input end of the control unit.

6. The test circuit of claim 3, further comprising: a calibration module;

the second ends of the fifth switch unit and the sixth switch unit are also electrically connected with the input end of the calibration module.

7. The test circuit of claim 6, wherein the fifth switching unit further comprises a fifth test switch, and the sixth switching unit further comprises a sixth test switch; the first node further comprises a fourth sub-node, and the second node further comprises a fifth sub-node; the first test switch and the second test switch are electrically connected to the fourth sub-node, and the third test switch and the fourth test switch are electrically connected to the fifth sub-node;

the first end of the fifth test switch is electrically connected with the fourth sub-node, the first end of the sixth test switch is electrically connected with the fifth sub-node, and the second end of the fifth test switch and the second end of the sixth test switch are electrically connected with the first input end of the calibration module;

the second end of the fifth driving switch and the second end of the sixth driving switch are also electrically connected with the second input end of the calibration module.

8. The test circuit of claim 1, further comprising: a time measurement module and a first switch;

one end of the time measurement module is electrically connected with a first end of the first switch, and a second end of the first switch is electrically connected with any one of the first node and the second node.

9. A circuit board comprising a test circuit as claimed in any one of claims 1 to 8.