CN219657814U - USB3.0PHY chip verification test board - Google Patents

Abstract

The utility model relates to USB3.0 test, in particular to a USB3.0PHY chip verification test board, a main controller, a test data receiving device and a test data processing device, wherein the main controller is used for controlling an FPGA chip and a USB3.0PHY chip verification platform and receiving test data fed back by the USB3.0PHY chip verification platform; the FPGA chip is used for carrying out verification test on the function of the USB3.0PHY chip verification platform; USB3.0PHY chip verification platform, carrying USB3.0PHY chip, carrying out interactive communication with FPGA chip, configuring USB3.0PHY chip, debug USB3.0PHY chip and sending test data to main controller; the technical scheme provided by the utility model can effectively overcome the defects of higher verification test cost and difficulty in fully meeting the user verification test requirement in the prior art.

Description

USB3.0PHY chip verification test board

Technical Field

The utility model relates to USB3.0 testing, in particular to a USB3.0PHY chip verification test board.

Background

USB is a well-known universal interface, and it goes through the stages of USB1.0 Low speed (1.5 Mbps), full speed USB1.1 Full speed (12 Mbps), high speed USB2.0 High speed (480 Mbps), and ultra High speed USB3.0 (5 Gbps).

The USB3.0 interface is mainly applied to computers, cameras, printers, mobile hard disks, mobile phones, automobiles and the like, and two master-slave devices can be connected by one USB3.0 line to realize data intercommunication. With the continuous development of USB, newly developed USB protocols are often downward compatible, and users do not need to consider compatibility issues.

The USB3.0 adopts a new physical layer, separates the transmission and confirmation processes of data through two channels, adopts a packet-routing (packet-routing) technology, and only allows terminal equipment to transmit when the terminal equipment has data to send, thereby achieving the data transmission rate of 5 Gbps.

In order to meet the requirement of a user to verify and test the functions of a USB3.0PHY chip, a USB3.0PHY chip verification test board needs to be designed, the test board needs to meet the requirement of a user on USB3.0 series compatibility test CTS (Compatibility Test suite), a chip debug pin and FMC (FPGA Mezzanine Card) interface connected with an FPGA are reserved, and the design requirement on ESD (Electro-Static discharge) and the like needs to be met.

For the existing USB3.0PHY chip verification test board on the market, the number of the FPGA which can be matched with the board is very small, if any, the board is realized based on a high-end FPGA, so that the verification test cost is high, and the existing USB3.0PHY chip verification test board is difficult to fully meet the verification test requirement of a user.

Disclosure of Invention

(one) solving the technical problems

Aiming at the defects existing in the prior art, the utility model provides the USB3.0PHY chip verification test board, which can effectively overcome the defects of higher verification test cost and difficulty in fully meeting the user verification test requirement existing in the prior art.

(II) technical scheme

In order to achieve the above purpose, the utility model is realized by the following technical scheme:

a USB3.0PHY chip verification test board comprises a main controller, an FPGA chip and a USB3.0PHY chip verification platform;

the main controller is used for controlling the FPGA chip and the USB3.0PHY chip verification platform and receiving the test data fed back by the USB3.0PHY chip verification platform;

the FPGA chip is used for carrying out verification test on the function of the USB3.0PHY chip verification platform;

USB3.0PHY chip verification platform carries USB3.0PHY chip, carries out interactive communication with FPGA chip, configures USB3.0PHY chip, debugs USB3.0PHY chip simultaneously, and sends test data to main control unit.

Preferably, the main controller controls the FPGA chip and the USB3.0PHY chip verification platform through a third communication module, and the third communication module is provided with a JTAG interface.

Preferably, the main controller is connected with external equipment for receiving the feedback test data of the USB3.0PHY chip verification platform through a second communication module;

the external equipment comprises an oscilloscope and/or an error coder.

Preferably, the USB3.0PHY chip verification platform comprises a USB3.0PHY chip, and an FMC interface, a first communication module, a JTAG interface and an interface module which are connected with the USB3.0PHY chip;

the FMC interface is used for carrying out interactive communication between the USB3.0PHY chip and the FPGA chip;

the first communication module converts USB bus signals of the USB interface into I2C signals to configure the USB3.0PHY chip;

JTAG interface, which is used to Debug USB3.0PHY chip and read CLK and register state;

and the interface module is used for sending the test data of the USB3.0PHY chip to the external equipment.

Preferably, the twelfth bank area of the FPGA chip is in signal connection with tx_data and Pclk in the PIPE interface of the USB3.0PHY chip through a second FMC interface;

the sixteenth bank area of the FPGA chip is in signal connection with RX_ DATA, reset, powerdown in the PIPE interface of the USB3.0PHY chip through a first FMC interface;

the twelfth bank area and the sixteenth bank area of the FPGA chip comprise CLK and GPIO signals.

Preferably, the FPGA chip is a Xilinx Kintex-7 series chip.

(III) beneficial effects

Compared with the prior art, the verification test board for the USB3.0PHY chip provided by the utility model can be effectively matched with the FPGA chip at the lower end, so that the verification test cost of the USB3.0PHY chip can be reduced, and meanwhile, the verification test requirement of a user on the function of the USB3.0PHY chip can be fully met.

Drawings

In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It is evident that the drawings in the following description are only some embodiments of the present utility model and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.

FIG. 1 is a hardware schematic of the present utility model.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present utility model more clear, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model. It will be apparent that the described embodiments are some, but not all, embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

A USB3.0PHY chip verification test board, as shown in fig. 1, comprises a main controller, an FPGA chip and a USB3.0PHY chip verification platform;

the main controller is used for controlling the FPGA chip and the USB3.0PHY chip verification platform and receiving the test data fed back by the USB3.0PHY chip verification platform;

the FPGA chip is used for carrying out verification test on the function of the USB3.0PHY chip verification platform;

USB3.0PHY chip verification platform carries USB3.0PHY chip, carries out interactive communication with FPGA chip, configures USB3.0PHY chip, debugs USB3.0PHY chip simultaneously, and sends test data to main control unit.

(1) The main controller controls the FPGA chip and the USB3.0PHY chip verification platform through a third communication module, and the third communication module is provided with a JTAG interface.

The main controller is connected with external equipment for receiving the feedback test data of the USB3.0PHY chip verification platform through a second communication module;

the external equipment comprises an oscilloscope and/or an error coder.

(2) The USB3.0PHY chip verification platform comprises a USB3.0PHY chip, and an FMC interface, a first communication module, a JTAG interface and an interface module which are connected with the USB3.0PHY chip;

the FMC interface is used for carrying out interactive communication between the USB3.0PHY chip and the FPGA chip;

the first communication module converts USB bus signals of the USB interface into I2C signals to configure the USB3.0PHY chip;

JTAG interface, which is used to Debug USB3.0PHY chip and read CLK and register state;

and the interface module is used for sending the test data of the USB3.0PHY chip to the external equipment.

(3) The twelfth bank area of the FPGA chip is in signal connection with TX_DATA and Pclk in the PIPE interface of the USB3.0PHY chip through a second FMC interface;

the sixteenth bank area of the FPGA chip is in signal connection with RX_ DATA, reset, powerdown in the PIPE interface of the USB3.0PHY chip through a first FMC interface;

the twelfth bank area and the sixteenth bank area of the FPGA chip comprise CLK and GPIO signals.

In the technical scheme of the utility model, the FPGA chip adopts Xilinx Kintex-7 series chips.

(4) The power supply module is mainly realized by adopting a power supply circuit consisting of a LDO (Low dropout regulator) power supply chip, a filter capacitor and a configuration resistor. The USB3.0PHY chip verification platform has a total of 3 LDO power chips, namely 3 MIC69303 power chips of Microchip company.

In specific implementation, the 3 LDO power chips are respectively set to be ldo1=1. V, LDO2 =2. V, LDO3 =3.3v voltage supply AVDD12, DVDD12, AVDD25, DVDD33, and the output currents of the 3 LDO power chips are all 3A.

The 3 LDO power chips realize manual adjustment of +/-5% and +/-10% of output voltage by using a switch dial switch, and the corresponding output voltage ranges are LDO1=1.08V-1. V, LDO2 =2.25V-2. V, LDO3 =2.97V-3.63V respectively.

The working process of the technical scheme of the utility model is approximately as follows:

1) The switch is opened to power on the FPGA chip and the USB3.0PHY chip for instant starting, so that power on configuration time is not required to wait;

2) Programming a hardware design program through a tool provided by the FPGA chip;

3) Connecting external equipment (including an oscilloscope and/or an error coder) without interrupting the operation of the equipment;

4) And starting a USB3.0PHY chip function verification test, and performing configuration and debugging in a plurality of modes of JTAG and I2C, UART.

The USB3.0PHY chip adopts a JTAG configuration mode, and is configured by using a JTAG interface. And at the PC end, the download debugging is realized by communicating with an upper computer through a Micro USB interface.

The technical scheme of the utility model can be effectively matched with the FPGA chip at the lower end, so that the verification test cost of the USB3.0PHY chip can be reduced, and the verification test requirement of a user on the USB3.0PHY chip function can be fully met.

The pin functions of the electrical components involved in the technical scheme of the utility model can be checked on technical data, and the circuit connection between the electrical components can be performed according to the technical data, so that the person skilled in the art can complete the work.

It should be noted that the purpose of the technical solution of the present utility model is only to provide a hardware configuration different from the prior art, so that a technician can implement further development under such a hardware configuration, and the software program can be programmed by a programmer in the field at a later stage according to the actual effect requirement.

The above embodiments are only for illustrating the technical solution of the present utility model, and are not limiting; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present utility model.

Claims (6)

1. USB3.0PHY chip verifies test panel, its characterized in that: the system comprises a main controller, an FPGA chip and a USB3.0PHY chip verification platform;

the main controller is used for controlling the FPGA chip and the USB3.0PHY chip verification platform and receiving the test data fed back by the USB3.0PHY chip verification platform;

the FPGA chip is used for carrying out verification test on the function of the USB3.0PHY chip verification platform;

USB3.0PHY chip verification platform carries USB3.0PHY chip, carries out interactive communication with FPGA chip, configures USB3.0PHY chip, debugs USB3.0PHY chip simultaneously, and sends test data to main control unit.

2. The USB3.0PHY chip authentication test board of claim 1, further comprising: the main controller controls the FPGA chip and the USB3.0PHY chip verification platform through a third communication module, and the third communication module is provided with a JTAG interface.

3. The USB3.0PHY chip authentication test board of claim 2, further comprising: the main controller is connected with external equipment for receiving the feedback test data of the USB3.0PHY chip verification platform through a second communication module;

the external equipment comprises an oscilloscope and/or an error coder.

4. A USB3.0PHY chip verification test board according to claim 3, wherein: the USB3.0PHY chip verification platform comprises a USB3.0PHY chip, and an FMC interface, a first communication module, a JTAG interface and an interface module which are connected with the USB3.0PHY chip;

the FMC interface is used for carrying out interactive communication between the USB3.0PHY chip and the FPGA chip;

the first communication module converts USB bus signals of the USB interface into I2C signals to configure the USB3.0PHY chip;

JTAG interface, which is used to Debug USB3.0PHY chip and read CLK and register state;

and the interface module is used for sending the test data of the USB3.0PHY chip to the external equipment.

5. The USB3.0PHY chip authentication test board of claim 4, further comprising: the twelfth bank area of the FPGA chip is in signal connection with TX_DATA and Pclk in the PIPE interface of the USB3.0PHY chip through a second FMC interface;

the sixteenth bank area of the FPGA chip is in signal connection with RX_ DATA, reset, powerdown in the PIPE interface of the USB3.0PHY chip through a first FMC interface;

the twelfth bank area and the sixteenth bank area of the FPGA chip comprise CLK and GPIO signals.

6. The USB3.0PHY chip authentication test board of claim 5, further comprising: the FPGA chip adopts XilinxKintex-7 series chips.