CN219268945U - Image sensor evaluating switching device and evaluating system - Google Patents

Abstract

The application discloses image sensor evaluates switching device and evaluation system, image sensor evaluates switching device and includes: the switching board is used for generating a first induction signal, a second induction signal and a third induction signal and splitting the first induction signal into a first level signal and a second level signal; the first level conversion circuit is used for generating a third level signal according to a first interface procedure of the signal receiving end of the first induction signal; the second level conversion circuit is used for generating a fourth level signal according to a second interface procedure of the signal receiving end of the second induction signal; a signal processing circuit extracting image data of the sensing signal; and sending the image sensor to an evaluation platform for evaluating the image sensor. The universality of the identification of the output signals of the image sensor is realized through multiplexing and unification of multiple data interfaces.

Description

Image sensor evaluating switching device and evaluating system

Technical Field

The application relates to the technical field of image sensors, in particular to an image sensor evaluating switching device and an evaluating system.

Background

The image sensing photoelectric test system is a physical performance test instrument used in the fields of information and system science related engineering and technology. The image sensor uses a photoelectric conversion function of a photoelectric device. The light image on the light sensitive surface is converted into an electric signal in a proportional relation with the light image. Is a device for converting an optical image into an electronic signal, and is widely used in digital cameras and other electronic optical devices.

In the existing image sensor, the image signals are divided into three signal types of LVDS (Low-voltage differential signaling), DVP (digital video interface, digital Video Port) and MIPI (mobile industry processor interface ), and the data interfaces of the respective data types are not unified. Meanwhile, the voltage requirements of the CMOS image sensors are not uniform.

In research, the applicant finds that in the existing evaluation system, a plurality of evaluation systems may be used for evaluating the CMOS image sensors with various data interface types or various voltage ranges respectively, but the measurement of different image sensors requires replacement of the hardware of the evaluation system, so that inconvenience is brought to a user, and the use efficiency is reduced; as demand increases, the increase in the amount of hardware in the evaluation system also greatly increases costs.

Disclosure of Invention

Based on the above problems, the present application provides an image sensor evaluation switching method, which includes:

acquiring induction signals of an image sensor, and generating a first induction signal, a second induction signal and a third induction signal through an adapter plate;

splitting the first induction signal into a first level signal and a second level signal, and generating a third level signal according to a first interface procedure of a signal receiving end of the first induction signal;

generating a fourth level signal according to a second interface procedure of the signal receiving end of the second induction signal;

identifying image data of the sensing signals according to the second level signal, the third level signal, the fourth level signal and the third sensing signal; and evaluating the image sensor according to the image data.

Optionally, the step of acquiring the sensing signal of the image sensor includes:

and configuring the image sensor according to preset parameters.

Optionally, the step of generating the third level signal according to the first interface procedure of the signal receiving end of the first sensing signal includes:

the first level signal is input into a first level conversion circuit for level conversion to output the third level signal.

Optionally, the step of generating the fourth level signal according to the second interface procedure of the signal receiving end of the second sensing signal includes:

and inputting the second sensing signal into a second level conversion circuit for level conversion to output the fourth level signal.

Optionally, the transmission channel of the first sensing signal is an MIPI signal channel;

the step of identifying the image data of the sensing signal includes:

respectively carrying out serial-to-parallel processing on the second level signal and the third level signal to obtain a first parallel data stream;

detecting a synchronous code in the first parallel data stream, and determining a frame header field, a frame tail field, a check code and an MIPI signal data field of an MIPI signal;

and synchronously reading MIPI signal data fields in a plurality of data channels, and checking according to the check codes to obtain MIPI signal data.

Optionally, the transmission channel of the second sensing signal is a DVP signal channel;

the step of identifying the image data of the sensing signal includes:

extracting a frame synchronization signal and a line synchronization signal of a DVP signal according to the fourth level signal in an adaptive manner;

And extracting DVP signal data in the fourth level signal according to the frame synchronous signal and the row synchronous signal of the DVP signal.

Optionally, the transmission channel of the third sensing signal is an LVDS signal channel;

the step of identifying the image data of the sensing signal includes:

performing serial-to-parallel processing on the third induction signal to obtain a second parallel data stream;

determining the frame head position of the LVDS signal according to the second parallel data stream;

extracting LVDS signal data fields in the second parallel data stream according to the frame head position;

and decoding to obtain LVDS signal data according to the LVDS signal data field.

Optionally, the step of evaluating the image sensor according to the image data includes:

reading at least one of the MIPI signal data, the DVP signal data and the LVDS signal data, and packaging the data into MIPI image data frames according to a MIPI signal format;

and sending the MIPI image data frame to an evaluation platform for evaluation.

Optionally, the application further provides an image sensor evaluating switching device, which includes:

the adapter plate is used for acquiring induction signals of the image sensor, generating a first induction signal, a second induction signal and a third induction signal through the adapter plate, and splitting the first induction signal into a first level signal and a second level signal;

The first level conversion circuit is connected with the adapter plate and used for generating a third level signal according to a first interface procedure of the signal receiving end of the first induction signal;

the second level conversion circuit is connected with the adapter plate and used for generating a fourth level signal according to a second interface procedure of the signal receiving end of the second induction signal;

the signal processing circuit is respectively connected with the adapter plate, the first level conversion circuit and the second level conversion circuit and can extract image data of the induction signals according to the second level signal, the third level signal, the fourth level signal and the third induction signal; and the image data can be sent to an evaluation platform so as to evaluate the image sensor.

Optionally, the first sensing signal is an MIPI signal, the second sensing signal is a DVP signal, and the third sensing signal is an LVDS signal; the signal processing circuit comprises an MIPI image data receiving module, an LVDS image data receiving module and a DVP image data receiving module;

the MIPI image data receiving module is used for receiving MIPI signal data of the MIPI signal, the LVDS image data receiving module is used for receiving LVDS signal data of the LVDS signal, and the DVP image data receiving module is used for receiving DVP signal data of the DVP signal.

Optionally, the signal processing circuit further comprises at least one of:

the I2C module is used for communication between the evaluation platform and the signal processing circuit so as to configure the signal processing circuit;

the system clock module is used for generating a clock with a corresponding frequency for the signal processing circuit to use;

the sensor clock configuration module is used for providing corresponding clock signals for the image sensor to evaluate according to the configuration of the upper computer;

a PWM module for generating a frame synchronization signal to trigger the image sensor;

the data caching module is used for caching the image data;

the algorithm processing module is used for sequentially reading the image data according to frames and carrying out preset image algorithm processing;

the USB module is used for integrating the time sequence of the image data so as to send the image data according to frames;

the data transmitting module is used for decoding the image data, and packaging the image data into MIPI image data frames according to a MIPI signal format so as to transmit the image data;

the optical fiber module is used for packaging the image data with a standard UDP protocol so as to be sent through an optical fiber;

and the firmware upgrading module is used for receiving the upgrading file of the evaluation platform and performing CRC (cyclic redundancy check) on the upgrading file so as to upgrade the signal processing circuit.

Optionally, the image sensor evaluation switching device further comprises at least one of the following:

the I2C control module is respectively connected with the signal processing circuit and the image sensor, and is used for respectively controlling I2C communication inside the signal processing circuit and I2C communication of the image sensor based on an I2C control link of the I2C module;

the storage module is connected with the signal processing circuit and used for storing the image data;

the programmable clock module is connected with the signal processing circuit and used for providing corresponding clock signals for the image sensor under the control of the signal processing circuit;

the power module is used for providing a working power supply;

and the data output module is connected with the signal processing circuit and is used for receiving and transmitting data between the signal processing circuit and the evaluation platform.

Optionally, the power module includes a system power module and a programmable power module:

the system power supply module comprises a PMIC and a DCDC power supply chip and is used for providing system power supply;

the programmable power module is connected with the system power module and comprises a linear stabilized voltage power supply, an ADC chip, a DAC chip and a current measuring chip, and is used for providing a programmable power supply for the image sensor.

Optionally, the data output module includes at least one of a USB data output module, a fiber SFP data output module, and a data transmission module:

the USB data output module comprises an FX3 chip, an EEPROM chip and a FLASH chip, which are connected between the evaluation platform and the signal processing circuit, wherein the FX3 chip is connected with the EEPROM chip through an I2C signal, the FX3 chip is connected with the FLASH chip through an SPI signal, and the FX3 chip is connected with the signal processing circuit through an I2C signal;

the optical fiber SFP data output module comprises an SFP interface conversion chip and an ESD protection tube which are connected with each other, and is used for converting the image data sent by the signal processing circuit into optical signals to be sent to the evaluation platform;

the data transmitting module comprises a bridge chip and a third level converting circuit, wherein the bridge chip is connected with the signal processing circuit through the third level converting circuit and is used for combining the image data subjected to level conversion into MIPI signals to be transmitted to the evaluation platform, and the third level converting circuit is used for converting the levels of the MIPI signals so as to adapt to the interface specification of the MIPI signal receiving end.

The application also provides an image sensor evaluating system which comprises an image sensor, an evaluating platform and the image sensor evaluating switching device, wherein the image sensor is connected with the evaluating platform through the image sensor evaluating switching device, so that the evaluating platform evaluates the image sensor through the image sensor evaluating switching device.

The present application also provides a storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the image sensor evaluation adapting method as described above.

Compared with the prior art, the beneficial effects of this application are:

the image sensor evaluation switching method, the device, the evaluation system and the storage medium realize the universality of the image sensor output signal identification through multiplexing and unification of the multipath data interfaces, facilitate the evaluation of the image sensor and can meet the evaluation requirements of different types of image sensors.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.

Fig. 1 is a flowchart of an image sensor evaluation switching method according to an embodiment of the present application.

Fig. 2 is a block diagram of an image sensor evaluation adapting device according to an embodiment of the present application.

Fig. 3 is a schematic diagram illustrating connection between a signal processing circuit and an interposer according to an embodiment of the present application.

Fig. 4 is a circuit board wiring diagram of an image sensor evaluation switching device according to an embodiment of the present application.

Fig. 5 is a schematic diagram of a read-write cache structure according to an embodiment of the present application.

Fig. 6 is a schematic diagram illustrating connection of an I2C control module according to an embodiment of the present application.

FIG. 7 is a block diagram of an image sensor evaluation system according to an embodiment of the present application.

FIG. 8 is a flowchart illustrating the operation of an image sensor evaluation system according to an embodiment of the present application.

The realization, functional characteristics and advantages of the present application will be further described with reference to the embodiments, referring to the attached drawings. Specific embodiments thereof have been shown by way of example in the drawings and will herein be described in more detail. These drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the element defined by the phrase "comprising one … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element, and furthermore, elements having the same name in different embodiments of the present application may have the same meaning or may have different meanings, a particular meaning of which is to be determined by its interpretation in this particular embodiment or by further combining the context of this particular embodiment.

It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.

First embodiment

Fig. 1 is a flowchart of an image sensor evaluation switching method according to an embodiment of the present application.

As shown in fig. 1, in an embodiment, the image sensor evaluation switching method includes:

S10: and acquiring induction signals of the image sensor, and generating a first induction signal, a second induction signal and a third induction signal through the adapter plate.

The image sensor converts the light image on the light sensing surface into an electric signal in a corresponding proportional relation with the light image by utilizing the photoelectric conversion function of the photoelectric device. In contrast to light sensitive elements of "point" light sources such as photodiodes, phototriodes, etc., an image sensor is a functional device that divides the light image on its light-receiving surface into a number of small cells that are converted into a usable electrical signal. The evaluation is a process of evaluating the effect of the product, from the use angle of the user, the demand effect is verified before the product is on line, and the three-dimensional effect evaluation of the product is established through the comprehensive analysis of the product, the user data and the bid data. The adapter plate is an intermediate bypass connection link for signal transfer between at least two unmatched interfaces. Illustratively, in the image sensor product architecture, image signals are generally classified into various signal types such as LVDS, DVP, and MIPI. The signals of the image sensor are converted into multipath signals through the adapter plate so as to be matched with the interface of the signal receiving end in electrical rules and protocols. For example, during evaluation, the image sensor sends data, the sensing signal is connected to the adapter board through the pin header, the multiple sensing signal data interfaces such as MIPI, LVDS, DVP are respectively plugged into the same adapter board through different interfaces, and then the data and the configuration signal are connected to the signal processing circuit board system through the high-speed connector (pin header) on the adapter board and the female socket (e.g. female header) on the signal processing circuit board.

S20: splitting the first induction signal into a first level signal and a second level signal, and generating a third level signal according to a first interface procedure of a signal receiving end of the first induction signal.

Illustratively, after the MIPI data signal is processed by the bridge chip, the HS signal and the LP signal can be separated, which are the main components of the MIPI signal. Optionally, by splitting different components of the first sensing signal, further matching adjustment can be performed according to the interface electrical rule of the signal input end, so as to obtain a third level signal matched with the corresponding signal receiving end, and ensure the correctness of signal transmission.

S30: and generating a fourth level signal according to a second interface procedure of the signal receiving end of the second induction signal.

Optionally, further matching adjustment can be performed according to the interface electrical specification of the signal input end, and level adjustment is performed on the second sensing signal, so that a fourth level signal matched with the corresponding signal receiving end is obtained, and accuracy of signal transmission is guaranteed.

S40: and identifying the image data of the sensing signal according to the second level signal, the third level signal, the fourth level signal and the third sensing signal. To evaluate the image sensor based on the image data.

Optionally, the second level signal, the third level signal, the fourth level signal and the third sensing signal are respectively received by the signal processing circuit, and are respectively subjected to effective data identification so as to extract image data. Regardless of the type of signal that the initial configuration of the image sensor is, the image data of the image sensor can be successfully identified through the above steps.

Optionally, the image data of the image sensor is successfully identified through the steps, and the image data can be sent to an evaluation platform so as to evaluate the performance of the image sensor according to the identified image data.

Through multiplexing and unification of the multipath data interfaces, the universality of the identification of the output signals of the image sensors can be realized, the evaluation of the image sensors is convenient, the trouble of repeated plugging configuration during the evaluation of different image sensors is avoided, and the evaluation requirements of various different types of image sensors can be met.

Optionally, the step of acquiring the sensing signal of the image sensor includes, before:

the image sensor is configured according to preset parameters.

Optionally, when the image sensor starts to work, the related register is firstly written with parameters so that the image sensor senses the light according to the written parameters. The signal processing circuit may, for example, perform configuration of the image sensor through I2C or SPI (serial peripheral interface ). Illustratively, the additionally configured image sensor clock configuration module provides clocks with selectable frequencies (6 MHz,7MHz,8MHz,9MHz,12MHz,24MHz,25MHz,27MHz,37.125 MHz) according to the configuration of the evaluation platform upper computer, and outputs the clocks to the FPGA for the image sensor.

Optionally, the step of generating the third level signal according to the first interface procedure of the signal receiving end of the first sensing signal includes:

the first level signal is input into a first level conversion circuit for level conversion to output a third level signal.

Illustratively, in the MIPI signal, the HS signal level is low, which is a high-speed signal, and the HS signal is directly transmitted to the signal processing circuit for processing without undergoing level conversion. While the LP signal depends on the signal splitting circuit Output IO (Input/Output) level, which should typically be 2.5V. The input/output unit is an interface part of the chip and an external circuit, and can fulfill the driving and matching requirements of input/output signals under different electrical characteristics. The IO level of the receiving end of the signal processing circuit depends on the level required by the driving and matching of the received signal, so that when the levels of the receiving end and the transmitting end are inconsistent, the signal is processed by the first level conversion circuit to the level which can be identified by the receiving end.

Optionally, the step of generating the fourth level signal according to the second interface procedure of the signal receiving end of the second sensing signal includes:

the second sensing signal is input into a second level conversion circuit for level conversion to output a fourth level signal.

Illustratively, the DVP signal path is composed of a DVP signal interface and a level shift circuit for receiving and level shifting DVP image data. The DVP data includes that the configuration signals of the image sensor have corresponding IO levels, and the IO levels output by the image sensor may not be consistent with the levels of the corresponding connection interfaces of the signal processing circuit, so that the level conversion circuit is required. Therefore, the DVP signal enters the signal processing circuit through the connector, and is converted into a level required by the signal processing circuit interface through the level converter or other chips for transmission. For example, the chip configuration signal I2C (two-wire serial bus signal, inter-Integrated Circuit, two wires in parallel are serial data wire SDA and serial Clock wire SCL) and MCLK (system Clock) or other GPIO (General-purpose input/output) signals may also be level-converted by the second level conversion circuit and then input to the signal processing circuit, where the transmission relationship is similar to that of the DVP signal, and reference may be made to the description of the above MIPI embodiment.

Optionally, the transmission channel of the first sensing signal is an MIPI signal channel. The step of identifying image data of the sensing signal may comprise:

Respectively carrying out serial-to-parallel processing on the second level signal and the third level signal to obtain a first parallel data stream;

detecting a synchronous code in a first parallel data stream, and determining a frame header field, a frame tail field, a check code and an MIPI signal data field of an MIPI signal;

and synchronously reading MIPI signal data fields in the data channels, and checking according to the check codes to obtain MIPI signal data.

Illustratively, the MIPI signal receiving module receives image data in an external MIPI format, converts a high-speed serial data stream into a parallel data stream by a serial-to-parallel procedure. And then detecting a synchronization code (sync code) in the parallel data stream for identifying signals of different areas, and verifying the synchronization code in the parallel data stream so as to ensure that a receiving end inputs complete and coherent signals), and determining the frame head position by adding the change of a double-end signal of Low-Power (LP (double-end transmission channel) for Low Power consumption. And caching the data stream obtained by positioning, synchronizing data among different channels, decoding MIPI image data from the data stream, and detecting the correctness of data transmission through a CRC check code (cyclic redundancy check, cyclic Redundancy Check, used for detecting or checking errors possibly occurring after data transmission or storage).

Alternatively, for image data in MIPI format, a high-speed serial data stream is converted into a parallel data stream by serial-parallel processing. For each data channel, the start of the valid data stream is determined, and then the synchronization code is detected by means of bit-shifting in the parallel data stream, so that the valid data stream start position can be accurately determined. From which the start of frame short packet field, end of frame short packet field, and image data long packet field can be intercepted. Optionally, the data of the data channels are synchronously read by caching the effective data of different channels and synchronously reading when the caching amount reaches a certain threshold value, so that the data of the data channels are synchronously read. Optionally, checking and calculating each image data long packet, comparing with the attached CRC check value of the tail at the end of the long packet, discarding the current image long packet data when the calculated value is inconsistent with the actual value, and adjusting the relative delay of the clock signal and the data signal in the serial-parallel IP until the image long packet data with the CRC check is identified.

Optionally, the transmission channel of the second sensing signal is a DVP signal channel. The step of identifying image data of the sensing signal may comprise:

extracting a frame synchronization signal and a line synchronization signal of the DVP signal according to the fourth level signal in an adaptive manner;

And extracting DVP signal data in the fourth level signal according to the frame synchronous signal and the row synchronous signal of the DVP signal.

Illustratively, the DVP signal data receiving module receives image data in an external DVP format, and receives DVP parallel data according to the effective polarity of the frame synchronization signal and the line synchronization signal obtained by the adaptive judgment. Optionally, after extracting the DVP signal data, the DVP data may be repackaged into MIPI data format and sent out of the module according to the received data bit width.

Optionally, the transmission channel of the third sensing signal is an LVDS signal channel. The step of identifying image data of the sensing signal may comprise:

serial-to-parallel processing is carried out on the third induction signal so as to obtain a second parallel data stream;

determining the frame head position of the LVDS signal according to the second parallel data stream;

extracting LVDS signal data fields in the second parallel data stream according to the frame head position;

and decoding according to the LVDS signal data field to obtain LVDS signal data.

Illustratively, the LVDS signal data receiving module receives image data in an external LVDS format, and converts a high-speed serial data stream into a parallel data stream through a serial-to-parallel procedure. The dummy may be detected in the parallel data stream, aided by an SAV (active video start, start of Active Video)/EAV (active video end, end of Active Video) signal, to determine the frame header position. Optionally, the data stream obtained by positioning is buffered for synchronizing data between different channels and decoding LVDS data therefrom.

Optionally, the step of evaluating the image sensor based on the image data comprises:

reading at least one of MIPI signal data, DVP signal data and LVDS signal data, and packaging the MIPI signal data into MIPI image data frames according to MIPI signal formats;

and sending the MIPI image data frame to an evaluation platform for evaluation.

Optionally, after extracting the image data such as the MIPI signal data, the DVP signal data, the LVDS signal data, and the like, the image data may be repackaged into the MIPI data format or other signal formats according to the received data bit width, and sent to the evaluation platform. Optionally, through adjustable output voltage, increase measuring current function, can carry out the verification of image algorithm, equally be favorable to the evaluation to image sensor, the power configuration interface is abundant, can satisfy the evaluation demand of various image sensors. Optionally, a programmable clock function may be added to provide various frequency clocks to the image sensor to meet more evaluation requirements.

Through multiplexing and unification of the multipath data interfaces, the universality of the image sensor system is realized, the evaluation of the image sensor can be conveniently carried out, and the user experience is improved.

Second embodiment

Fig. 2 is a block diagram of an image sensor evaluation adapting device according to an embodiment of the present application.

As shown in fig. 2, in an embodiment, the present application further provides an image sensor evaluation switching device, which includes a switching board 1, a first level conversion circuit 2, a second level conversion circuit 3, and a signal processing circuit 4.

The adapter plate 1 is used for acquiring induction signals of the image sensor, generating a first induction signal, a second induction signal and a third induction signal through the adapter plate 1, and splitting the first induction signal into a first level signal and a second level signal;

the first level conversion circuit 2 is connected with the adapter plate 1 and is used for generating a third level signal according to a first interface procedure of a signal receiving end of the first induction signal;

the second level conversion circuit 3 is connected with the adapter plate 1 and is used for generating a fourth level signal according to a second interface procedure of the signal receiving end of the second induction signal;

the signal processing circuit 4 is respectively connected with the adapter plate 1, the first level conversion circuit 2 and the second level conversion circuit 3, and can extract image data of the sensing signals according to the second level signal, the third level signal, the fourth level signal and the third sensing signal; and can send image data to an evaluation platform for evaluation of the image sensor.

For example, during evaluation, the image sensor sends data, the sensing signal is connected to the adapter board through the pin header, the multiple sensing signal data interfaces such as MIPI, LVDS, DVP are respectively plugged into the same adapter board through different interfaces, and then the data and the configuration signal are connected to the signal processing circuit board system through the high-speed connector (pin header) on the adapter board and the female socket (e.g. female header) on the signal processing circuit board. Illustratively, after the MIPI data signal is processed by the bridge chip, the HS signal and the LP signal can be separated, which are the main components of the MIPI signal. The input three paths of signals are respectively transmitted to the signal processing circuit for processing through the respective receiving modules. The three paths of signals are respectively provided with own transmission channels and do not interfere with each other in the board diagram of the circuit board, and the signal transmission quality is not affected.

Optionally, by splitting different components of the first sensing signal, further matching adjustment can be performed according to the interface electrical rule of the signal input end, so as to obtain a third level signal matched with the corresponding signal receiving end, and ensure the correctness of signal transmission. Optionally, further matching adjustment can be performed according to the interface electrical specification of the signal input end, and level adjustment is performed on the second sensing signal, so that a fourth level signal matched with the corresponding signal receiving end is obtained, and accuracy of signal transmission is guaranteed. Optionally, the second level signal, the third level signal, the fourth level signal and the third sensing signal are respectively received by the signal processing circuit, and are respectively subjected to effective data identification so as to extract image data. Regardless of the type of signal that the initial configuration of the image sensor is, the image data of the image sensor can be successfully identified through the above steps. After successfully identifying the image data of the image sensor, the performance of the image sensor can be evaluated according to the identified image data.

Through multiplexing and unification of the multipath data interfaces, the universality of the identification of the output signals of the image sensors can be realized, the evaluation of the image sensors is convenient, the trouble of repeated plugging configuration during the evaluation of different image sensors is avoided, and the evaluation requirements of various different types of image sensors can be met.

Fig. 3 is a schematic diagram illustrating connection between a signal processing circuit and an interposer according to an embodiment of the present application.

As shown in fig. 3, in the present embodiment, the signal processing circuit is described by taking an FPGA chip circuit as an example. In other embodiments, the signal processing circuit may be other circuits with signal processing capability, which is not limited in this application. Optionally, the processing module based on the FPGA chip is composed of the FPGA chip, a JTAG interface (joint test working group, joint Test Action Group, for internal test of input and output signals) and a Flash memory Flash, so that data of the image sensor can be processed, configuration of the image sensor can be performed through I2C or SPI (serial peripheral interface ), and algorithm verification of the image sensor can also be performed.

Referring to fig. 3, alternatively, the first sensing signal is an MIPI signal, the second sensing signal is a DVP signal, and the third sensing signal is an LVDS signal; the signal processing circuit comprises an MIPI image data receiving module, an LVDS image data receiving module and a DVP image data receiving module;

The MIPI image data receiving module is used for receiving MIPI signal data of MIPI signals, the LVDS image data receiving module is used for receiving LVDS signal data of LVDS signals, and the DVP image data receiving module is used for receiving DVP signal data of DVP signals.

With continued reference to fig. 3, the main components of the MIPI signal are, illustratively, the HS signal and the LP signal. Optionally, the MIPI signal data is passed mainly through the patch panel to the bridge chip MC20901, and the HS signal and the LP signal are separated after chip processing. The HS signal level is lower, belongs to high-speed signals, and can be directly transmitted to an FPGA chip for processing. The LP signal depends on the Output IO (Input/Output) level of the MC20901, which may be 2.5V, and the IO level of the receiving end FPGA depends on the level of the driving and matching requirements (bank, the programmable Input/Output unit is abbreviated as I/O unit) of the FPGA receiving signal, which is an interface part between the chip and the external circuit, so as to complete the driving and matching requirements of the Input/Output signal under different electrical characteristics, so that when the levels are inconsistent, the level conversion process needs to be performed through the level conversion chip LSF 0108.

Fig. 4 is a circuit board wiring diagram of an image sensor evaluation switching device according to an embodiment of the present application.

Optionally, the specification of the MIPI trace, including signal interference, MIPI trace length, etc., may be noted in the circuit board trace (Layout), which trace is shown in fig. 4 to meet MIPI signal trace requirements.

Alternatively, the MIPI signal trace may be patterned as follows:

the differential line impedance control standard of MIPI is 100deg.C, and the error is not more than + -10%.

b. The right-angle wiring is avoided so as not to generate reflection and influence the high-speed transmission performance.

c. Reference layer: a reference layer (recommended stratum) is arranged below the MIPI signal line, and the continuity of the reference layer is ensured (namely, the reference layer below the MIPI signal line is not divided or has gaps and is not cut off by other wires), and the reference layer below the MIPI signal line can be wider than each side of the MIPI signal line by more than 4W (W is the width of the MIPI signal wires); preferably, there is a single piece of the formation.

d. Equal length: the length error between MIPI wire pairs is controlled within 10mil, and the length error between wire pairs is controlled within 100 mil; the equal length is to ensure that two differential signals arrive at the receiving end at the same time. When the wires are equal in length, the concentration of the coiled wires is not less than 4W according to the symmetry principle, the equal-length requirement can be met near the bonding pads, the wires are routed in a chamfer mode, and the fixed line width and the fixed line distance are kept.

e. Symmetry: the MIPI line pairs may be equally long and equidistant. The symmetry is to ensure the consistent wiring impedance and reduce reflection. Signal distortion is avoided, resulting in instability or shadowless phenomena.

f. Away from interference: the distance between the MIPI line pairs can be at least 2W, the MIPI line pairs can be far away from other high-speed signals (parallel data lines, clock lines and the like), the distance above 3W is kept, and the MIPI line pairs are not parallel. The source of the switching power supply should be kept away to avoid interference.

g. And (3) through hole: the MIPI signal wire can be free of through holes, if the MIPI signal wire is provided with through holes, two wires on the wire pair can exist, symmetry can be kept, and after the signal wire is replaced, the reference layer can be perforated and replaced at the position of the through holes close to the signal wire. If 1Lane data or clock line pair has a via, then all other data or clock line pairs may be punched with vias to ensure consistent delay.

Optionally, the signal processing circuit may further include:

and the I2C module is used for evaluating the communication between the platform and the signal processing circuit so as to configure the signal processing circuit.

Illustratively, communication is realized between the FPGA and the upper computer of the evaluation platform through an I2C protocol, and configuration of parameters related to the FPGA processing module, such as an image size parameter, a PWM (pulse width modulation ) parameter, and an image processing enabling parameter, is completed.

Optionally, the signal processing circuit may further include:

and the system clock module is used for generating a clock with a corresponding frequency for the signal processing circuit to use.

Illustratively, the system clock module may generate clocks of different frequencies (25 MHz,50MHz,100MHz,200MHz,300 MHz) for internal processing by the FPGA.

Optionally, the signal processing circuit may further include:

the sensor clock configuration module is used for providing corresponding clock signals for the image sensor to evaluate according to the configuration of the upper computer.

Optionally, the additionally configured image sensor clock configuration module provides clocks with selectable frequencies (6 MHz,7MHz,8MHz,9MHz,12MHz,24MHz,25MHz,27MHz and 37.125 MHz) according to the configuration of the upper computer of the evaluation platform, and outputs the clocks to the FPGA for supplying the image sensor.

Optionally, the signal processing circuit may further include:

and the PWM module is used for generating a frame synchronous signal so as to trigger the image sensor.

Illustratively, the PWM module may generate a frame synchronization signal EFSYNC with an adjustable frequency (0.1 MHz-150 MHz) and an adjustable duty cycle (0% -100%) to be output to the outside of the FPGA to trigger the image sensor.

Optionally, the signal processing circuit may further include:

And the data caching module is used for caching the image data.

Fig. 5 is a schematic diagram of a read-write cache structure according to an embodiment of the present application.

Referring to fig. 5, optionally, the data buffer module buffers the received image data in DDR3 for subsequent processing by MIG IP (Memory Interface Generator). DDR3 is divided into 16 buffer pools, each buffer pool size being the size of 1 frame image.

Optionally, in order to improve the buffering efficiency and the cross-clock domain processing, before the image data is rewritten into DDR3, the image data is buffered in an asynchronous FIFO (first-in first-out storage, first In First Out, asynchronous is controlled by different clock signals respectively, when a signal is sent, a signal or an identifier that needs to be received by a given receiving end is needed, when the data amount in the FIFO reaches 16 lines, the 16 data is written into DDR3 at a time in a burst transmission mode, and the same is true for the read operation.

Optionally, in order to prevent the problem of DDR3 (Double-Data-Rate Three SRAM) read/write collision, a read/write judgment is present inside the module, so that DDR3 is prevented from simultaneously reading and writing to the same buffer pool, where DDR3 write operation priority is higher than read operation, i.e. read operation is completed during idle write operation.

Optionally, the signal processing circuit may further include:

and the algorithm processing module is used for sequentially reading the image data according to the frames and carrying out preset image algorithm processing.

The algorithm processing module reads the image data buffered in the DDR3 in sequence according to the frames, performs related image algorithm processing, improves algorithm processing efficiency, and transmits the processed data to the next module.

Optionally, the signal processing circuit may further include:

and the USB module is used for integrating the time sequence of the image data so as to send the image data according to frames.

Illustratively, the FPGA sends the image data to FX3 (USB 3.0 chip, for example, CYUSB 3014) via GPIF II ([ second generation ] universal programmable interface, general Programmable Interface II, which can be set to an 8/16/32bit configuration, so there are 32 parallel interfaces) via 32 parallel interfaces, and then FX3 sends each frame of image data to the PC according to USB3.0 protocol integration timing.

Optionally, the signal processing circuit may further include:

and the data transmitting module is used for decoding the image data and packaging the image data into MIPI image data frames according to the MIPI signal format so as to transmit the image data.

The data transmitting module receives the image data from the algorithm processing module, decodes the image data, adds the short packet field and the synchronization code, generates the corresponding LP double-ended signal, and outputs a parallel data stream conforming to a preset protocol specification to the parallel-to-serial program, thereby obtaining a serial data stream for transmission to the outside of the FPGA.

Optionally, the signal processing circuit may further include:

and the optical fiber module is used for packaging the image data in a standard UDP protocol so as to transmit the image data through an optical fiber.

Illustratively, the fiber optic module receives the image data from the algorithm processing module and packages the image data in a standard UDP protocol for transmission outside the FPGA through the tera ethernet interface.

Optionally, the signal processing circuit may further include:

the firmware upgrading module is used for receiving the upgrading file of the evaluation platform and performing CRC (cyclic redundancy check) on the upgrading file so as to upgrade the signal processing circuit.

Illustratively, when the code of the signal processing circuit is upgraded, the firmware upgrade module receives the firmware upgrade file from the host computer, intercepts the data stream from the USB3.0 module, and upgrades the firmware after CRC check.

Optionally, the image sensor evaluating and adapting device may further include:

and the I2C control module is respectively connected with the signal processing circuit and the image sensor, and is based on an I2C control link of the I2C module and used for respectively controlling I2C communication inside the signal processing circuit and I2C communication of the image sensor.

Fig. 6 is a schematic diagram illustrating connection of an I2C control module according to an embodiment of the present application.

Referring to fig. 6, an I2C control module is exemplarily based on an I2C control link of an FX3 chip, and mainly designs that the FX3 chip can control two I2C modules of an inner module and an outer module respectively through an I2C selection switch, so that I2C devices in an evaluation system all belong to the inner module, and can be encrypted when being used externally, and cannot access to I2C of devices in the evaluation system, thereby playing a role of protection. And an off-board module is reserved and is mainly connected to an image Sensor (Sensor) board end part in an evaluation system, wherein the off-board module comprises I2C of the image Sensor or I2C equipment matched with the image Sensor for use, such as EEPROM and the like.

The chip in the system can be protected through the I2C switching function, and meanwhile, the equipment number identification function of FX3 improves the safety of the system and effectively improves the performance of products.

Optionally, the image sensor evaluating and adapting device may further include:

and the storage module is connected with the signal processing circuit and used for storing the image data.

For example, the memory module may be composed of a DDR3 chip to securely store and read and write image data.

Optionally, the image sensor evaluating and adapting device may further include:

and the programmable clock module is connected with the signal processing circuit and used for providing corresponding clock signals for the image sensor under the control of the signal processing circuit.

Illustratively, the clock signal of the common frequency may be provided by the FPGA, but with lower precision and resources, so the system only provides the clock frequency of 6m 12m 24m 27m or the like which is relatively common. In addition, the high-precision adjustable clock frequency is composed of clock chips LMK61E2-SIAT, and a programmable clock oscillator can be provided through I2C control, so that the module can provide the most suitable programmable and controllable clock signal for the image sensor, and FPGA resources are saved while the precision is high.

The programmable clock module provides the clock frequency with higher precision for the image sensor, meanwhile, clock processing resources of the FPGA are saved, the FPGA provides the common clock frequency to realize proper programmable controllable clock signals with precision assurance, and user experience is improved.

Optionally, the image sensor evaluating and adapting device may further include:

and the power supply module is used for providing working power supply.

Optionally, the power supply module includes a system power supply module and a programmable power supply module:

the system power supply module comprises a PMIC and a DCDC power supply chip and is used for providing system power supply;

the programmable power module is connected with the system power module and comprises a linear stabilized voltage power supply, an ADC chip, a DAC chip and a current measuring chip, and is used for providing a programmable power supply for the image sensor.

The system power module is illustratively composed of a PMIC (integrated power management circuit, power Management Integrated Circuit), a DCDC (Direct Current/Direct Current for high-low voltage Direct Current conversion) power chip, and a linear regulated power supply, and mainly provides system power. The whole system is powered by a 12V power adapter, is turned to 5V through a DCDC power chip of RT6219 (power management circuit), and provides power required by systems of 3.3V,1.8V,1.5V,1.2V,1.0V and the like through a PMIC of a buck converter TPS 65251. Wherein the power supplied to the Sensor is specifically split to a 5V power supply for the programmable power module.

The programmable power supply module consists of a linear stabilized voltage power supply, an ADC chip, a DAC chip, a current measurement chip and a related resistance network, and is mainly used for providing the programmable power supply for the image sensor. In the prior art, the image sensor is divided into three power supplies, namely an analog power supply, a digital power supply and an IO power supply. Wherein the voltage of the analog power supply ranges from 2.8V to 3.3V, the voltage of the digital power supply ranges from 0.9V to 1.8V, and the voltage of the IO power supply ranges from 1.8V to 3.3V.

The adjustable and high-precision power supply voltage is used, the power supply configuration interface is rich, the requirements of different types of image sensors can be met, the functions of voltage adjustment and current measurement can be realized by measuring current through the programmable power supply module, and the power supply requirements of different types of image sensors can be met.

Optionally, the image sensor evaluating and adapting device may further include:

the data output module is connected with the signal processing circuit and used for receiving and transmitting data between the signal processing circuit and the evaluation platform.

Through the data sending module, the requirement of sending data under different conditions of a user is met, and user experience is improved.

Optionally, the data output module includes at least one of a USB data output module, a fiber optic SFP data output module, and a data transmission module.

Optionally, the USB data output module may include an FX3 chip, an EEPROM chip, and a FLASH chip, connected between the evaluation platform and the signal processing circuit, where the FX3 chip is connected to the EEPROM chip through an I2C signal, and the FX3 chip is connected to the FLASH chip through an SPI signal, and the FX3 chip is connected to the signal processing circuit through an I2C signal.

Illustratively, the USB data output module may be composed of an FX3 chip, an EEPROM (electrically erasable programmable read Only memory ) chip, a FLASH chip, and may control, receive and output data to a PC via I2C communication. The FX3 chip CYUSB3014-BZXI is used for transmitting main data to the FPGA, and meanwhile, the main data can be connected to an EEPROM chip CAT24AA02TDI-GT3 through an I2C signal for storage, or connected to a FLASH chip W25Q64DVSSIG through an SPI signal for storage. The whole system can read and write the register through I2C. Meanwhile, the FX3 chip can read the internal equipment number, if the equipment number is in the stock range, the functions are normally realized, and other conditions can prohibit the use of the functions so as to protect the equipment and improve the safety of the whole system.

Optionally, the optical fiber SFP data output module may include an SFP interface conversion chip and an ESD protection tube connected to each other, for converting the image data sent by the signal processing circuit into an optical signal for sending to the evaluation platform.

The optical fiber SFP data output module can be composed of an SFP interface conversion chip, a matched resistor network and an ESD protection tube. Through the mutual conversion of the optical signal and the high-speed signal, the TX RX data processed in the high-speed bank of the FPGA is connected with the optical signal, so that the high-speed transmission of the data is realized. Meanwhile, besides the sending and receiving signals of high-speed data, the configuration signals are connected to corresponding BANK in the FPGA to perform configuration, and meanwhile, ESD protection measures can be added to protect the whole interface. The optical fiber SFP data output module can provide input and output of high-speed data, the optical fiber interface has a very high interface speed upper limit, and can meet the data transmission of large data volume, thereby effectively improving the product performance.

Alternatively, the data transmission module may include a bridge chip and a third level conversion circuit.

The bridge chip is connected with the signal processing circuit through the level conversion chip and is used for combining the image data after the level conversion into MIPI signals to be sent to the evaluation platform. The third level conversion circuit is used for converting the level of the MIPI signal so as to adapt to the interface specification of the receiving end of the MIPI signal.

Optionally, after extracting the image data such as the MIPI signal data, the DVP signal data, the LVDS signal data, and the like, the image data may be repackaged into the MIPI data format or other signal formats according to the received data bit width, and sent to the evaluation platform. The miptx data transmission module receives image data from the algorithm processing module, decodes the image data, adds a short packet field and a sync code, generates a corresponding LP double-ended signal, and outputs a parallel data stream conforming to MIPI protocol specifications to a parallel-to-serial IP, thereby obtaining a serial data stream, and transmits the serial data stream to the outside of the FPGA.

For example, the MIPI image data transmitting module may be composed of a MIPI interface, an FPGA bridge chip, and a level conversion chip, and is used for level conversion and transmission of MIPI image data, and the image data may be transmitted by a MIPI TX (Transmit) data transmitting module of the FPGA. Alternatively, the MIPI data may be sent to the bridge chip MC 20202 through the FPGA, and the chip processes the MIPI data to combine the HS signal and the LP signal, which are the main components of the MIPI signal, and send the MIPI signal to the TX connector. If the levels of the MIPI signal transceiver terminals are not consistent, a third level shifting circuit can be used for level shifting.

Through multiplexing and unification of the multipath data interfaces, the universality of the image sensor system is realized, the evaluation of the image sensor can be conveniently carried out, and the user experience is improved.

Third embodiment

FIG. 7 is a block diagram of an image sensor evaluation system according to an embodiment of the present application.

Referring to fig. 7, the present application further provides an image sensor evaluation system, which includes an image sensor, an evaluation platform, and an image sensor evaluation switching device as described above.

The image Sensor is connected with a computer PC of the evaluation platform through the image Sensor evaluation switching device, so that the evaluation platform evaluates the image Sensor through the image Sensor evaluation switching device.

FIG. 8 is a flowchart illustrating the operation of an image sensor evaluation system according to an embodiment of the present application.

Referring to fig. 8, in one embodiment, the image Sensor evaluation system mainly uses the hardware system, and an image Sensor board card, a 12V power adapter, a USB cable and a PC equipped with an evaluation platform driver are required to be evaluated. Firstly, a 12V power adapter is inserted to supply power to the whole hardware system, a USB line is connected with a PC, and a Sensor board card to be evaluated is installed. After the hardware is connected, the system is powered on, at the moment, the computer can display USB interface drive, corresponding software can be opened after the required drive is installed, and the sensor image can be displayed on the computer by clicking and running Play. The image Sensor evaluation system can also read and write the Sensor register of the image Sensor through I2C to verify various functions of the Sensor for image evaluation. And after the evaluation is finished, the power-down and power-up are performed again for drawing, or the Sensor board card is replaced for evaluating other image sensors.

Fourth embodiment

The present application also provides a storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the image sensor evaluation adapting method as described above.

The technical details involved in the step of realizing the method for evaluating and switching the image sensor on the market by the computer program are the same as those of the above embodiments, and reference is made to the above embodiments.

In summary, the image sensor evaluating and switching method, the device, the evaluating system and the storage medium provided by the application realize multiplexing and unifying multiple data interfaces through the switching board, so that the universality of an image sensor system is realized, the image sensor evaluation is convenient to perform, the power supply voltage is adjustable, the accuracy is high, the current can meet the requirements of most image sensors, the current can be measured, the image algorithm can be verified, the evaluation of the image sensors is also facilitated, the power supply configuration interface is rich, the evaluating requirement of most image sensors on the market can be met, and the programmable clock module can provide various frequency clocks for the image sensors to meet the majority of evaluating requirements.

The foregoing description is only of the preferred embodiments of the present application, and is not intended to limit the scope of the claims, and all equivalent structures or equivalent processes using the descriptions and drawings of the present application, or direct or indirect application in other related technical fields are included in the scope of the claims of the present application.

Claims (7)

1. An image sensor evaluation switching device, characterized by comprising:

the adapter plate is used for acquiring induction signals of the image sensor, generating a first induction signal, a second induction signal and a third induction signal through the adapter plate, and splitting the first induction signal into a first level signal and a second level signal;

the first level conversion circuit is connected with the adapter plate and used for generating a third level signal according to a first interface procedure of the signal receiving end of the first induction signal;

the second level conversion circuit is connected with the adapter plate and used for generating a fourth level signal according to a second interface procedure of the signal receiving end of the second induction signal;

the signal processing circuit is respectively connected with the adapter plate, the first level conversion circuit and the second level conversion circuit and can extract image data of the induction signals according to the second level signal, the third level signal, the fourth level signal and the third induction signal; and the image data can be sent to an evaluation platform so as to evaluate the image sensor.

2. The image sensor evaluation switching device according to claim 1, wherein the first sensing signal is an MIPI signal, the second sensing signal is a DVP signal, and the third sensing signal is an LVDS signal; the signal processing circuit comprises an MIPI image data receiving module, an LVDS image data receiving module and a DVP image data receiving module;

The MIPI image data receiving module is used for receiving MIPI signal data of the MIPI signal, the LVDS image data receiving module is used for receiving LVDS signal data of the LVDS signal, and the DVP image data receiving module is used for receiving DVP signal data of the DVP signal.

3. The image sensor evaluation switching device of claim 1, wherein the signal processing circuit further comprises at least one of:

the I2C module is used for communication between the evaluation platform and the signal processing circuit so as to configure the signal processing circuit;

the system clock module is used for generating a clock with a corresponding frequency for the signal processing circuit to use;

the sensor clock configuration module is used for providing corresponding clock signals for the image sensor to evaluate according to the configuration of the upper computer;

a PWM module for generating a frame synchronization signal to trigger the image sensor;

the data caching module is used for caching the image data;

the algorithm processing module is used for sequentially reading the image data according to frames and carrying out preset image algorithm processing;

the USB module is used for integrating the time sequence of the image data so as to send the image data according to frames;

The data transmitting module is used for decoding the image data, and packaging the image data into MIPI image data frames according to a MIPI signal format so as to transmit the image data;

the optical fiber module is used for packaging the image data with a standard UDP protocol so as to be sent through an optical fiber;

and the firmware upgrading module is used for receiving the upgrading file of the evaluation platform and performing CRC (cyclic redundancy check) on the upgrading file so as to upgrade the signal processing circuit.

4. The image sensor evaluation switching device of any one of claims 1-3, further comprising at least one of:

the I2C control module is respectively connected with the signal processing circuit and the image sensor and is used for respectively controlling I2C communication inside the signal processing circuit and I2C communication of the image sensor based on an I2C control link;

the storage module is connected with the signal processing circuit and used for storing the image data;

the programmable clock module is connected with the signal processing circuit and used for providing corresponding clock signals for the image sensor under the control of the signal processing circuit;

the power module is used for providing a working power supply;

And the data output module is connected with the signal processing circuit and is used for receiving and transmitting data between the signal processing circuit and the evaluation platform.

5. The image sensor evaluation switching device of claim 4, wherein the power supply module comprises a system power supply module and a programmable power supply module:

the system power supply module is used for providing a system power supply; the programmable power module is connected with the system power module and is used for providing programmable power for the image sensor.

6. The image sensor evaluation switching device of claim 4, wherein the data output module comprises at least one of a USB data output module, a fiber optic SFP data output module, and a data transmission module:

the USB data output module comprises an FX3 chip, an EEPROM chip and a FLASH chip, which are connected between the evaluation platform and the signal processing circuit, wherein the FX3 chip is connected with the EEPROM chip through an I2C signal, the FX3 chip is connected with the FLASH chip through an SPI signal, and the FX3 chip is connected with the signal processing circuit through an I2C signal;

the optical fiber SFP data output module comprises an SFP interface conversion chip and an ESD protection tube which are connected with each other, and is used for converting the image data sent by the signal processing circuit into optical signals to be sent to the evaluation platform;

The data transmitting module comprises a bridge chip and a third level converting circuit;

the bridge chip is connected with the signal processing circuit through the third level conversion circuit and is used for combining the image data subjected to level conversion into MIPI signals so as to send the MIPI signals to the evaluation platform;

the third level conversion circuit is used for converting the level of the MIPI signal so as to adapt to the interface specification of the MIPI signal receiving end.

7. An evaluation system comprising an image sensor, an evaluation platform and an image sensor evaluation adapter according to any one of claims 1-6, wherein the image sensor and the evaluation platform are connected by the image sensor evaluation adapter such that the evaluation platform evaluates the image sensor by the image sensor evaluation adapter.

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