CN219203110U - DC bias voltage detection device - Google Patents

Abstract

The present disclosure relates to semiconductor manufacturing technology, and in particular, to a dc bias voltage detection device. The wafer substrate comprises a bonded lower wafer and an upper wafer, wherein the lower wafer is provided with an energy supply cavity and a plurality of detection cavities, and the detection cavities and the upper wafer form a plurality of closed wafer grids; the voltage detection module is arranged in the detection cavity; the energy supply module is arranged in the energy supply cavity and is electrically connected with the voltage detection module; wherein, the contact part of the upper wafer and the lower wafer is provided with a silicon oxide layer; the upper wafer surrounds the outer edge of the detection cavity and is provided with a spacing gap, and the spacing gap penetrates through the upper wafer to the silicon oxide layer. According to the direct current bias voltage detection device, through the bonded upper wafer and lower wafer, the direct current bias voltage detection device can adapt to a vacuum environment and an ion environment, and voltage detection at an accurate position in a vacuum chamber is achieved.

Description

DC bias voltage detection device

Technical Field

The present disclosure relates to semiconductor manufacturing technology, and in particular, to a dc bias voltage detection device.

Background

Electrostatic discharge (ESD el electro-Stat ic d i scharge) is a common cause of failure in current wafer manufacturing processes.

At present, the process of generating static electricity in the production process is mainly in the etching (etching) stage, and during the etching process, the etching cavity radio frequency generates plasma and acts on the wafer to generate direct current bias voltage (Vdc). The DC bias voltage can reach 8000V, and the excessive voltage can cause abnormal discharge of the wafer, generate ESD failure and even cause wafer explosion.

However, the prior art lacks suitable measurement methods to simulate and detect the electrostatic condition of the etching process. In practical production, the etching process, i.e. the potential in the plasma environment, is mainly tested by using a pull-down probe. And extending the external probe into the cavity to detect the potentials at different positions on the wafer. However, the external lead leads damage the electric field in the plasma chamber, and the reference of the measured value is greatly reduced.

Disclosure of Invention

In order to solve the problems that the prior art cannot adapt to vacuum environment and ion environment and cannot detect specific point voltage due to insufficient precision, the application provides a direct current bias voltage detection device, which comprises

The wafer substrate comprises a bonded lower wafer and an upper wafer, wherein the lower wafer is provided with an energy supply cavity and a plurality of detection cavities, and the detection cavities and the upper wafer form a plurality of closed wafer grids;

the voltage detection module is arranged inside the detection cavity;

the energy supply module is arranged in the energy supply cavity and is electrically connected with the voltage detection module;

wherein, the contact part of the upper wafer and the lower wafer is provided with a silicon oxide layer; the upper wafer surrounds the outer edge of the detection cavity, and a spacing gap is formed, and penetrates through the upper wafer to the silicon oxide layer.

In one embodiment, the spacer void is filled with a silicon oxide isolation layer.

In one embodiment, a metal oxide layer is disposed on the surface of the silicon oxide isolation layer.

In an embodiment, the material of the metal oxide layer is any one of silicon oxide, silicon nitride, aluminum oxide or yttrium oxide.

In an embodiment, the lower wafer surface is provided with a conductive line from the energy supply cavity to the voltage detection module, and the energy supply module is electrically connected with the voltage detection module through the conductive line.

In one embodiment, the wafer cells are distributed or closely arranged.

In one embodiment, the material of the lower wafer and the upper wafer is silicon wafer.

In one embodiment, the voltage detection module includes a voltage detection unit, a storage control unit, and a wireless transmission unit; the energy supply module comprises a storage battery and a wireless energy charging unit;

the voltage detection unit detects the potential difference between the upper wafer and the lower wafer; the storage control unit records the data measured by the voltage detection unit; the wireless transmission unit transmits the data recorded by the storage control unit to the outside; the wireless energy charging unit wirelessly transmits external electric energy to the storage battery, and the storage battery supplies energy for the voltage detection module.

In one embodiment, the detection cavity is filled with an insulating resin layer.

Based on the above, compared with the prior art, the beneficial effects of the application are as follows:

1. the direct current bias voltage detection device provided by the application is characterized in that the wafer lattice is arranged inside the wafer, the voltage detection module is arranged inside the wafer lattice, and the whole voltage detection device is sealed, so that an external lead is not required in the whole voltage detection process, and the problem that the lead damages the whole electric field is avoided.

2. The direct current bias voltage detection device provided by the application makes the wafer grids isolated from each other through the interval gap, so that the voltage detection module can independently detect the up-down potential difference at the corresponding wafer grid, and the direct current bias voltage detection device can accurately detect the voltages at different positions in the ion cavity.

3. According to the direct current bias voltage detection device, through the bonded upper wafer and lower wafer, the direct current bias voltage detection device can adapt to a vacuum environment and an ion body environment, and expands a target environment to the technical processes of etching, PECVD, PVD, ion implantation, electron beam detection and the like, so that voltage detection at the accurate position in a vacuum chamber is realized.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. The objectives and other advantages of the application will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

For a clearer description of embodiments of the present application or of the solutions of the prior art, the following description will briefly introduce a brief description of the drawings that are needed in the embodiments or description of the prior art, it being obvious that, in the following description, the drawings are some embodiments of the present application, and that, without the need for inventive efforts, other drawings may be obtained from these drawings; the positional relationships described in the drawings in the following description are based on the orientation of the elements shown in the drawings unless otherwise specified.

FIG. 1 is a top view of a lower wafer in an embodiment of a DC bias voltage detection apparatus provided herein;

fig. 2 is a top view of another arrangement of wafers in accordance with an embodiment of the present application.

Fig. 3 is a top view of another arrangement of wafers in accordance with an embodiment of the present application.

Fig. 4 is a cross-sectional view of a single wafer cell in an embodiment of the present application.

Fig. 5 is a cross-sectional view of an embodiment of a wafer lattice provided with a silicon oxide isolation layer according to the present application.

Fig. 6 is a cross-sectional view of an embodiment of a wafer lattice provided with a metal oxide layer according to the present application.

FIG. 7 is a cross-sectional view of an energizing cavity in an embodiment of the present application.

Reference numerals:

wafer 111 silicon oxide layer on 100 wafer substrate 110

112 gap 113 silicon oxide isolation layer 114 metal oxide layer

120 lower wafer 121 inspection cavity 122 energy supply cavity

130 voltage detection module 140 energy supply module

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments; technical features designed in different embodiments of the present application described below may be combined with each other as long as they do not collide with each other; all other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

In the description of the present application, it should be noted that all terms (including technical terms and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs and are not to be construed as limiting the application; it will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In practice, as shown in fig. 1 to 4, a dc bias voltage detection apparatus includes a wafer substrate 100, a voltage detection module 130, and an energy supply module 140.

The wafer substrate 100 includes a bonded lower wafer 120 and an upper wafer 110, the lower wafer 120 is provided with an energy supply cavity 122 and a plurality of detection cavities 121, and the detection cavities 121 and the upper wafer 110 form a plurality of closed wafer grids. Specifically, after the lower wafer 120 is bonded to the upper wafer 110, the energy supply cavity 122 and the detection cavity 121 are not in contact with the outside, so that the working processes in the energy supply cavity 122 and the detection cavity 121 cannot be affected by the outside environment.

The voltage detection module 130 is disposed inside the detection cavity 121; the energy supply module 140 is disposed inside the energy supply cavity 122, and the energy supply module 140 is electrically connected with the voltage detection module 130. Specifically, the voltage detection module 130 detects the potential difference between the upper wafer 110 and the lower wafer 120 at the corresponding wafer cell. Specifically, the sizes of the detection cavity 121 and the power supply cavity 122 may be adjusted according to the size of the voltage detection module 130 or the power supply module 140.

Wherein, the contact part of the upper wafer 110 and the lower wafer 120 is provided with a silicon oxide layer 111; the upper wafer 110 is provided with a spacing gap 112 around the outer edge of the detection cavity 121, and the spacing gap 112 penetrates through the upper wafer 110 to the silicon oxide layer 111; the voltage detection module 130 is disposed inside the detection cavity 121.

Specifically, the arrangement of the silicon oxide layer 111 and the spacing gaps 112 enables the upper wafer 110 corresponding to a single wafer lattice to form a potential island more integrally, so that the voltage detection module 130 correspondingly arranged with the upper wafer 110 can detect the potential at the corresponding position,

in the practical use process, the wafer substrate 100 is integrated after the upper wafer 110 and the lower wafer 120 are bonded, and factors such as vacuum, plasma in the environment can not affect the internal structure of the wafer substrate 100, so that the device is not affected by the equipment environment. During the detection, the energy supply module 140 supplies energy to the voltage detection module 130, the voltage detection module 130 detects and records the potential difference between the upper wafer 110 and the lower wafer 120 at the corresponding wafer lattice, and meanwhile, due to the existence of the gap 112 and the silicon oxide layer 111, the detected potential of the upper wafer 110 is the potential of the corresponding area, but not the whole potential.

Specifically, the silicon oxide layer 111 is formed by oxidizing the upper wafer 110 and etching and removing the area not contacted with the lower wafer 120, that is, etching a conductive surface corresponding to the detection cavity 121 after oxidizing the upper wafer 110, and completely exposing the surface of the upper wafer 110 not contacted with the lower wafer 120.

Preferably, as shown in fig. 1 to 3, the energy supply cavity 122 may be disposed at the center or the edge of the lower wafer 120, so long as the detection of the detection cavity 121 is not affected, and those skilled in the art may select according to practical situations. Further, a standby energy supply module 140 can be disposed in the energy supply cavity 122, so that temporary energy supply can be performed when the energy supply module 140 fails, and meanwhile, whether the failure occurs in the energy supply module 140 can be rapidly judged, so that subsequent maintenance work is facilitated.

In one embodiment, as shown in fig. 5, the spacer 112 is filled with a silicon oxide isolation layer 113. The gap 112 reduces the overall strength of the upper wafer 110, and may cause the upper wafer 110 to break under stress, thereby resulting in overall device damage. Therefore, the silicon oxide isolation layer 113 is filled in the space 112, and the overall strength is supplemented under the condition that the upper wafer 110 corresponding to the wafer lattice is ensured to be a potential island. And the upper wafer 110 can be formed again into a whole, so that the stress is uniformly transmitted, and the problem of breakage caused by overlarge local stress is prevented.

Preferably, as shown in fig. 6, the surface of the silicon oxide isolation layer 113 is provided with a metal oxide layer 114. The arrangement of the metal oxide layer 114 can further protect the silicon oxide isolation layer 113, effectively reduce the etching of the silicon oxide isolation layer 113 by plasma, protect the internal result of the device and prolong the service life of the device.

Preferably, the material of the metal oxide layer 114 is any one of silicon oxide, silicon nitride, aluminum oxide, or yttrium oxide.

In one embodiment, the surface of the lower wafer 120 is provided with a conductive line from the power cavity 122 to the voltage detection module 130, and the power module 140 is electrically connected to the voltage detection module 130 through the conductive line. Specifically, the conductive circuit can be obtained by filling conductive metal after etching the conductive path, and the arrangement of the conductive circuit makes the overall integration level of the device higher, so that more voltage detection modules 130 can be arranged.

In one embodiment, the wafer cells are distributed or closely arranged. As shown in fig. 1 to 3, the arrangement mode of the wafer grids can be distributed or compact, and the skilled person can adjust the arrangement mode according to actual requirements. Specifically, as shown in fig. 2 and 3, the wafer grid array is distributed on the wafer substrate 100, that is, the upper wafer 110 is separated by the spacing gaps 112 into independent areas, so that the cost can be reduced under the condition of meeting the data volume requirement in a distributed distribution manner. As shown in fig. 1, the wafer grids closely arranged are spaced only by the spacing gaps 112, and more wafer grids can be arranged in a unit area to obtain higher detection precision.

In one embodiment, the material of the lower wafer 120 and the upper wafer 110 is silicon.

Preferably, the detection cavity 121 is filled with an insulating resin layer. The insulating resin layer can further fix the voltage detection module 130 in the detection cavity 121, effectively preventing the occurrence of problems such as displacement, damage, etc. due to external force.

In one embodiment, the voltage detection module 130 includes a voltage detection unit, a storage control unit, and a wireless transmission unit; the energy supply module 140 comprises a storage battery and a wireless energy charging unit;

the voltage detecting unit detects a potential difference between the upper wafer 110 and the lower wafer 120; the storage control unit records the data measured by the voltage detection unit; the wireless transmission unit transmits the data recorded by the storage control unit to the outside; the wireless charging unit wirelessly transmits external power to the battery, which powers the voltage detection module 130.

In one embodiment, the wafer cassette further comprises an external box body, wherein the external box body is provided with a containing cavity for containing the wafer substrate 100; the external box is in communication with the voltage detection module 130. Specifically, the wireless charging device and the information reading device are integrated in the external box body, and the information reading device is in communication connection with the wireless transmission unit and is used for guiding out data in different forms. Prior to inspection, the wafer substrate 100 may be placed in the receiving cavity and the wireless charging device wirelessly transmits external electrical energy to the wireless charging unit to charge the battery. After the detection is finished, the information reading device is communicated with the wireless transmission unit, data recorded in the storage control unit are exported and converted into different forms, and the information reading device is convenient for operators to read.

In addition, it will be appreciated by those skilled in the art that although many problems exist in the prior art, each embodiment or technical solution of the present application may be modified in only one or several respects, without necessarily simultaneously solving all of the technical problems listed in the prior art or the background. Those skilled in the art will understand that nothing in one claim should be taken as a limitation on that claim.

Although terms such as wafer substrate, upper wafer, silicon oxide layer, spacer void, silicon oxide isolation layer, metal oxide layer, lower wafer, detection cavity, powered cavity, voltage detection module, powered module, etc. are more used herein, the possibility of using other terms is not precluded. These terms are used merely for convenience in describing and explaining the essence of the present application; they are to be interpreted as any additional limitation that is not inconsistent with the spirit of the present application; the terms first, second and the like in the description and in the claims of the embodiments and in the above-described figures, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims (9)

1. A dc bias voltage detecting device, characterized in that: comprising

The wafer substrate comprises a bonded lower wafer and an upper wafer, wherein the lower wafer is provided with an energy supply cavity and a plurality of detection cavities, and the detection cavities and the upper wafer form a plurality of closed wafer grids;

the voltage detection module is arranged inside the detection cavity;

the energy supply module is arranged in the energy supply cavity and is electrically connected with the voltage detection module;

wherein, the contact part of the upper wafer and the lower wafer is provided with a silicon oxide layer; the upper wafer surrounds the outer edge of the detection cavity, and a spacing gap is formed, and penetrates through the upper wafer to the silicon oxide layer.

2. The direct current bias voltage detecting device according to claim 1, wherein: and the interval gap is filled with a silicon oxide isolation layer.

3. The direct current bias voltage detecting device according to claim 2, wherein: the surface of the silicon oxide isolation layer is provided with a metal oxide layer.

4. A dc bias voltage detecting apparatus according to claim 3, wherein: the metal oxide layer is made of any one of silicon oxide, silicon nitride, aluminum oxide or yttrium oxide.

5. The direct current bias voltage detecting device according to claim 1, wherein: the lower wafer surface is provided with a conductive circuit from the energy supply cavity to the voltage detection module, and the energy supply module is electrically connected with the voltage detection module through the conductive circuit.

6. The direct current bias voltage detecting device according to claim 1, wherein: the wafer grids are distributed or closely distributed.

7. The direct current bias voltage detecting device according to claim 1, wherein: the lower wafer and the upper wafer are made of silicon wafers.

8. The direct current bias voltage detecting device according to claim 1, wherein: the voltage detection module comprises a voltage detection unit, a storage control unit and a wireless transmission unit; the energy supply module comprises a storage battery and a wireless energy charging unit;

the voltage detection unit detects the potential difference between the upper wafer and the lower wafer; the storage control unit records the data measured by the voltage detection unit; the wireless transmission unit transmits the data recorded by the storage control unit to the outside; the wireless energy charging unit wirelessly transmits external electric energy to the storage battery, and the storage battery supplies energy for the voltage detection module.

9. The direct current bias voltage detecting device according to claim 1, wherein: and an insulating resin layer is filled in the detection cavity.

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