CN218298521U - Radar system for measurement - Google Patents

Abstract

The application discloses a radar system for measurement, it contains: a printed circuit board, and the following hardware parts arranged on the printed circuit board: a first chip configured with a first antenna array; the second chip is provided with a second antenna array and is connected with the first chip; the first antenna array and the second antenna array are positioned in an antenna area of the printed circuit board; the signal converter is connected with the first chip or the second chip and used for converting the level signal output by the first chip or the second chip to output an intermediate signal, and the level range of the intermediate signal is lower than the level threshold of signal interference among printed circuit board lines; and the interface adapter is connected with the signal converter and is used for processing the intermediate signal output by the signal converter into a data format adaptive to an external circuit. The radar device simplifies the system component composition in the radar device, effectively reduces the size of the radar device, saves the resource cost and is more convenient to use.

Description

Radar system for measurement

The present application claims priority from chinese patent application entitled "radar system for measurement" filed by chinese patent office on 28/12/2021 with application number 202111628509.7, the entire contents of which are incorporated herein by reference.

Technical Field

The embodiment of the application relates to the overall circuit layout of a sensor, in particular to a radar system for measurement.

Background

A radar system for measurement is generally a sensor that detects an obstacle in a surrounding environment using a transmitted electromagnetic wave, such as a millimeter wave radar, and measures a physical quantity between the sensor and the obstacle using an echo reflected by the obstacle.

The radar system is a systematized product with multi-device integration. Radar systems have many challenges in terms of signal transmission, signal interference, and overall size of multiple devices.

Disclosure of Invention

Based on the above technical problem, the present application provides a radar system for measurement, which is used to solve the optimization problem of how to improve the transmission of data signals of a MIMO antenna radar chip among multiple devices.

The present application provides a radar system for measurement, comprising: a printed circuit board, and the following hardware parts arranged on the printed circuit board: a first chip configured with a first antenna array; the second chip is provided with a second antenna array and is connected with the first chip; wherein the first antenna array and the second antenna array are located in an antenna area of the printed circuit board; the first antenna array is used for transmitting an exploration signal wave, and the first antenna array and/or the second antenna array are used for receiving an echo signal wave corresponding to the exploration signal wave; the signal converter is connected with the first chip or the second chip and used for converting the level signal output by the first chip or the second chip to output an intermediate signal, and the level range of the intermediate signal is lower than the level threshold of signal interference among the circuits of the printed circuit board; and the interface adapter is connected with the signal converter and is used for processing the intermediate signal output by the signal converter into a data format adaptive to an external circuit.

In some examples, the first antenna array includes a transmit antenna array and the second antenna array includes a receive antenna array; or the first antenna array comprises a transmitting antenna array and a first receiving antenna array, and the second antenna array comprises a second receiving antenna array, wherein the first receiving antenna array and/or the second receiving antenna array receive the echo signal wave.

In some examples, the transmit antenna array comprises at least one transmit antenna; the first antenna array and the second antenna array each comprise at least one receiving antenna.

In some examples, the radiation structures of the antennas in the first antenna array and the second antenna array are spaced according to the wavelength of the millimeter wave; the radiating structure is pasted on the surface of the printed circuit board.

In some examples, the local oscillator signal output terminal of the first chip or the second chip is respectively connected to the local oscillator signal input terminal of the first chip and the local oscillator signal input terminal of the second chip.

In some examples, the interface adapter includes: at least one of a Board Connector interface, a PCI interface, a CAN interface, a UART interface, and a JTAG interface.

In some examples, the first chip, the first antenna array, the second chip, and the second antenna array are all disposed on a front side of the printed circuit board.

In some examples, the interface of the interface adapter is disposed on a back side and/or a side edge region of the printed circuit board.

In certain examples, the external circuit includes at least one of: the device comprises a test instrument, an upper computer and a communication module.

In some examples, the radar system further comprises: the clock signal source is connected with the first chip or the second chip; the first chip or the second chip connected with the clock signal source generates a local oscillation signal based on the clock signal generated by the clock signal source, and transmits the local oscillation signal to the second chip or the first chip which is not connected with the clock signal source, so that the local oscillation signal can be synchronously used for: the first chip controls to transmit the detection signal wave, and the first chip and/or the second chip controls to receive the echo signal wave.

Above-mentioned radar system, cascade main chip and follow chip, be main chip and follow chip power supply through same power, realize main chip and follow chip and external communication connection through first connector, make only need a radar antenna circuit board can realize the work of two radar chips, follow-up also only need a data acquisition circuit to the collection of the radar signal data of main and slave chip, thereby system components among the radar device has been simplified and the size of radar device has effectively been reduced, the resource cost has been practiced thrift, it is also more convenient in the use.

Drawings

FIG. 1 is a block diagram of a radar antenna circuit in accordance with one embodiment;

FIG. 2 is a schematic diagram of a radar antenna circuit according to an embodiment;

FIG. 3 is a schematic diagram of a radar antenna circuit according to another embodiment;

FIG. 4 is a block diagram of a radar apparatus according to an embodiment;

FIG. 5 is a schematic diagram of a data acquisition circuit according to an embodiment.

Detailed Description

The present application will be described in further detail with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be further noted that, for the convenience of description, only some of the structures related to the present application are shown in the drawings, not all of the structures.

The radar system adopts a printed circuit board to organize various devices into a circuit structure capable of stably operating. The printed circuit board utilizes a multi-layer board structure composed of conductive and insulating materials, which includes thin conductive lines, holes, and the like. The spacing between the thin wires and the spacing, position, etc. of the holes on the printed circuit board are related to the signals transmitted by the devices in the radar system, the influence between the signals, etc.

Therefore, the printed circuit board of the radar system arranges the positions of various devices on the printed circuit board according to the characteristics of high-frequency signals in the area where the chip and the antenna array are located, and the interference and the connection between electric signals output by the output end of the chip and various signals such as electric signals provided by a power circuit and electric signals required by a data interface.

The antenna array may be coordinated by multiple radar chips, depending on the measurement requirements of the radar system. Correspondingly, the number of devices connected to the chip in the radar system increases. This results in the printed circuit board not only requiring a concomitant adjustment of the circuit configuration, but also a corresponding increase in its size. These are disadvantageous for achieving the need for electronics to achieve a comprehensive match of radar systems in size and performance.

Therefore, the present application provides a radar system, which improves the integration level of a printed circuit board and optimizes the signal interference prevention when the printed circuit board transmits data signals by systematically integrating devices on the printed circuit board.

Referring to fig. 1, a block diagram of a radar antenna circuit (also called a radar system) in an embodiment is shown, and as shown in fig. 1, in an embodiment, a radar antenna circuit 100 includes an antenna 110, a first chip 130, a second chip 150, a first connector 170, and a power supply 190.

The first chip is configured with a first antenna array and the second chip is configured with a second antenna array. The first antenna array and the second antenna array respectively comprise at least one antenna, and the first antenna array and the second antenna array at least form a single-transmission multi-reception antenna array or a multi-transmission multi-reception antenna array.

For example, the first antenna array is configured with N transmit antennas, where N is a natural number. The second antenna array is configured with M receiving antennas, wherein M is a natural number larger than 1. As another example, the first antenna array is configured with N transmit antennas and M1 receive antennas, where N and M1 are natural numbers. The second antenna array is configured with M2 receiving antennas, where M2 is a natural number. For another example, the first antenna array is configured with N1 transmitting antennas and M1 receiving antennas, where N1 and M1 are natural numbers. The second antenna array is configured with N2 transmitting antennas and M2 receiving antennas, where N2 and M2 are natural numbers.

The radiating structures in the first antenna array and the second antenna array are located in the antenna area of the printed circuit board and are communicated with the free space in the form of a patterned metal layer. No signal lines other than the antenna array are disposed within the same layer of the patterned metal layer in the antenna area.

The first chip 130 and the second chip 150 are both radar chips. The first chip and the second chip can be chips with the same configuration; different configuration chips can be adopted according to the compatibility of the chips. The first chip 130 and the second chip 150 are connected in a cascade manner to meet the signal output requirements of a plurality of scalable chips. The printed circuit board may connect signal terminals of the first chip 130 and the second chip 150 at thin wires on the same metal layer as the antenna. The printed circuit board may also connect the signal terminals of the first chip 130 and the second chip 150 using wires and holes provided by the printed circuit board, thereby establishing transmission isolation between the signal terminals and the high frequency signals transmitted by the antenna array.

The first chip 130 (or the second chip 150) serves as a master chip, and the second chip 150 (or the first chip 130) serves as a slave chip. For example, the first chip 130 is a master chip, the second chip 150 is a slave chip, and the antenna 110 is connected to the master chip 150 and the slave chip 170, respectively. Wherein the cascading is accomplished through thin wires in a printed circuit board.

In order to facilitate signal transmission and cascade connection of the devices, the first chip, the first antenna array, the second chip and the second antenna array are all arranged on the front surface of the printed circuit board. For example, the signal pad a11 of the first chip 130 is connected to a pad of a hole of the uppermost layer on the printed circuit board, a thin wire connected to a certain layer of the middle of the printed circuit board through the hole, and another hole and its pad connected through the thin wire are connected to the signal pad a21 of the second chip 150 also located at the uppermost layer.

The master chip controls the signals generated by any one of the chips in the cascade. According to the arrangement rules of the transmitting antennas and the receiving antennas in the first antenna array and the second antenna array, the main chip is further configured to synchronize local oscillation signals of the transmitting antennas to the first chip and/or the second chip configured with the receiving antennas, so that baseband signals containing measurement information can be demodulated from echo signals output by the corresponding receiving antennas.

In order to realize synchronous transceiving of multiple chips, the first chip and the second chip realize signal synchronization through cascading. In some examples, the master chip (or slave chip) may be configured with a clock signal output terminal, and the slave chip (or master chip) may be configured with a clock signal input terminal, and then the two signal terminals are connected by using the printed circuit board, so as to realize that the first chip and the second chip perform signal transmission/signal reception based on the same clock signal.

In other examples, referring to fig. 3, a clock signal source (also called a crystal oscillator) 240 is also disposed on the printed circuit board. The clock signal source is connected with the first chip or the second chip; the first chip or the second chip connected with the clock signal source generates a local oscillation signal based on the clock signal generated by the clock signal source, and transmits the local oscillation signal to the second chip or the first chip which is not connected with the clock signal source, so that the local oscillation signal can synchronously cause: the first chip controls to transmit the detection signal wave, and the first chip and/or the second chip controls to receive the echo signal wave. In order to prevent the attenuation and interference of the clock signal during long-distance transmission, the clock signal source on the printed circuit board is in close proximity to the first chip or the second chip. As shown in fig. 3, the clock signal source 240 is located next to the first chip 230, which is a master chip. For example, the first chip, the first antenna array, the second chip, the second antenna array, and the clock signal source 240 are disposed on the front surface of the printed circuit board.

In order to optimize the electronics on the printed circuit board and to increase the capacity of the printed circuit board for accommodating a plurality of chips provided with antennas, a signal converter is also arranged on the printed circuit board. The signal converter is used for adjusting the level of the data signal output by the first chip or the second chip, thereby reducing the anti-interference interval between the signal lines on the printed circuit board.

The signal converter is connected to the first chip or the second chip, and is configured to convert the level signal output by the first chip or the second chip to output an intermediate signal, where a level range of the intermediate signal is lower than a level threshold of signal interference between lines of the printed circuit board.

The signal converter is connected with the first chip or the second chip for outputting the data signal. The first chip or the second chip may be a master chip or a slave chip. For example, under the control of the master chip, the first chip or the second chip, which is the slave chip, outputs the data signal. The data signal is obtained by the first chip and/or the second chip through signal processing according to the echo signal wave received by the receiving antenna. The data signal may be used to represent any of: data signals for describing measurement information (such as three-dimensional measurement point clouds, angle information, distance information, etc.); or to describe a data signal (e.g., a pseudorandom code, etc.) associated with the transmitted signal; or a synchronization signal (e.g., a clock signal, etc.) for describing synchronization of the cascaded chips, etc.

The signal converter may be parallel-to-serial conversion or serial-to-serial conversion, which generates an intermediate signal corresponding to the data signal by adjusting a voltage or a current of the data signal, according to an interface design of the first chip or the second chip to which the signal converter is connected. Examples of the signal converter include: LVDS interface, etc.

In some examples, the signal converter may be connected to other devices on the printed circuit board for further data processing of the measurement information described by the intermediate signal. Such as a connection processor, etc.

In still other examples, the radar system further includes an interface adapter coupled to the signal converter for processing the intermediate signal output by the signal converter into a data format adapted to an external circuit.

Here, the interface adapter may be connected to the signal converter on the pcb by using a longer thin wire, a thin wire arranged at a closer distance, or a thin wire arranged on the pcb in a non-coplanar (or coplanar) manner with the signal converter, so as to implement data connection between the pcb and an external circuit. The external circuit is used for receiving the measurement information output by the radar system. The external circuit can also send control instructions to the radar system to control the radar system to transmit data and/or collect data and the like. The external circuit includes at least one of: the device comprises a test instrument, an upper computer and a communication module. Wherein, the communication module includes: ethernet interface adapters, etc. The interface adapter includes: at least one of a Board Connector interface, a PCI interface, a CAN interface, a UART interface, and a JTAG interface.

Because the signal converter reduces the voltage of the data signal output by the chip, even the signal frequency and the like, the physical interval between metal media for transmitting signals in the printed circuit board is narrowed, and the size of the printed circuit board can not be obviously increased under the condition of properly increasing the cascade chips. In order to further not increase the size of the printed circuit board, i.e. the overall size of the radar system, the interface of the interface adapter can be arranged more flexibly in the rear and/or side edge region of the printed circuit board.

The at least one interface adapter and the signal converter may also be integrated in the same connector to further reduce the impact of interference between signal transmissions, or wiring, on the overall size of the radar system.

Based on the circuit structure principle provided by the above examples, the present application also provides some specific examples.

Taking the first chip 130 as a master chip and the second chip 150 as a slave chip as an example, please refer to fig. 1, the antenna 110 is connected to the master chip 150 and the slave chip 170 respectively; the first connector 170 is respectively connected with the master chip 130 and the slave chip 150, and the first connector 170 is used for being connected with an external circuit in a communication way; power supply 190 is used to power the radar antenna circuit.

Specifically, the radar antenna circuit 100 is generally applied to a radar device, the radar antenna circuit 100 may implement functions such as target detection and communication by transmitting and receiving signals, in the radar antenna circuit 100, the antenna 110 is used for transmitting or receiving radar signals, the master chip 130 (master chip) and the slave chip 150 (slave chip) are both radar chips for controlling the operation of the antenna 110, and both the master chip 130 and the slave chip 150 may include corresponding channels for receiving radar signals or transmitting radar signals. The number and the specification of the antennas 110 can be determined according to the actual situations of the master chip 130 and the slave chip 150, and generally, one antenna 110 is connected to each path of the master chip 130 and the slave chip 150. In a preferred embodiment, the antenna 110 may also be designed to be replaceable, and different antenna structures may be replaced according to requirements, so as to achieve more flexible application of the radar antenna circuit 100.

The radar antenna circuit 100 is further provided with a first connector 170 and a power supply 190, and the first connector 170 and the power supply 190 are connected to the master chip 130 and the slave chip 150, respectively. The master chip 130 and the slave chip 150 may be communicatively connected to an external circuit through the first connector 170, and the first connector 170 may transmit two paths of data of the master chip 130 and the slave chip 150 at the same time. The external circuit may be connected to the first connector 170 to receive radar signal data of the master chip 130 and the slave chip 150, so as to perform corresponding processing. The type and specification of the first connector 170 may be determined according to the actual condition of the external circuit, and may be a communication interface adopting the same communication protocol as the external circuit. The power supply 190 is used for supplying power to the radar antenna circuit 100, and besides the master chip 130 and the slave chip 150, the power supply 190 may also be connected to other components of the radar antenna circuit 100 that need to be independently supplied with power.

Further, the master chip 130 and the slave chip 150 in the radar antenna circuit 100 are connected in a cascade manner, and the master chip 130 may operate independently or may control the slave chip 150 to operate simultaneously. When the slave chip 150 is controlled by the master chip 130, the master chip 130 and the slave chip 150 are mapped in relation to each other, and when the master chip 130 performs an operation, the slave chip 150 also performs the same operation in synchronization. Compared with a single radar chip, the cascade connection of the master chip 130 and the slave chip 150 can achieve a longer measurement distance and a wider measurement range, and the measurement precision is more accurate. Moreover, by using the cascaded radar chips and using the same first connector 170 and the power supply 190 to be used by the master chip 130 and the slave chip 150, compared with the conventional radar device in which each radar chip is respectively disposed on a separate circuit board, each circuit board includes a connector and a power supply, the radar antenna circuit 100 can also reduce the waste of redundant connectors and power supplies, reduce the size of the radar device, and be adapted to applications at longer distances.

It can be understood that, the number of the master chips 130 and the slave chips 150 of the radar antenna circuit 100 may be determined according to actual requirements of a radar apparatus, one master chip 130 may be cascaded with one slave chip 150, and one master chip 130 may also be cascaded with a plurality of slave chips 150, so as to implement synchronous operation of more radar chips, and further improve the performance of the radar.

Above-mentioned radar antenna circuit 100, cascade master chip 130 with from chip 150, supply power for master chip 130 and from chip 150 through same power 190, realize master chip 130 and from chip 150 and external communication connection through first connector 170, make only need a radar antenna circuit board can realize the work of two radar chips, follow-up collection to the radar signal data of master-slave chip also only needs a data acquisition circuit, thereby system components among the radar device has been simplified constitutes, the size of radar device has effectively been reduced, resource cost is saved, it is also more convenient in the use.

Fig. 2 is a schematic structural diagram of a radar antenna circuit in an embodiment, as shown in fig. 2, based on the foregoing technical solution, a master chip 130 and a slave chip 150 are cascaded by a local oscillator signal; the local oscillation signal output terminal of the master chip 130 is connected to the local oscillation signal input terminals of the master chip 130 and the slave chip 150, respectively.

Specifically, the master chip 130 and the slave chip 150 IN this embodiment may specifically be cascaded through a Local Oscillator signal (LO), the master chip 130 includes a Local Oscillator signal input end (LO-IN) and a Local Oscillator signal output end (LO-OUT), the slave chip 150 includes a Local Oscillator signal input end (LO-IN), after the Local Oscillator signal of the master chip is sent from the Local Oscillator signal output end (LO-OUT), the Local Oscillator signals respectively enter the Local Oscillator signal input ends (LO-IN) of the master chip and the slave chip, so as to synchronize clock signals of the master chip 130 and the slave chip 150, thereby implementing the cascade connection between the master chip 130 and the slave chip 150.

Further, in one embodiment, the antenna 110 includes four transmit antennas 112 and eight receive antennas 114, the master chip 130 includes four transmit channels and four receive channels, and the slave chip 150 includes four receive channels; the four transmitting antennas 112 are connected to the four transmitting channels of the master chip 130, and the eight receiving antennas 114 are respectively connected to the four receiving channels of the master chip 130 and the four receiving channels of the slave chip 150.

Specifically, the conventional radar apparatus generally has 2-transmitting and 4-receiving modes, i.e., includes 2 transmitting channels and 4 receiving channels. In the radar antenna circuit 100 of the present embodiment, 4-transmission and 8-reception may be implemented by cascading the master chip 130 and the slave chip 150, that is, the radar antenna circuit 100 may include 4 transmission channels and 8 reception channels. The master chip 130 includes 4 Transmission (TX) signal channels and 4 Reception (RX) signal channels, the slave chip 150 includes 4 Reception (RX) signal channels, the antenna 110 specifically includes 4 transmission antennas 112 and 8 reception antennas 114, the 4 transmission antennas 112 are connected to the 4 TX signal channels of the master chip 130, and the 8 reception antennas 114 are respectively connected to the 4 RX signal channels of the master chip 130 and the 4 RX signal channels of the slave chip 150, thereby implementing 4-transmission 8-reception function in the radar antenna circuit 100.

It is understood that when the master chip 130 and the slave chip 150 operate simultaneously, the radar antenna circuit 100 operates in a 4-transmission-8-reception mode, while in other embodiments, only the master chip 130 may operate, and the radar antenna circuit 100 may operate in a 2-transmission-4-reception mode or a 4-transmission-4-reception mode.

In one embodiment, master chip 130 and slave chip 150 are 77GHz millimeter wave radar chips. The master chip 130 and the slave chip 150 may specifically adopt an ALPS millimeter-wave radar chip or a Rhine millimeter-wave radar chip produced by gatran microelectronics, for example CAL77S244 of 77 Ghz. It is understood that the specific specifications of the master chip 130 and the slave chip 150 are not limited to those in the above embodiments, and in other embodiments of the present application, the master chip 130 and the slave chip 150 may also select radar chips of other bands or other types.

In one embodiment, the first connector 170 includes at least one of a low voltage differential signal interface, a Debug interface, a CAN interface, a UART interface, and a JTAG interface. The first connector 170 may use a Low-Voltage Differential Signaling (LVDS) interface, and data of the master chip 130 and the slave chip 150 are transmitted to an external data acquisition circuit through the Low-Voltage Differential signal, where the Low-Voltage Differential signal is a Differential signal technology with Low power consumption, low error rate, low crosstalk and Low radiation, and uses an extremely Low Voltage swing high-speed Differential transmission data, so as to implement point-to-point or point-to-multipoint connection. The physical interface specifically adopted by the first connector 170 may be an RS-644 bus interface, and the transmission medium between the first connector 170 and the external circuit may be a PCB trace, or a balanced cable. It is to be understood that the specific specification of the first connector 170 is not limited to the embodiment, and in other embodiments of the present application, the first connector 170 may also select other communication protocols and physical interfaces, for example, the first connector 170 may also be a Debug interface, a CAN (Controller Area Network) interface, a UART (Universal Asynchronous Receiver Transmitter/Transmitter) interface, a JTAG (Joint Test Action Group) interface, and the like.

Fig. 3 is a schematic structural diagram of a radar antenna circuit in another embodiment, as shown in fig. 2, based on the above technical solution, a radar antenna circuit 200 in this embodiment includes a master chip 230, a slave chip 250, a first connector 270, and a power supply 290, which may be respectively the same as the corresponding components in the above embodiments, the radar antenna circuit 200 further includes a crystal oscillator 240, a flash memory module, and a communication module, the crystal oscillator 240 is connected with the master chip 230, and the flash memory module and the communication module are both connected with the master chip 230 and the slave chip 250, respectively.

Specifically, the radar antenna circuit 200 further includes a crystal oscillator 240, a flash memory module, and a communication module. The crystal oscillator 240 is configured to generate an oscillation frequency, and the crystal oscillator 240 of the present embodiment may be a passive crystal oscillator (crystal) and is connected to the main chip 230 as an external circuit. The flash memory module may be embodied as a memory in various media forms, and may include a master flash memory module 262 and a slave flash memory module 264, where the master flash memory module 262 and the slave flash memory module 264 are respectively in communication connection with the master chip 230 and the slave chip 250, and are respectively used for storing data generated by the master chip 230 and the slave chip 250. The communication module may specifically be an interface and a transmission line of various communication protocols, and may also include a master communication module and a slave communication module, which are respectively connected to the master chip 230 and the slave chip 250, so as to implement various communication functions of the master chip 230 and the slave chip 250.

Further, in a specific embodiment, the communication module includes at least one of a USB conversion module, an SPI module, a JTAG module, and a CAN module. In radar antenna circuit 200, the master communication module may specifically include a master USB conversion module 281, a master SPI module 283, a master JTAG module 285, and a master CAN module 287, and the slave communication module may specifically include a slave USB conversion module 282, a slave SPI module 284, a slave JTAG module 286, and a slave CAN module 288. The communication modules are respectively used for implementing functions of USB (Universal Serial Bus) communication, SPI (service provider interface) communication, JTAG (Joint Test Action Group) communication, CAN (Controller Area Network) communication, and the like of the master chip 230 and the slave chip, wherein the SPI modules may further include a digital SPI unit and an analog SPI unit. It is understood that the specific number and kind of the communication modules are not limited to the above embodiments, and in other embodiments of the present application, the communication modules may also include other kinds or combinations of communication interfaces and communication buses.

In one embodiment, radar antenna circuit 200 is a printed circuit board, antenna 210, master chip 230, and slave chip 250 are disposed on a front side of the printed circuit board, and first connector 270 is disposed near an edge of the printed circuit board.

Specifically, as in the radar antenna circuit 200 in fig. 3, the components of the solid frame are disposed on the front surface of a Printed Circuit Board (PCB), and the components of the dotted frame are disposed on the back surface of the PCB. Since the antenna of the radar device is generally upward after being mounted, the antenna 210 and the connected master chip 230 and slave chip 250 are disposed on the front surface of the PCB. The first connector 270 is generally disposed near an edge of the PCB in order to facilitate connection with other external circuits, and the first connector 270 may be disposed at a rear surface of the PCB in order to prevent the connected external circuits from blocking antenna signals. While the remaining components, the master SPI module 283 and the slave SPI module 284, may be disposed on the front side of the PCB, and the crystal oscillator 240, the master flash memory module 262, the slave flash memory module 264, the master USB conversion module 281, the USB conversion module 282, the master JTAG module 285, the slave JTAG module 286, the master CAN module 287, the slave CAN module 288, and the power supply 290 may be disposed on the back side of the PCB.

It can be understood that the arrangement positions of the components in the radar antenna circuit may be arranged at corresponding positions of the PCB according to the conditions of functions, connection relationships, performance requirements, and the like, and are not limited to the position arrangement manner in the above embodiments. In other embodiments of the present application, the components in the radar antenna circuit may be arranged on the PCB in other manners.

Fig. 4 is a block diagram of a radar apparatus according to an embodiment, as shown in fig. 4, in which the radar apparatus includes a data acquisition circuit 500 and the radar antenna circuit 100 of the above embodiment; the data acquisition circuit 500 includes a second connector 560, the second connector 560 is used for connecting with the first connector 170, and the signal data of the antenna 110 is transmitted to the digital acquisition circuit 500 through the first connector 170 and the second connector 560.

Specifically, in the radar apparatus 10, the radar antenna circuit 100 is used to implement functions such as target detection and communication by transmitting and receiving signals, and the data acquisition circuit 500 is used to acquire radar signal data of the radar antenna circuit 100. The data acquisition circuit 500 is provided with a second connector 560, the second connector 560 is a communication interface that adopts the same communication protocol as the first connector 170 of the radar antenna circuit 100, for example, when the first connector 170 is a Low Voltage Differential Signaling (LVDS) interface, the second connector 560 is also an LVDS interface, the first connector 170 and the second connector 560 may adopt the same physical interface form, and the first connector 170 and the second connector 560 may be connected by a PCB wire or a cable, etc. After the radar signal data of the antenna is transmitted to the data acquisition circuit 500, the data acquisition circuit 500 may also transmit the data to a computer or other device for the user to check or perform related processing.

Above-mentioned radar installations 10, cascade the master chip with from the chip, be master chip and follow the chip power supply through same power, realize master chip and follow chip and external communication connection through first connector, make only need a radar antenna circuit board can realize the work of two radar chips, follow-up also only need a data acquisition circuit to the collection of the radar signal data of master slave chip, thereby system's parts among the radar installation is constituteed, radar installation's size has effectively been reduced, the resource cost is practiced thrift, it is also more convenient in the use.

Fig. 5 is a schematic diagram of a data acquisition circuit according to an embodiment, and as shown in fig. 5, in an embodiment, the data acquisition circuit 600 includes a second connector 660, which may be the same as the corresponding components in the above embodiments, the data acquisition circuit 600 further includes an FPGA processor 620 and an ethernet interface 640, and the FPGA processor 620 is communicatively connected to an external computer device through the ethernet interface 640.

Specifically, in the present embodiment, the data acquisition circuit 600 employs an FPGA (Field Programmable Gate Array) processor. The data acquisition circuit 600 comprises a memory 670 and a power supply 680, the FPGA processor 620 is respectively connected with the memory 670 and the power supply 680, the memory 670 is used for storing the operation data of the FPGA processor 620, and the power supply 680 is used for supplying power to the FPGA processor 620. The data acquisition circuit 600 further includes an ethernet interface 640, the ethernet interface 640 may generally adopt interfaces such as RJ-45, after the radar antenna circuit sends LVDS data of a radar signal to the data acquisition circuit 600, the FPGA processor 620 processes the received data and forwards the processed data to the ethernet interface 640, the ethernet interface 640 is generally in communication connection with an external computer device, after the computer device receives the radar signal data through the ethernet interface 640, a user may open a display on a display or other devices through a graphical interface, or perform other operation processing and the like. It is understood that the processor architecture and the interface for connecting the computer device used in the data acquisition circuit 600 may be determined according to actual requirements, and are not limited to the above embodiments, and in other embodiments of the present application, the data acquisition circuit 600 may also use other types of processors and communication interfaces.

In the radar apparatus of this embodiment, the radar signal data of two radar chips of radar antenna circuit can only be handled through a data acquisition circuit and a computer equipment, and then need connect two radar antenna circuit respectively through two data acquisition boards among the traditional radar apparatus, is connected to two computer equipment respectively with two data acquisition boards again, and service environment is more complicated troublesome. Therefore, the radar device can effectively save resource cost and labor cost and is more convenient to use.

It can be understood that, the radar antenna circuit and the radar apparatus provided in the embodiments of the present application are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be implemented; in addition, specific names of the functional units are only used for distinguishing one functional unit from another, and are not used for limiting the protection scope of the present application.

In one embodiment, the present application further provides an apparatus comprising: an apparatus body; and a radar device according to the above embodiment provided on the apparatus body; wherein the radar device is used for target detection and/or communication.

Specifically, the above-mentioned device body can be an intelligent transportation device (such as an automobile, a bicycle, a motorcycle, a ship, a subway, a train, etc.), a security device (such as a camera), an intelligent wearable device (such as a bracelet, glasses, etc.), an intelligent household device (such as a television, an air conditioner, an intelligent lamp, etc.), various communication devices (such as a mobile phone, a tablet electric energy, etc.), etc., and a barrier gate, an intelligent transportation indicator lamp, an intelligent sign, a transportation camera, various industrial manipulators (or robots), etc., and also can be various instruments for detecting vital sign parameters and various devices carrying the instruments. The radar apparatus may be the radar apparatus described in any embodiment of the present application, and may implement functions such as target detection and communication by transmitting and receiving signals, and the structure and the operation principle of the radar apparatus have been described in detail in the above embodiments, which are not described in detail herein.

Above-mentioned equipment, cascade the main chip with from the chip, be main chip and follow the chip power supply through same power, realize main chip and follow chip and external communication connection through first connector, make only need a radar antenna circuit board can realize the work of two radar chips, follow-up also only need a data acquisition circuit to the collection of the radar signal data of main and slave chip, thereby system components among the radar device has been simplified and the size of radar device has effectively been reduced, the resource cost is practiced thrift, it is also more convenient in the use.

Further, on the basis of the above embodiments, in one embodiment of the present application, the radar device may be disposed outside the apparatus body, in another embodiment of the present application, the radar device may be disposed inside the apparatus body, and in other embodiments of the present application, a part of the radar device may be disposed inside the apparatus body, and a part of the radar device may be disposed outside the apparatus body. The present application is not limited to this, as the case may be.

All possible combinations of the technical features of the above embodiments may not be described for the sake of brevity, but should be considered as within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.

The above-described embodiments are merely illustrative of the preferred embodiments of the present application and the technical principles applied, and the present application has been described in detail with specific reference to the embodiments, but the present application is not limited thereto. Numerous variations, rearrangements, and substitutions will now become apparent to those skilled in the art without departing from the scope of the present application. Therefore, although the present application has been described in more detail with reference to the above embodiments, the present application is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims (10)

1. A radar system for measurement, comprising:

a printed circuit board, and the following hardware parts arranged on the printed circuit board:

a first chip configured with a first antenna array;

the second chip is provided with a second antenna array and is connected with the first chip;

wherein the first antenna array and the second antenna array are located in an antenna area of the printed circuit board; the first antenna array is used for transmitting an exploration signal wave, and the first antenna array and/or the second antenna array are used for receiving an echo signal wave corresponding to the exploration signal wave;

the signal converter is connected with the first chip or the second chip and used for converting the level signal output by the first chip or the second chip to output an intermediate signal, and the level range of the intermediate signal is lower than the level threshold of signal interference among the circuits of the printed circuit board;

and the interface adapter is connected with the signal converter and is used for processing the intermediate signal output by the signal converter into a data format adaptive to an external circuit.

2. The radar system for measurement according to claim 1, wherein the first antenna array includes a transmit antenna array and the second antenna array includes a receive antenna array; or alternatively

The first antenna array comprises a transmitting antenna array and a first receiving antenna array, and the second antenna array comprises a second receiving antenna array, wherein the first receiving antenna array and/or the second receiving antenna array receive the echo signal wave.

3. The radar system for measurement according to claim 2, wherein the transmit antenna array includes at least one transmit antenna; the first antenna array and the second antenna array each comprise at least one receiving antenna.

4. The radar system for measurement according to claim 1, wherein a spacing is set according to a wavelength of a millimeter wave between radiation structures of respective antennas in the first antenna array and the second antenna array; the radiating structure is pasted on the surface of the printed circuit board.

5. The radar system for measurement according to claim 1, wherein the local oscillator signal output terminal of the first chip or the second chip is connected to the local oscillator signal input terminal of the first chip and the local oscillator signal input terminal of the second chip, respectively.

6. The radar system for measurement according to claim 1, wherein the interface adapter comprises: at least one of a Board Connector interface, a PCI interface, a CAN interface, a UART interface, and a JTAG interface.

7. The radar system for measurement according to claim 1, wherein the first chip, the first antenna array, the second chip, and the second antenna array are all disposed on a front side of the printed circuit board.

8. Radar system for measurement according to claim 1, characterised in that the interface of the interface adapter is provided at the back and/or side edge region of the printed circuit board.

9. The radar system for measurement according to claim 1, wherein the external circuit includes at least one of: the device comprises a test instrument, an upper computer and a communication module.

10. The radar system for measurement according to claim 1, further comprising: the clock signal source is connected with the first chip or the second chip; the first chip or the second chip connected with the clock signal source generates a local oscillation signal based on the clock signal generated by the clock signal source, and transmits the local oscillation signal to the second chip or the first chip which is not connected with the clock signal source, so that the local oscillation signal can be synchronously used for: the first chip controls to transmit the detection signal wave, and the first chip and/or the second chip controls to receive the echo signal wave.

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