CN218068841U

CN218068841U - Configurable APB protocol converter and SOC system

Info

Publication number: CN218068841U
Application number: CN202220961502.0U
Authority: CN
Inventors: 王朝林; 王黎; 陶慧斌
Original assignee: Xian Jiaotong University
Current assignee: Xian Jiaotong University
Priority date: 2022-04-24
Filing date: 2022-04-24
Publication date: 2022-12-16
Anticipated expiration: 2032-04-24

Abstract

The utility model discloses a configurable APB protocol converter and an SOC system, which comprises a data writing controller, a data reading controller, a control register, a data writing buffer, a data reading buffer and an APB protocol controller; the data writing controller is connected with the control register and the data writing buffer; the control register and the write data buffer are connected with the APB protocol controller; the APB protocol controller is connected with the read data buffer, and the read data buffer is connected with the read data controller; the data writing controller and the data reading controller are both connected with an upstream control data unit, and the APB protocol controller is connected with an APB slave port; the write data buffer and the read data buffer are both FIFO's. The converter can convert the data port of the upstream main controller into a standard APB protocol interface, is easy to integrate into the SOC, reduces the complexity of non-uniform ports during SOC system integration, and realizes cross-clock domain data interaction.

Description

Configurable APB protocol converter and SOC system

Technical Field

The utility model belongs to the digital integrated circuit field relates to a can dispose APB protocol converter and a SOC system.

Background

With the development of semiconductor manufacturing technology, more and more functional units can be integrated on one chip. SOC systems based on IP design have been developed. The SOC design based on IP is a design with multiplexing design units, and with the refinement of functions and the improvement of complexity, the types and the number of IPs become larger and larger, and there is a great challenge to interconnect these functional IPs into an SOC system with reliable performance and efficient data path.

The AMBA bus system is a bus interconnection structure commonly adopted by the current SOC design, is used by a plurality of SOC system interconnection designs, and is also an industry standard of bus interconnection. How to simply use the AMBA bus for interconnection between IPs and configuration becomes the key point of SOC integration overall planning. The excellent bus interconnection structure can embody the strong advantage of chip performance. And bridge circuits of various bus interconnects play an important role in SOC system interconnection.

In the interconnection of the SOC chip, the interconnection of the common read-write data interface and the standard APB interface is a design difficulty as a typical clock domain crossing process. The clock and data rates of the two IPs are greatly different, and how to realize the interconnection between the common read-write data interface and the standard APB interface is particularly important.

SUMMERY OF THE UTILITY MODEL

To the problem that exists among the prior art, the utility model provides a can dispose APB protocol converter and an SOC system to effectively realize the interconnection of ordinary read-write data interface and standard APB interface, realize the quick access of data between the two.

The utility model discloses a realize through following technical scheme:

a configurable APB protocol converter comprises a write data controller, a read data controller, a control register, a write data buffer, a read data buffer and an APB protocol controller;

the write data controller is connected with the control register and the write data buffer;

the control register and the write data buffer are connected with the APB protocol controller;

the APB protocol controller is connected with the read data buffer, and the read data buffer is connected with the read data controller;

the data writing controller and the data reading controller are both connected with an upstream control data unit, and the APB protocol controller is connected with an APB slave port;

the write data buffer and the read data buffer are asynchronous FIFO.

Preferably, the NCLK signal input port, the WCHN signal input port, and the WVALID signal input port of the write data controller are connected to an upstream control data unit.

Preferably, the CMD signal and CVALID signal output ports of the write data controller are connected to the control register.

Preferably, the WDATA signal and DVALID signal output ports of the write data controller are connected to the write data buffer.

Preferably, the PSELn signal output port, penband signal output port, PADDR signal output port, PWRITE signal output port, PWDATA signal output port, and PRDATA signal input port of the APB protocol controller are connected to the APB slave port.

Preferably, the ARDATA signal output port and the ardalid signal output port of the read data buffer are connected to the read data controller.

Preferably, the NCLK signal input port, the RDCHN signal output port, and the RDVALID signal output port of the read data controller are connected to an upstream control data unit.

An SOC system comprises the configurable APB protocol converter.

Compared with the prior art, the utility model discloses following profitable technological effect has:

a configurable APB protocol converter comprises a write data controller, a read data controller, a control register, a write data buffer, a read data buffer and an APB protocol controller. The write data controller receives input information of the upstream control unit, writes data information into the write data buffer, and writes control information into the control register. The control register is connected with the write data controller and the APB protocol controller, receives control information of the write data controller and sends the control information to the APB protocol controller. The data writing buffer is connected with the data writing controller, receives data information of the data writing controller and sends the data to the APB protocol controller. The read data controller is connected with the read data buffer, receives data of the read data buffer and sends the data to the upstream control unit. The read data buffer is connected with the APB protocol controller, receives read transaction data of the APB protocol controller and sends the data to the read data controller. The APB protocol controller is connected with the control register, the write data buffer and the read data buffer. During writing transaction, the APB protocol controller receives a writing command of the control register, reads data from the writing data buffer, and outputs the data to the APB slave port according to the protocol specification set by the APB. In a read transaction, the APB protocol controls the reception of data from the port by the APB and the writing of the data into the read data buffer. The data writing buffer and the data reading buffer are both FIFO, and data interaction between the same clock domain or different clock domains can be realized.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

Fig. 1 is a schematic view of the connection structure of the present invention;

fig. 2 is a timing diagram of a write operation of the configurable APB protocol converter according to embodiment 2 of the present invention;

fig. 3 is a timing diagram of a read operation of the configurable APB protocol converter according to embodiment 2 of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiments of the present invention, all other embodiments obtained by a person skilled in the art without making creative efforts belong to the protection scope of the present invention.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

In the description of the embodiments of the present invention, it should be noted that, if the terms "upper", "lower", "horizontal", "inner", etc. indicate the orientation or position relationship based on the orientation or position relationship shown in the drawings, or the orientation or position relationship that the product of the present invention is usually placed when in use, the description is only for convenience of description and simplification, but the indication or suggestion that the device or element to be referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be interpreted as limiting the present invention. Furthermore, the terms "first," "second," and the like are used solely to distinguish one from another, and are not to be construed as indicating or implying relative importance.

Furthermore, the term "horizontal", if present, does not mean that the component is required to be absolutely horizontal, but may be slightly inclined. For example, "horizontal" merely means that the direction is more horizontal than "vertical" and does not mean that the structure must be perfectly horizontal, but may be slightly inclined.

In the description of the embodiments of the present invention, it should be further noted that unless explicitly stated or limited otherwise, the terms "disposed," "mounted," "connected," and "connected" should be interpreted broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.

The present invention will be described in further detail with reference to the accompanying drawings:

as shown in fig. 1, a configurable APB protocol converter includes a write data controller, a read data controller, a control register, a write data buffer, a read data buffer, and an APB protocol controller; the write data controller is connected with the control register and the write data buffer; the control register and the write data buffer are connected with the APB protocol controller; the APB protocol controller is connected with a read data buffer, and the read data buffer is connected with the read data controller; the data writing controller and the data reading controller are both connected with an upstream control data unit, and the APB protocol controller is connected with an APB slave port; the write data buffer and the read data buffer are both FIFO interfaces.

Specifically, the WCHN signal input port and the WVALID signal input port of the write data controller are connected to the upstream control data unit, and are configured to receive input information of the upstream control unit. Meanwhile, a CMD signal output port of the write data controller is connected with the control register and used for writing the control information into the control register, and a WDATA signal output port of the write data controller is connected with the write data buffer and used for writing the data information into the write data buffer. In addition, the control register is connected with the APB protocol controller and used for sending the received control information from the write data controller to the APB protocol controller. Meanwhile, the write data buffer is connected with the APB protocol controller and used for sending the received data information from the write data controller to the APB protocol controller.

The APB protocol controller is provided with a PSELn signal output port, a PENBABLE signal output port, a PADDR signal output port, a PWRITE signal output port, a PWDATA signal output port and a PRDATA signal input port which are connected with the APB slave port. During writing transaction, the APB protocol controller receives a writing command of the control register, reads data from the writing data buffer, and outputs the data to the APB slave port according to the established APB protocol specification. In a read transaction, the APB protocol controls the reception of data from the port by the APB and the writing of the data into the read data buffer.

The read data controller is connected with the ARDATA signal and ARVALID signal output ports of the read data buffer, and is used for receiving the data of the read data buffer and sending the data to the upstream control unit. Meanwhile, the read data buffer is connected with the APB protocol controller and used for receiving the read transaction data of the APB protocol controller and sending the data to the read data controller. The RDCHN signal output port and the RDVALID signal output port of the read data controller are connected with the upstream control data unit and used for transmitting read data to the upstream control unit.

Therefore, in the present invention, the write data controller is mainly used for receiving the information input by the upstream control unit through the write channel, and writing the input information into the control register and the write data buffer according to the data format specification; the control register is mainly used for storing configuration information. The data in the configuration register is typically in a fixed format defined in advance, and different data bits represent different configuration functions. The write data buffer is mainly used for storing data needing to be sent by the APB controller. The write data buffer is an asynchronous FIFO, and data interaction between different clock domains can be realized. The read data controller is mainly used for storing data read from the device side of the APB. The read data buffer is an asynchronous FIFO, and data interaction between different clock domains can be realized. The APB protocol controller generates address and control signals required by the APB protocol according to the configuration information stored in the control register. The write and read data addresses can be automatically calculated based on the configuration information. The APB protocol controller writes data read from the APB slave device into the read data buffer. Through the utility model provides a can dispose APB protocol converter can realize converting ordinary read-write data format into standard APB bus protocol.

The utility model also discloses a SOC system, including the utility model provides a can dispose APB protocol converter.

The utility model provides a data interaction process as follows:

(1) Configuration information or data information is written by the upstream processing unit through the write channel.

(2) The write data controller stores the input information into a control register or a write data buffer according to the configurable APB protocol converter input channel information specification.

(3) After receiving the control information, the control register outputs a state flag to the APB protocol controller.

(4) The APB protocol controller firstly reads the control information in the control register according to the status flag. Reading data in the write data buffer according to the control information;

(5) The APB protocol controller generates a slave device chip selection signal PSELn according to the control information; a slave device operation enable signal PENABLE, a slave device read-write address signal PADDR;

(6) And the APB protocol controller determines whether to send the data in the write data buffer to an APB write data channel or receive the data from an APB read data channel according to the read-write control bit information in the control information, and writes the data into a read data buffer, wherein the function is a function established by the APB protocol controller.

(7) If the read-write control bit in the control information is high, indicating a write operation, the APB protocol controller sends PADDR, PSELn, PWRITE (high state at this time), PENABLE, PWDATA to the slave device to complete a write operation, and the function is the function established by the APB protocol controller.

(8) If the read-write control bit in the control information is low, indicating read operation, the APB protocol controller sends PADDR, PSELn, PWRITE (at this time, low state) and PENABLE; this function is the function intended by the APB protocol controller.

(9) In the read operation, the APB protocol controller writes data transmitted by the APB from the device into a read data buffer, and the read data buffer sends a status flag to the read data controller;

(10) The read data controller reads the data in the read data buffer after receiving the status flag, sends the data to the upstream processing unit, and generates a data valid flag signal.

Example 2

The utility model relates to a can dispose APB protocol converter converts the main control unit data port in the upper reaches into standard APB protocol interface, can facilitate for main control has bus, system submodule piece and the system peripheral hardware of APB interface through APB interface access. The module can be conveniently integrated into the SOC and used as a part of SOC bus interconnection, and the integration complexity of the SOC system integration caused by non-uniform ports is reduced. Meanwhile, for the data buffer unit, asynchronous FIFO is adopted, cross-clock domain data interaction is realized, and convenience is brought to cross-clock domain design.

Further, taking data read and write operations as an example, the specific implementation steps of the configurable APB protocol converter in the present invention completing one read and write operation are described.

As shown in fig. 2, a timing diagram of a write operation of the configurable APB protocol converter:

(1) At time T0 and time T1, the write data controller receives the configuration information C0 and C1 transmitted on the write channel WCHN, the WVALID signal is high, and the transmitted data is valid.

(2) The data writing controller writes the first two groups of valid data into the control register at the time T3 and the time T4 according to the data transmission format.

(3) The data writing controller receives data information D0 and D1 transmitted from a writing channel WCHN at the time of T4 and T5, and writes input data into a data buffer memory at the time of T7 and T8;

(4) After receiving the configuration information of the control register unit, the APB protocol controller generates APB protocol control signals PADDR, PSELn and PWRITE at time T12 according to the information of the address, data length, read-write operation bit and slave device selection bit of the configuration information, where the PWRITE signal is high, indicating a write operation.

(5) The APB protocol controller asserts the enable signal high at times T13, T15, asserts data on the APB write data channel, and transfers data to the PWDATA write data channel at times T12 and T14.

As shown in fig. 3, for the configurable APB protocol converter read operation steps:

(1) At the time of T0 and T1, the data writing controller receives the configuration information C0 and C1 transmitted from the writing channel, the WVALID signal is high, and the transmission data is valid.

(3) The APB protocol controller generates a read data address PADDR, an APB chip select signal PSELn, and a read operation enable signal PWRITE, which is in a low state indicating a read operation, according to the information of the configuration register.

(4) At times T7 and T9, the penalty signal is high and data is received from the APB slave, or APB slave device. The APB protocol converter writes data to the read data buffer at times T11 and T12.

(5) The read data buffer sends the received data status information to the read data controller, which reads the data in the read data buffer and sends the data to the upstream control unit at times T15 and T16.

The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A configurable APB protocol converter is characterized by comprising a write data controller, a read data controller, a control register, a write data buffer, a read data buffer and an APB protocol controller;

the write data buffer and the read data buffer are asynchronous FIFO.

2. The configurable APB protocol converter of claim 1, wherein the NCLK, WCHN, and WVALID signal input ports of the write data controller are connected to upstream control data units.

3. The APB converter of claim 1, wherein the CMD signal and CVALID signal output ports of the write data controller are configured to be coupled to the control register.

4. The APB protocol converter of claim 1, wherein the WDATA signal and DVALID signal output ports of the write data controller are configured to couple to the write data buffer.

5. The APB configurable protocol converter of claim 1, wherein the PSELn signal output port, the PENBABLE signal output port, the PADDR signal output port, the PWRITE signal output port, the PWDATA signal output port and the PRDATA signal input port of the APB protocol controller are connected to the APB slave port.

6. The configurable APB protocol converter of claim 1, wherein the ARDATA signal output port and the ARVALID signal output port of the read data buffer are configured to interface with the read data controller.

7. The configurable APB protocol converter of claim 1, wherein the NCLK signal input port, RDCHN signal output port, and RDVALID signal output port of the read data controller are configured to interface with an upstream control data unit.

8. An SOC system, comprising the configurable APB protocol converter of any one of claims 1 to 7.