CN217390725U - Interference suppression circuit for wearable electrocardiogram acquisition - Google Patents
Interference suppression circuit for wearable electrocardiogram acquisition Download PDFInfo
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- CN217390725U CN217390725U CN202220619105.5U CN202220619105U CN217390725U CN 217390725 U CN217390725 U CN 217390725U CN 202220619105 U CN202220619105 U CN 202220619105U CN 217390725 U CN217390725 U CN 217390725U
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Abstract
The utility model relates to the technical field of medical electronic instruments, in particular to an interference suppression circuit for wearable electrocardio acquisition, which comprises two lead input ends, a right leg drive, an electrostatic protection circuit, a buffer, an electrocardiosignal conditioning chip and a power frequency wave trap, wherein the two lead input ends are connected with the input end of the electrocardiosignal conditioning chip through the buffer, the output end of the electrocardiosignal conditioning chip is connected with the power frequency wave trap, the input end of the right leg drive is connected with the output end of the buffer and the electrostatic protection circuit, thereby solving the problems that the prior electrocardiosignal conditioning chip is not only influenced by a lead mode and electrode materials when acquiring electrocardiosignals, but also has poor suppression capability on power frequency interference, the utility model strengthens input impedance by arranging the buffer and the power frequency wave trap, and maximally reduces the interference of power frequency signals, therefore, more accurate electrocardiosignals can be obtained, and the reliability of electrocardio detection data is improved.
Description
Technical Field
The utility model relates to a medical electronic instrument technical field especially relates to a wearing formula electrocardio collection restrain interference circuit.
Background
An Electrocardiogram (ECG) is used for recording the electrocardio-changes caused by the electrocardio-activities of the human body, can reflect the physiological activity conditions of the human body, and has great significance for the diagnosis of doctors. However, the ECG signal is a very weak physiological signal, the voltage amplitude of the variation ranges from 1mV to 4mV, the frequency ranges from 0.05 HZ to 100HZ, and during the collection of the ECG signal, there are usually many kinds of noises, mainly including: baseline drift, myoelectricity interference, power frequency interference and motion interference, and the identification of the electrocardiographic waveform can be seriously influenced by the interference signals, so that the misdiagnosis phenomenon is caused.
In order to suppress the interference of the noise and obtain a pure electrocardiogram, some semiconductor companies have proposed IC chips for high-performance ECG signal acquisition, but because the wearing modes of the electrocardiographic detection products are different, the lead modes are different, and for the differences, the IC chips for acquiring ECG signals cannot be well adapted, that is, the wearing modes will affect the performance of the IC chips, and meanwhile, different choices of electrode materials will also affect the ECG signals acquired by the IC chips, and in addition, the suppression capability of the IC chips on power frequency interference is generally not obvious.
SUMMERY OF THE UTILITY MODEL
The utility model provides a wearing formula electrocardio collection restrain interference circuit, the technical problem of solution is, current electrocardiosignal takes care of the chip when gathering electrocardiosignal, not only receives the influence of the mode of leading, electrode material, and is poor to power frequency interference's suppressive capability moreover.
In order to solve the technical problem, the utility model provides a wearable interference suppression circuit for electrocardiograph acquisition, which comprises two lead input ends, a right leg drive, an electrostatic protection circuit, a buffer, an electrocardiograph signal conditioning chip and a power frequency wave trap, wherein the two lead input ends are respectively a first lead input end and a second lead input end;
the two lead input ends are connected with the input end of the electrocardiosignal conditioning chip through the buffer, the output end of the electrocardiosignal conditioning chip is connected with the power frequency wave trap, and the input end of the right leg drive is connected with the output end of the buffer and the electrostatic protection circuit.
In a further embodiment, the first lead input and the second lead input are both connected to the electrostatic protection circuit.
In a further embodiment, the buffer includes a first voltage follower and a second voltage follower connected in parallel.
In a further embodiment, the first voltage follower comprises a first resistor and a first operational amplifier;
one end of the first resistor is connected with the first lead input end, the other end of the first resistor is connected with the non-inverting input end of the first operational amplifier, and the inverting input end of the first operational amplifier is connected with the output end of the first operational amplifier.
In a further embodiment, the second voltage follower comprises a second resistor and a second operational amplifier;
one end of the second resistor is connected with the second lead input end, the other end of the second resistor is connected with the non-inverting input end of the second operational amplifier, and the inverting input end of the second operational amplifier is connected with the output end of the second operational amplifier.
In a further embodiment, the power frequency trap comprises a double-T network passive filter, a third operational amplifier and a fourth operational amplifier, wherein the double-T network passive filter comprises third to tenth resistors and first to fourth capacitors;
the input end of the power frequency wave trap is connected with the non-inverting input end of a third operational amplifier through a third resistor, a fourth resistor, a fifth resistor and a sixth resistor which are sequentially connected in series, the inverting input end of the third operational amplifier is connected with the output end of the third operational amplifier, and the output end of the third operational amplifier is grounded through a ninth resistor and a tenth resistor which are connected in series; the input end of the power frequency wave trap is also connected with the non-inverting input end of the third operational amplifier through the first capacitor and the second capacitor which are connected in series, and the third capacitor and the fourth capacitor are connected between the fourth resistor and the fifth resistor in parallel;
One end of the seventh resistor is connected with the common end of the first capacitor and the second capacitor, the other end of the seventh resistor is connected with the output end of the fourth operational amplifier through an eighth resistor, the inverting input end of the fourth operational amplifier is connected with the common end of the ninth resistor and the tenth resistor, and the non-inverting input end of the fourth operational amplifier is connected with the output end of the fourth operational amplifier.
In a further embodiment, the first and second lead inputs are RA and LA electrodes, respectively.
In a further embodiment, the power frequency trap comprises a trap centered at 50 Hz.
The utility model provides a pair of wearing formula electrocardio is gathered suppresses interference circuit, including electrostatic protection circuit, buffer, electrocardiosignal conditioning chip and power frequency trapper, wherein, two buffers and electrocardiosignal conditioning chip that lead the input and connect the power frequency trapper through connecting gradually, the output of buffer is connected to right leg driven input, and electrostatic protection circuit still leads input and right leg drive to two and carries out electrostatic protection. The utility model discloses a buffer can restrain the influence that the difference of the mode of leading, electrode material and individual epidermis brought, improves input impedance, adopts the interference that reduces the power frequency signal that power frequency trapper can maximize, improves electrocardiosignal acquisition's accuracy effectively, the utility model discloses whole circuit structure is simple, provides reliable instrument for relevant clinical research simultaneously, and application scope is wide, can be applicable to various electronic equipment that have ECG and detect.
Drawings
Fig. 1 is a block diagram of an interference suppression circuit for wearable electrocardiograph acquisition according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a buffer circuit provided by an embodiment of the present invention;
fig. 3 is a schematic circuit diagram of a power frequency wave trap provided in an embodiment of the present invention;
fig. 4 is a schematic diagram comparing ECG waveforms provided by the embodiment of the present invention.
Detailed Description
The following embodiments of the present invention will be described in detail with reference to the accompanying drawings, which are given for illustrative purposes only and are not to be construed as limiting the invention, including the drawings, which are only used for reference and illustration, and do not constitute a limitation to the scope of the invention, since many changes may be made thereto without departing from the spirit and scope of the invention.
Referring to fig. 1, the embodiment of the utility model provides a wearing formula electrocardio is gathered suppresses interference circuit, can be applied to all electronic equipment that have ECG detection function such as wearing formula wrist-watch, as shown in fig. 1, suppress interference circuit and include that two lead input, right leg drive RLD, electrostatic protection circuit 1, buffer 2, electrocardiosignal condition chip 3 and power frequency trapper 4, wherein, two lead inputs include first lead input and second lead input, electrocardiosignal condition chip is including the IC chip that is used for gathering electrocardiosignal, in this embodiment, first lead input with the second lead input is RA electrode, LA electrode respectively.
In this embodiment, the two lead input ends LA and RA are both connected to the input end of the ecg signal conditioning chip 3 through the buffer 2, the output end of the ecg signal conditioning chip 3 is connected to the power frequency trap 4, the input end of the right leg driving RLD is connected to the output end of the buffer 2 and the electrostatic protection circuit 1, and the first lead input end LA and the second lead input end RA are both connected to the electrostatic protection circuit 1.
In the embodiment, when the device works, two lead input ends LA and RA are used for collecting human body electrocardiosignals; the input end of the right leg driving RLD is used for acquiring a reference signal of a human body, so that a common-mode interference signal in an electrocardiosignal is suppressed by utilizing negative feedback regulation, and the processed electrocardiosignal is input to an electrocardiosignal conditioning chip; the electrocardiosignal conditioning chip is used for amplifying and filtering the processed electrocardiosignals, wherein the filtering comprises low-pass filtering and high-pass filtering.
In the embodiment, the static protection is performed on the three inputs, namely the first lead input terminal LA, the second lead input terminal RA and the right leg driving RLD, so that the static protection capability of different inputs can be improved, and the static resistance capability of the interference suppression circuit is effectively improved.
Meanwhile, due to the fact that the gray level of the skin is different and the body hair of the wearing part of an individual is different, the contact resistance of the electrode and the skin detection is caused to float, and when the contact resistance is too large, the load capacity of a circuit is affected, so that the two voltage followers are connected to the lead input end to improve the input impedance.
In one embodiment, the buffer 2 comprises a first voltage follower and a second voltage follower connected in parallel.
As shown in fig. 2, the first voltage follower includes a first resistor R1 and a first operational amplifier a 1; wherein one end of the first resistor R1 is connected to the first lead input terminal LA, the other end of the first resistor R1 is connected to the non-inverting input terminal of the first operational amplifier A1, the non-inverting input terminal of the first operational amplifier A1An inverting input terminal and an output terminal V of the first operational amplifier A1 out1 And (4) connecting.
The second voltage follower comprises a second resistor R2 and a second operational amplifier A2; one end of the second resistor R2 is connected to the second lead input terminal RA, the other end of the second resistor R2 is connected to the non-inverting input terminal of the second operational amplifier A2, the inverting input terminal of the second operational amplifier A2 is connected to the output terminal V of the second operational amplifier A2 out2 And (4) connecting.
The buffer provided by the embodiment can improve the input impedance, thereby inhibiting the influence caused by different lead modes, electrode materials and individual epidermis.
In one embodiment, the power frequency trap 4 comprises a dual-T network passive filter, a third operational amplifier and a fourth operational amplifier; the double-T network passive filter comprises third to tenth resistors and first to fourth capacitors; in this embodiment, the power frequency wave trap is configured to perform power frequency filtering on the electrocardiographic signal processed by the electrocardiographic signal conditioning chip, and input the filtered signal to the microprocessor.
As shown in fig. 3, the input terminal of the power frequency trap 4 is connected to the non-inverting input terminal of the third operational amplifier A3 through a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6 which are connected in series in sequence, the inverting input terminal of the third operational amplifier A3 is connected to the output terminal of the third operational amplifier A3, and the output terminal of the third operational amplifier A3 is further connected to the ground through a ninth resistor R9 and a tenth resistor R10 which are connected in series; the input end of the power frequency trap 4 is further connected with the non-inverting input end of the third operational amplifier A3 through the first capacitor C1 and the second capacitor C2 which are connected in series, and the third capacitor C3 and the fourth capacitor C4 are connected in parallel between the fourth resistor R4 and the fifth resistor R5;
One end of the seventh resistor R7 is connected to the common end of the first capacitor C1 and the second capacitor C2, the other end of the seventh resistor R7 is connected to the output end of the fourth operational amplifier a4 through an eighth resistor R8, the inverting input end of the fourth operational amplifier a4 is connected to the common end of the ninth resistor R9 and the tenth resistor R10, and the non-inverting input end of the fourth operational amplifier a4 is connected to the output end of the fourth operational amplifier a 4.
In one embodiment, the power frequency trap comprises a center frequency f 0 The 50Hz trap provided in this embodiment can eliminate 50Hz power frequency interference, and the parameters of the filter are as follows:
C=1/（2π*f 0 *R）
Q=f 0 /BW 3dB
wherein C represents an equivalent capacitance, f 0 Representing the trap center frequency, R the equivalent resistance, Q the quality factor, BW 3dB Representing a 3db bandwidth.
The double-T network passive filter device meets the following relation:
C 1 =C 2 =C；C 3 +C 4 =2C
R 3 +R 4 =R 5 +R 6 =R；R 7 +R 8 =1/（2R）。
it should be noted that, in this embodiment, preferably, the third resistor R3, the fifth resistor R5, the seventh resistor R7 and the ninth resistor R9 are set to 5.1K Ω, the fourth resistor R4, the sixth resistor R6 and the tenth resistor R10 are set to 91K Ω, the eighth resistor R8 is set to 43K Ω, and the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 are set to 33 nF.
As shown in fig. 4, the ECG waveform of the interference suppression circuit provided in this embodiment has the characteristics of stable output waveform and low noise, and when the human body motion interference signal is reduced, the accuracy of acquiring the electrocardiographic signal is ensured.
The embodiment of the utility model provides a pair of wearing formula electrocardio collection's interference suppression circuit, through setting up two input terminals that lead, right leg drive RLD, electrostatic protection circuit, buffer, electrocardiosignal conditioning chip and power frequency trapper, solved current electrocardiosignal conditioning chip when gathering electrocardiosignal, not only received the mode of leading, electrode material's influence, and the poor problem of power frequency interference's inhibition ability, the embodiment of the utility model provides a through buffer and power frequency trapper, not only improved input impedance, have higher common mode rejection ratio, strengthened moreover and inhibited power frequency interference ability, the interference suppression circuit simple structure that this embodiment provided simultaneously, it is high to the identification rate of electrocardiosignal, and can detect the rhythm of the heart more accurately, reduce clinical misdiagnosis rate.
The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be equivalent replacement modes, and all are included in the scope of the present invention.
Claims (8)
1. The utility model provides a wearing formula electrocardio is gathered suppresses interference circuit which characterized in that: the device comprises two lead input ends, a right leg drive, an electrostatic protection circuit, a buffer, an electrocardiosignal conditioning chip and a power frequency wave trap, wherein the two lead input ends are respectively a first lead input end and a second lead input end;
the two lead input ends are connected with the input end of the electrocardiosignal conditioning chip through the buffer, the output end of the electrocardiosignal conditioning chip is connected with the power frequency wave trap, and the input end of the right leg drive is connected with the output end of the buffer and the electrostatic protection circuit.
2. The interference suppression circuit for wearable electrocardiographic acquisition according to claim 1, wherein: the first lead input end and the second lead input end are both connected with the electrostatic protection circuit.
3. The interference suppression circuit for wearable electrocardiographic acquisition according to claim 1, wherein: the buffer comprises a first voltage follower and a second voltage follower connected in parallel.
4. The interference suppression circuit for wearable electrocardiographic acquisition as claimed in claim 3, wherein: the first voltage follower comprises a first resistor and a first operational amplifier;
one end of the first resistor is connected with the first lead input end, the other end of the first resistor is connected with the non-inverting input end of the first operational amplifier, and the inverting input end of the first operational amplifier is connected with the output end of the first operational amplifier.
5. The interference suppression circuit for wearable electrocardiographic acquisition according to claim 3, wherein: the second voltage follower comprises a second resistor and a second operational amplifier;
one end of the second resistor is connected with the second lead input end, the other end of the second resistor is connected with the non-inverting input end of the second operational amplifier, and the inverting input end of the second operational amplifier is connected with the output end of the second operational amplifier.
6. The interference suppression circuit for wearable electrocardiographic acquisition according to claim 1, wherein: the power frequency wave trap comprises a double-T network passive filter, a third operational amplifier and a fourth operational amplifier, wherein the double-T network passive filter comprises third to tenth resistors and first to fourth capacitors;
The input end of the power frequency wave trap is connected with the non-inverting input end of a third operational amplifier through a third resistor, a fourth resistor, a fifth resistor and a sixth resistor which are sequentially connected in series, the inverting input end of the third operational amplifier is connected with the output end of the third operational amplifier, and the output end of the third operational amplifier is grounded through a ninth resistor and a tenth resistor which are connected in series; the input end of the power frequency wave trap is also connected with the non-inverting input end of the third operational amplifier through a first capacitor and a second capacitor which are connected in series, and the third capacitor and the fourth capacitor are connected between the fourth resistor and the fifth resistor in parallel;
one end of a seventh resistor is connected with the common end of the first capacitor and the second capacitor, the other end of the seventh resistor is connected with the output end of the fourth operational amplifier through an eighth resistor, the inverting input end of the fourth operational amplifier is connected with the common end of the ninth resistor and the tenth resistor, and the non-inverting input end of the fourth operational amplifier is connected with the output end of the fourth operational amplifier.
7. The interference suppression circuit for wearable electrocardiographic acquisition according to claim 1, wherein: the first lead input end and the second lead input end are respectively an RA electrode and an LA electrode.
8. The interference suppression circuit for wearable electrocardiographic acquisition according to claim 1, wherein: the power frequency wave trap comprises a wave trap with the center frequency of 50 Hz.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220619105.5U CN217390725U (en) | 2022-03-22 | 2022-03-22 | Interference suppression circuit for wearable electrocardiogram acquisition |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220619105.5U CN217390725U (en) | 2022-03-22 | 2022-03-22 | Interference suppression circuit for wearable electrocardiogram acquisition |
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| CN217390725U true CN217390725U (en) | 2022-09-09 |
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| CN202220619105.5U Active CN217390725U (en) | 2022-03-22 | 2022-03-22 | Interference suppression circuit for wearable electrocardiogram acquisition |
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- 2022-03-22 CN CN202220619105.5U patent/CN217390725U/en active Active
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