CN217085740U

CN217085740U - Extension structure, mainboard and electronic equipment

Info

Publication number: CN217085740U
Application number: CN202123450357.4U
Authority: CN
Inventors: 王宏伟
Original assignee: Loongson Zhongke Chengdu Technology Co ltd
Current assignee: Loongson Zhongke Chengdu Technology Co ltd
Priority date: 2021-12-31
Filing date: 2021-12-31
Publication date: 2022-07-29
Anticipated expiration: 2031-12-31

Abstract

The embodiment of the utility model provides an extension structure, mainboard and electronic equipment, extension structure includes treater and at least two bus controller; the processor is integrated with parallel port controllers, and at least two bus controllers are provided with parallel transmission interfaces matched with the parallel port controllers; and at least two bus controllers are respectively connected with different signal pins of the parallel port bus controller. The embodiment of the utility model provides an in the extension structure that provides, through connect each bus controller respectively on the different signal pins of the parallel port controller of treater, avoid occuping of signal path in the same time quantum, can realize two bus controller's simultaneous workings, improve data transceiver efficiency.

Description

Extension structure, mainboard and electronic equipment

Technical Field

The utility model relates to a computer technology field especially relates to an extension structure, mainboard and electronic equipment.

Background

With the development and progress of science and technology, in the field of industrial control, various types of signal acquisition devices are increasingly used, and the various types of signal acquisition devices need to rely on a bus to realize signal transmission with a processor. When the bus interface is limited and there are more signal acquisition devices to be connected, the bus interface needs to be expanded to realize the access of more signal acquisition devices.

However, the existing bus extension mode cannot realize simultaneous operation of different bus controllers, and reduces data transceiving efficiency.

SUMMERY OF THE UTILITY MODEL

In view of the above problems, an extension structure, a motherboard, and an electronic device that overcome or at least partially solve the above problems are provided to solve the problem that the existing bus extension method cannot achieve simultaneous operations of different bus controllers, thereby reducing data transceiving efficiency.

In order to solve the above problem, in one aspect, the present invention discloses an extension structure, which includes a processor and at least two bus controllers;

the processor is integrated with parallel port controllers, and at least two bus controllers are provided with parallel transmission interfaces matched with the parallel port controllers;

and at least two bus controllers are respectively connected with different signal pins of the parallel port controller.

Optionally, the at least two bus controllers comprise a first bus controller and a second bus controller;

the first bus controller is electrically connected with a low eight-bit signal pin and a chip selection signal pin of the parallel port controller;

the second bus controller is connected with a high eight-bit signal pin of the parallel port controller and is electrically connected with a GPIO pin of the processor.

Optionally, the first bus controller and the second bus controller are both CAN controllers, and the extension structure further includes a first CAN transceiver and a second CAN transceiver;

the first CAN controller is electrically connected with the first CAN transceiver through a CAN bus, and the second CAN controller is electrically connected with the second CAN transceiver through a CAN bus.

Optionally, the CAN bus comprises an RX signal line for transmitting data to the first bus controller and the second bus controller, and a TX signal line for transmitting data to the first CAN transceiver and the second CAN transceiver.

Optionally, the first bus controller and the second bus controller are electrically connected to an address data selection signal pin, a data read valid pin and a data write valid pin of the parallel port controller at the same time.

Optionally, when the data read valid pin is active at a low level, the first bus controller and/or the second bus controller reads data from the processor;

when the data write active pin is active at a low level, the first bus controller and/or the second bus controller writes data to the processor.

In a second aspect, an embodiment of the present invention further provides a motherboard, where the motherboard includes the extension structure of the foregoing first aspect.

In a third aspect, an embodiment of the present invention further provides an electronic device, where the electronic device includes the extended structure of the foregoing first aspect or the motherboard of the foregoing second aspect.

The embodiment of the utility model provides a include following advantage:

the embodiment of the utility model provides an in the extension structure that provides, through connect each bus controller respectively on the different signal pins of the parallel port controller of treater, avoid occuping of signal path in the same time quantum, can realize two bus controller's simultaneous workings, improve data transceiver efficiency.

Drawings

Fig. 1 is a schematic view of a first embodiment of the invention;

fig. 2 is a schematic view of a second expanded configuration of the present invention;

fig. 3 is a schematic view of a third extended structure of the present invention.

Detailed Description

In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention is described in detail with reference to the accompanying drawings and the detailed description.

Referring to fig. 1, an embodiment of the present invention provides an extension structure, which is applied to bus extension of a processor interface, and includes a processor 10 and at least two bus controllers;

the processor 10 is integrated with a parallel port controller 101, and at least two bus controllers each have a transmission interface matched with the parallel port controller 101;

at least two bus controllers are respectively connected with different signal pins of the parallel port controller 101.

Specifically, the processor 10 in the embodiment of the present invention is a Central Processing Unit (CPU). When the bus interface of the processor 10 is used up, a new extension structure can be constructed by using the connection method provided by the embodiment of the present invention, so as to meet the use requirement of the peripheral circuit. The embodiment of the present invention provides a parallel port controller 101 integrated inside a processor 10, wherein the parallel port controller 101 provides a simple peripheral access interface, and is mainly used for connecting a system boot ROM (Read-Only Memory). The parallel port controller 101 provides a chip select signal externally, which has configurable data bit width and access delay, and the parallel port controller 101 has an address data multiplexing function, so that the bus interface can be expanded by time division multiplexing. Illustratively, the parallel port controller 101 in the present invention may be an LIO (local IO) controller or an ISA (Industrial Standard Architecture) controller.

The embodiment of the utility model provides an in, with two at least bus controllers respectively through the parallel port bus connection on the different signal pins of parallel port controller 101. In specific application, if the parallel port controller 101 is an LIO controller, the parallel port bus is an LIO bus, and two, three or four bus controllers can be selectively connected according to the width of the LIO bus, such as 16 bits, 24 bits or 32 bits, that is, each bus controller independently occupies eight bit line widths for data transmission, and different bus controllers occupy different bit numbers for data transmission, so that the work of each bus controller is not interfered with each other, the simultaneous work of each bus controller can be realized, and the data transceiving efficiency is improved.

Alternatively, referring to fig. 1, taking the number of bus controllers as two as an example, the bus controllers include a first bus controller 11 and a second bus controller 12; the parallel port controller 101 comprises 16-bit signal pins, namely a low eight-bit signal pin and a high eight-bit signal pin; in addition, the parallel port controller further includes a chip select signal pin and a GPIO (General-purpose input/output) pin, where the chip select signal pin is used to select one active bus controller, and when the parallel port controller 101 has only one chip select signal pin, the GPIO pin can be used to select another active bus controller.

The first bus controller 11 is electrically connected to a first set of eight-bit signal pins and a chip select signal pin of the parallel port controller 101;

the second bus controller 12 is electrically connected to the second set of eight-bit signal pins of the parallel port controller 101 and the GPIO pins of the processor 10.

Specifically, in the embodiment of the present invention, the bus controller may include a first bus controller 11 and a second bus controller 12, which are connected to the first group of eight-bit signal pins and the second group of eight-bit signal pins of the parallel port controller 101 through the parallel port bus, respectively. The first eight-bit signal pins may be eight signal pins with consecutive pin numbers, or eight signal pins with alternating even or odd numbers. The second set of eight bit signal pins may be consecutive or alternate, similar to the first set of eight bit signal pins. In a specific implementation process, the corresponding connection mode may be selected according to the characteristics of the parallel port controller 101, the first bus controller 11, and the second bus controller 12.

For example, as shown in fig. 2, when the parallel port controller 101 is an LIO controller, the first bus controller 11 is electrically connected to a first set of eight-bit signal pins of the parallel port controller 101 and an LIO chip select signal pin LIO _ CSN, and the second bus controller 12 is electrically connected to a second set of eight-bit signal pins of the parallel port controller 101 and a GPIO pin of the processor 10, which can be configured as another chip select function pin by software.

Therefore, it can be understood from the figure that the first bus controller 11 is selectively enabled to operate when the LIO chip select signal pin LIO _ CSN is active low, and the second bus controller 12 is selectively enabled to operate when the GPIO pin is active low. In addition, the two bus controllers respectively transmit data/addresses through two groups of eight-bit signal pins, and the transmission channels of the data/addresses are not occupied in the same time period, so that the two bus controllers can be simultaneously selected to be started and work independently.

Optionally, referring to fig. 3, the first bus controller 11 and the second bus controller 12 are both CAN controllers, and the extension structure further includes a first CAN transceiver 13 and a second CAN transceiver 14;

the first bus controller 11 is electrically connected to the first CAN transceiver 13 via a CAN bus, and the second bus controller 12 is electrically connected to the second CAN transceiver 14 via a CAN bus.

Specifically, as shown in fig. 3, in one embodiment, when it is required to implement an extension of a CAN (Controller Area Network) bus, the first bus Controller 11 and the second bus Controller 12 are both CAN controllers. The CAN controller is used to receive data from the processor 10 or to transmit data to the processor 10. The data received and transmitted by the CAN controller also needs to be converted between the binary code stream and the differential signal through the CAN transceiver. Specifically, the first CAN transceiver 13 receives data from the first CAN controller 11 through a TX signal line in the CAN bus, and transmits data to the first CAN controller 11 through an RX signal line in the CAN bus, so as to realize data interaction with the first CAN controller 11 and convert data of the first CAN controller 11. The second CAN transceiver 14 receives data from the second CAN controller 12 through a TX signal line in the CAN bus, and transmits data to the second CAN controller 12 through an RX signal line in the CAN bus, so that data interaction with the first CAN controller 11 is realized, and data of the second CAN controller 12 is converted. Illustratively, the processor 10 used in the present invention may be a Loongson processor.

Alternatively, referring to fig. 2, the first set of eight bit signal pins are low eight bit signal pins and the second set of eight bit signal pins are high eight bit signal pins.

Specifically, as shown in FIG. 2, the first eight-bit signal pins may be eight low-bit signal pins LIO _ AD [7:0], the second eight-bit signal pins may be eight high-bit signal pins LIO _ AD [15:8], LIO _ AD [7:0] and LIO _ AD [15:8] are continuous eight-bit signal pins, respectively, for bus routing.

Alternatively, referring to fig. 3, the first bus controller 11 and the second bus controller 12 are electrically connected to the address data selection signal pin, the data read valid pin, and the data write valid pin of the parallel port controller 101 at the same time.

Specifically, as shown in fig. 3, for the extended scheme of the CAN bus, the first bus controller 11 and the second bus controller 12 are also electrically connected to the address data selection signal pin ADLOCK, the data read valid pin RDN, and the data write valid pin WRN of the parallel port controller 101 at the same time. Taking the working principle of the first bus controller 11 as an example, when the address data selection signal pin address defines a transmission address signal, the eight lower bit signal pins AD [7:0] are used for transmitting the address signal, and when the address data selection signal pin address defines a transmission data signal, the eight lower bit signal pins AD [7:0] are used for transmitting the data signal. When the data read valid pin RDN is active low, the first bus controller 11 reads data from the processor 10, and when the data write valid pin WRN is active low, the first bus controller 11 writes data to the processor 10. The operation principle of the second bus controller 12 is the same as that of the first bus controller 11, and is not described herein again.

The embodiment of the utility model provides a mainboard is still provided, the mainboard includes any kind of aforesaid extension structure. The expansion structure can be formed by taking a circuit board as a carrier, and fixing the processor 10, the first bus controller 11 and the second bus controller 12 on the circuit board in a welding manner to form an expansion mainboard. The motherboard provides two bus interfaces that can operate simultaneously. For example, two CAN buses CAN be operated simultaneously.

The embodiment of the utility model provides an electronic equipment is still provided, electronic equipment includes aforementioned arbitrary kind extension structure or mainboard. The expansion structure or the mainboard can be applied to electronic equipment such as a general computer or industrial control equipment and the like to meet the defect of insufficient bus interfaces. For example, in the field of automotive electronics, the above-mentioned extension structure or main board may be disposed in an ECU (Electronic Control Unit) to meet the requirement of externally connecting more sensors.

The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or terminal equipment comprising the element.

The expanded structure, the main board and the electronic device provided by the present invention are introduced in detail, and the principle and the implementation of the present invention are explained by applying specific examples, and the descriptions of the above examples are only used to help understanding the method and the core idea of the present invention; meanwhile, for the general technical personnel in the field, according to the idea of the present invention, there are changes in the specific implementation and application scope, to sum up, the content of the present specification should not be understood as the limitation of the present invention.

Claims

1. An extension architecture, characterized in that the extension architecture comprises a processor and at least two bus controllers;

2. The expansion fabric of claim 1, wherein the at least two bus controllers include a first bus controller and a second bus controller;

the first bus controller is electrically connected with a first group of eight-bit signal pins and a chip selection signal pin of the parallel port controller;

the second bus controller is electrically connected with a second group of eight-bit signal pins of the parallel port controller and GPIO pins of the processor.

3. The extension architecture of claim 2, wherein the first bus controller and the second bus controller are both CAN controllers, the extension architecture further comprising a first CAN transceiver and a second CAN transceiver;

4. The extension architecture of claim 3, wherein the CAN bus comprises an RX signal line for transmitting data to the first bus controller and the second bus controller, and a TX signal line for transmitting data to the first CAN transceiver and the second CAN transceiver.

5. The extension structure of claim 2, wherein the first set of eight bit signal pins are low eight bit signal pins and the second set of eight bit signal pins are high eight bit signal pins.

6. The expansion structure of claim 2, wherein the first bus controller and the second bus controller are electrically connected to an address data selection signal pin, a data read valid pin and a data write valid pin of the parallel port controller at the same time.

7. The extension architecture of claim 6, wherein the first bus controller and/or the second bus controller reads data from the processor when the data read active pin is active low;

8. The fabric of any one of claims 1 to 7, wherein the parallel port controller is a LIO controller or an ISA controller.

9. A motherboard, characterized in that it comprises an extension structure according to any one of claims 1-8.

10. An electronic device, characterized in that the electronic device comprises the extension structure of any one of claims 1-8 or the main board of claim 9.