CN216957458U

CN216957458U - Delay locked loop circuit

Info

Publication number: CN216957458U
Application number: CN202123025865.8U
Authority: CN
Inventors: 吴镇锋
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2021-12-03
Filing date: 2021-12-03
Publication date: 2022-07-12
Anticipated expiration: 2031-12-03

Abstract

The utility model discloses a delay locked loop circuit, which comprises a delay circuit, a phase detector and a counting control circuit, wherein the delay circuit is used for receiving a reference clock signal from the outside and delaying the reference clock signal to output a delay clock signal; the phase detector is used for receiving the reference clock signal and the delayed clock signal and detecting a phase difference of the reference clock signal and the delayed clock signal; the counting control circuit is used for generating a control delay signal according to the phase difference, wherein the delay circuit delays the reference clock signal according to the control delay signal to output a delay clock signal; the counting control circuit has a first mode with a first updating frequency and a second mode with a second updating frequency, and the first updating frequency is different from the second updating frequency.

Description

Delay locked loop circuit

Technical Field

The utility model belongs to the field of delay-locked loops (DLLs), and particularly relates to a delay-locked loop circuit with a plurality of modes.

Background

According to the related specifications of the current Dynamic Random Access Memory (DRAM), the DRAM product (especially, the Memory of the Fourth Generation Double-Data-Rate (DDR 4)) needs better voltage and power stability, for the faster and faster transmission speeds, even a small power change may cause jitter (jitter) of the output Data and degrade the eye diagram (eye diagram) of the output Data, and when the eye diagram of the output Data is too poor, the system cannot read out the correct Data, so that the system fails. Therefore, for the field of high transmission speed, a Delay-locked loop (DLL) circuit needs to be improved to make the data jitter less. The delay locked loop circuit is generally determined by the phase detector and the delay amount is adjusted by the counting control circuit. In which a continuous auto-refresh command (auto-refresh command) causes the dll circuit to consume a large amount of current, such large current consumption variation causes variation in internal power supply voltage, and a negative delay is generated in an output signal when the dll circuit switches from refresh to read data. Furthermore, the period and step size of the count control circuit of the dll circuit are fixed and cannot be adjusted quickly to accommodate large delay variations, for example, when a read command is received, data may not be aligned with the clock signal and jitter may occur. Therefore, a novel method and related architecture are needed to achieve the reduction of delay jitter and current variation and solve the problem without side effects or with less possibility of side effects.

SUMMERY OF THE UTILITY MODEL

In order to solve the above problems in the prior art, the present invention provides a delay locked loop circuit with multiple modes, which can effectively change the period and step size for different requirements, so as to solve the above problems.

An embodiment of the present invention discloses a dll circuit, including a delay circuit, a phase detector and a count control circuit, wherein the delay circuit is configured to receive a reference clock signal from the outside and delay the reference clock signal to output a delayed clock signal, the phase detector is configured to receive the reference clock signal and the delayed clock signal and detect a phase difference between the reference clock signal and the delayed clock signal to generate a phase difference signal, the count control circuit is configured to receive the phase difference signal and generate a control delay signal according to the phase difference signal, wherein the delay circuit delays the reference clock signal according to the control delay signal to output a delayed clock signal, and the count control circuit has a first mode and a second mode, when the counting control circuit is in the first mode, the counting control circuit has a first updating frequency, and when the counting control circuit is in the second mode, the counting control circuit has a second updating frequency, and the first updating frequency is different from the second updating frequency.

Compared with the prior art, the counting control circuit of the delay locked loop circuit has a plurality of modes (including a first mode and a second mode), the delay locked loop circuit can rapidly lock the delay by the second mode, the output signal does not generate negative delay when the data reading starts, and when the external circuit reads the data, the delay locked loop circuit is switched to the first mode again to reduce the delay jitter (jitter) which is not beneficial to reading the data. Furthermore, when the dll circuit is in standby mode, the mode with a lower refresh frequency can be selected to reduce the current consumption. With this configuration, the delay locked loop circuit of the present invention can achieve delay lock more quickly, and effectively reduce delay jitter and reduce the variation of current consumption.

Drawings

FIG. 1 is a diagram of a DLL circuit according to an embodiment of the present invention.

FIG. 2 is a diagram of a count control circuit having multiple modes according to an embodiment of the present invention.

FIG. 3 is a waveform diagram of a delayed clock signal output by a DLL circuit according to an embodiment of the present invention in different modes.

FIG. 4 is a waveform diagram of a delayed clock signal output by a DLL circuit according to an embodiment of the present invention in different modes.

Wherein the reference numerals are as follows:

delay locked loop circuit-10; a delay circuit-12; a phase detector-14; a count control circuit-16; delay locked loop delay line-18; data output control circuit-20.

Detailed Description

Referring to fig. 1, fig. 1 is a schematic diagram of a dll circuit 10 according to an embodiment of the present invention. As shown in FIG. 1, the DLL circuit 10 includes a delay circuit 12, a phase detector 14, and a count control circuit 16. The delay circuit 12 is configured to receive a reference clock signal (e.g., a reference clock signal of a Dynamic Random Access Memory (DRAM)) from the outside, and delay the reference clock signal to output a delayed clock signal, where the delayed clock signal is output to a clock tree (e.g., a clock tree of a DRAM), and the delayed clock signal is output from the clock tree by an output driving circuit. The phase detector 14 is configured to receive the reference clock signal and the delayed clock signal, detect a phase difference between the reference clock signal and the delayed clock signal, and generate a phase difference signal according to the phase difference. The count control circuit 16 is configured to receive the phase difference signal and generate a control delay signal according to the phase difference signal. For example, the delay circuit 12 includes a delay locked loop delay line 18 and a data output control circuit 20, the delay locked loop delay line 18 is configured to receive the control delay signal and delay the reference clock signal according to the control delay signal, and the data output control circuit 20 is configured to output the delayed clock signal. The count control circuit 16 has a first mode and a second mode, and the count control circuit 16 can switch between the first mode and the second mode according to the command requirement of the external circuit, and the difference between the first mode and the second mode is that at least one of the refresh frequency and the delay step of the two modes is different. For example, when the count control circuit 16 is in the first mode, it has a first update frequency and a first delay step, and when the count control circuit 16 is in the second mode, it has a second update frequency and a second delay step, and the first update frequency is lower than the second update frequency, and the first delay step is not greater than the second delay step.

The circuit connections of the delay locked loop circuit 10 are as shown in fig. 1: the reference clock signal is input into the delay locked loop delay line 18, the output end of the delay locked loop delay line 18 is connected with the input end of the data output control circuit 20, and the data output control circuit 20 outputs the delay clock signal; the reference clock signal and the delayed clock signal are input to the phase detector 14, the output of the phase detector 14 is connected to the input of the count control circuit 16, and the output of the count control circuit 16 is connected to the delay locked loop delay line 18. The delay locked loop delay line 18 and the data output control circuit 20 together form the delay circuit 12.

Referring to fig. 2, fig. 2 is a schematic diagram of a count control circuit 16 having multiple modes according to an embodiment of the utility model. As shown in fig. 2, the count control circuit 16 receives the phase difference signal and generates the control delay signal according to the phase difference signal, wherein the control delay signal can control the update frequency and the delay step of the dll delay line 18, in other words, the dll delay line 18 can adjust the update frequency and the delay step according to the control delay signal. Furthermore, the count control circuit 16 is further configured to receive an external circuit command and switch the first mode and the second mode according to the external circuit command. For example, when the external circuit command received by the count control circuit 16 is a lock command, the count control circuit 16 is controlled to be in the second mode, and the count control circuit 16 has a second update frequency and a second delay step. The count control circuit 16 controls the delay locked loop delay line 18 to perform delay locking using a second update frequency and a second delay step by the control delay signal, wherein the second update frequency may be higher than the first update frequency, and the second delay step may be not less than the first delay step, for example, the second update frequency is an after-edge update delay (labeled 8clk in fig. 2 for simplicity) of the reference clock signal for 8 times, and the second delay step is an adjustment delay of 20 picoseconds per update (labeled 20 picoseconds in fig. 2 for simplicity). For another example, when the external circuit command received by the count control circuit 16 is a read start command, the count control circuit 16 is controlled to be in the first mode, and the count control circuit 16 has a first update frequency and a first delay step. Similarly, the count control circuit 16 controls the delay locked loop delay line 18 to perform delay locking using a first update frequency and a first delay step by the control delay signal, wherein the first update frequency may be lower than the second update frequency, and the first delay step may be not greater than the second delay step, for example, the first update frequency is an edge post-update delay (denoted as 16clk in fig. 2 for simplicity) of the reference clock signal after 16 times, and the first delay step is an adjustment delay of 10 picoseconds per update (denoted as 10 picoseconds in fig. 2 for simplicity).

In addition, the count control circuit 16 can dynamically adjust different modes, where the different modes may further include more than two modes, and at least one of the update frequency and the delay step in one mode is different from the other modes. For example, when the external circuit command received by the count control circuit 16 is a standby command, the count control circuit 16 is controlled to be in a third mode, and the count control circuit 16 has a third update frequency and a third delay step. Similarly, the count control circuit 16 controls the delay locked loop delay line 18 to perform delay locking by using a third update frequency and a third delay step by using the control delay signal, wherein the third update frequency is an update delay (denoted as 32clk in fig. 2 for simplicity) after 32 edges of the reference clock signal, and the third delay step is 10 picoseconds (denoted as 10 picoseconds in fig. 2 for simplicity) identical to the first delay step. In some embodiments, the count control circuit 16 comprises a logic circuit for receiving the external circuit instruction, which is well known in the art, and therefore, the details thereof are not described herein.

According to the above configuration, the dll circuit 10 of the present invention can adjust different modes to have different update frequencies and delay steps according to the requirement of the external circuit command, for example, when the external circuit command received by the count control circuit 16 is a pending command, the update frequency is adjusted to a lower update frequency (such as after-edge update delay of the reference clock signal after 32 times) to reduce the power consumed by the dll circuit 10. Furthermore, the first mode for the read start instruction and the second mode for the lock instruction may also have the corresponding update frequency and delay step size set. Referring to fig. 3 and 4 together, fig. 3 and 4 are waveform diagrams of a delay locked loop circuit 10 outputting a delay clock signal in different modes according to an embodiment of the utility model.

As shown in fig. 3, after the delay locked loop circuit 10 is in the delay locked state, the external circuit refreshes (refreshes) the delay state, in which the delay clock signal is delayed from the reference clock signal for a longer time (e.g. 150 picoseconds behind), in fig. 3, the delay locked loop circuit 10 uses the edge post-update delay (denoted as frequency: 16clk in fig. 3 for simplicity) with the update frequency of 16 times of the reference clock signal, and the delay step size is adjusted by 10 picoseconds per update delay (denoted as step size: 10 picoseconds in the figure for simplicity), and after a while, the delay locked loop circuit 10 locks the delay of the delay clock signal, and the external circuit enters a read data state, the delay clock signal has a negative delay (i.e. leads the reference clock signal), the delay locked loop circuit 10 uses the update frequency of 16 times of the edge post-update delay (denoted as frequency: 16clk in fig. 3, for simplicity), and the delay step size is adjusted by 10 picoseconds for each update delay (labeled step size in fig. 3: 10 picoseconds for simplicity) so that the negative delay of the delayed clock signal can be slowly adjusted to delay lock. Wherein, the larger the negative delay at the beginning of reading data, the larger the delay jitter will be.

Similarly, as shown in FIG. 4, after the delay locked loop circuit 10 is delayed, the external circuit refreshes (refresh) the delay state, in which the delayed clock signal is delayed from the reference clock signal for a longer time, but when the count control circuit 16 receives a lock command, the count control circuit 16 is controlled to be in the second mode, and the count control circuit 16 has a second update frequency and a second delay step. Wherein the second update frequency is the post-update delay (labeled frequency: 8clk in FIG. 4 for simplicity) over 8 edges of the reference clock signal, and the second delay step is the delay adjustment of 20 picoseconds per update (labeled step: 20 picoseconds in FIG. 4 for simplicity). The update frequency and the delay step size of the second mode lock the delay of the delayed clock signal in a shorter time compared to fig. 3. It should be noted that the delay lock in the second mode generates jitter (jitter) due to the high update frequency and large delay step, however, the jitter has a large effect only in the read data state, and the delay jitter in the refresh state has a small effect. After the refresh is finished, the external circuit enters a read data state, the delay clock signal has a negative delay, and since the delay lock in the second mode is delayed and locked quickly due to the higher update frequency and the larger delay step size, the count control circuit 16 receives a read start command after the read data starts, the count control circuit 16 is controlled to be in the first mode, and the count control circuit 16 has a first update frequency and a first delay step size, wherein the first update frequency is the update delay after 16 edges of the reference clock signal (marked as frequency: 16 in fig. 4 for simplicity), and the first delay is the adjustment of each update delay by 10 picoseconds (marked as step size: 10 picoseconds in fig. 4 for simplicity). Thus, the mode is switched to the first mode, so that the delay locking of the delay clock signal can be maintained without generating jitter, and an external circuit can read data conveniently.

Compared with the prior art, the counting control circuit of the delay locked loop circuit has a plurality of modes (including a first mode and a second mode), the delay locked loop circuit can rapidly lock the delay through the second mode, the output signal does not generate negative delay when the data reading starts, when the external circuit reads the data, the delay locked loop circuit is switched to the first mode again to reduce the delay jitter which is not beneficial to the data reading, and when the delay locked loop circuit is in a standby state, the mode with lower updating frequency can be selected to reduce the current consumption. With this configuration, the delay locked loop circuit of the present invention can achieve delay lock more quickly, and effectively reduce delay jitter and reduce the variation of current consumption.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A dll circuit, comprising:

a delay circuit for receiving a reference clock signal from the outside and delaying the reference clock signal to output a delayed clock signal;

a phase detector for receiving the reference clock signal and the delayed clock signal and detecting a phase difference between the reference clock signal and the delayed clock signal to generate a phase difference signal; and

a counting control circuit for receiving the phase difference signal and generating a control delay signal according to the phase difference signal,

wherein the delay circuit delays the reference clock signal according to the control delay signal to output a delayed clock signal;

the counting control circuit has a first mode and a second mode, and has a first update frequency when the counting control circuit is in the first mode, and has a second update frequency when the counting control circuit is in the second mode, and the first update frequency is different from the second update frequency.

2. The dll circuit of claim 1, wherein the delay circuit comprises:

a delay locked loop delay line for receiving the control delay signal and delaying the reference clock signal according to the control delay signal; and

and the data output control circuit is used for outputting the delay clock signal.

3. The dll circuit of claim 1, wherein when the dll circuit receives a lock instruction, the count control circuit is controlled to be in the second mode such that the count control circuit has the second update frequency.

4. The dll circuit of claim 1, wherein when the dll circuit receives a read start command, the count control circuit is controlled to be in the first mode such that the count control circuit has the first update frequency.

5. The dll circuit of claim 1, wherein when the dll circuit receives a standby command, the counter control circuit is controlled to be in the first mode, such that the counter control circuit has the first update frequency.

6. The dll circuit of claim 1, wherein the second update frequency is 2 times the first update frequency.

7. The dll circuit of claim 1, wherein the first update frequency is a post-edge update delay of the reference clock signal over 32 times.

8. The dll circuit of claim 1, wherein the first update frequency is a post-edge update delay of the reference clock signal over 16 times.

9. The dll circuit of claim 1, wherein the second update frequency is a post-edge update delay of the reference clock signal over 8 times.

10. The dll circuit of claim 1, wherein the count control circuit has a first delay step when the count control circuit is in the first mode, has a second delay step when the count control circuit is in the second mode, and the first delay step is not greater than the second delay step.

11. The dll circuit of claim 10, wherein the first delay step is 10 picoseconds per update delay adjustment.

12. The dll circuit of claim 10, wherein the second delay step is 20 ps per update delay adjustment.

13. The dll circuit of claim 10, wherein when the dll circuit receives a lock instruction, the count control circuit is controlled to be in the second mode such that the count control circuit has the second delay step.

14. The dll circuit of claim 10, wherein when the dll circuit receives a read start command, the count control circuit is controlled to be in the first mode such that the count control circuit has the first delay step.

15. The dll circuit of claim 10, wherein the count control circuit further has a third mode, and when the count control circuit is in the third mode, the count control circuit has a third update frequency and a third delay step, and at least one of the third update frequency and the third delay step is different from the first update frequency, the second update frequency, and the first delay step and the second delay step.