CN216449690U

CN216449690U - Chip testing device and system

Info

Publication number: CN216449690U
Application number: CN202123126931.0U
Authority: CN
Inventors: 萨斌; 王刚
Original assignee: Chipone Technology Beijing Co Ltd
Current assignee: Chipone Technology Beijing Co Ltd
Priority date: 2021-12-13
Filing date: 2021-12-13
Publication date: 2022-05-06
Anticipated expiration: 2031-12-13

Abstract

The utility model relates to a chip testing device and a system, wherein the device comprises: a device main body; the mobile industry processor interface MIPI chip is arranged on the device main body and comprises a first interface and a second interface, the first interface is used for receiving test data, the second interface is connected to a chip to be tested, and the second interface is used for transmitting the test data to the chip to be tested so as to test the chip to be tested. The chip testing device provided by the embodiment of the utility model tests the chip to be tested through the mature MIPI chip, can effectively reduce the complexity of chip testing and reduce the cost.

Description

Chip testing device and system

Technical Field

The utility model relates to the technical field of testing, in particular to a chip testing device and system.

Background

The most basic links of chip manufacturing include chip design, tape-out, packaging and testing, wherein the testing is the last concern of product quality, and if no good testing exists, the PPM (million failure rate) of the product is too high, which causes a significant quality problem. At present, a test system for testing a chip is complex, the test system is complex to build, and the cost is high.

SUMMERY OF THE UTILITY MODEL

According to an aspect of the present invention, there is provided a chip testing apparatus, the apparatus including:

a device main body;

the mobile industry processor interface MIPI chip is arranged on the device main body and comprises a first interface and a second interface, the first interface is used for receiving test data, the second interface is connected to a chip to be tested, and the second interface is used for transmitting the test data to the chip to be tested so as to test the chip to be tested.

In a possible implementation manner, the first interface includes an IIC interface, the first interface is connected to a first register configuration device, the first register configuration device communicates with an upper computer through a serial interface to receive test data, and the first register configuration device sends the test data to the MIPI chip through the first interface, where the test data is used for configuring a register of the MIPI chip.

In a possible embodiment, the serial interface includes any one of a UART interface, a CAN bus interface, an SPI interface, and a USB interface.

In one possible implementation, the second interface includes an LVDS interface.

In a possible implementation manner, the chip testing apparatus further includes a second register configuration apparatus, where the second register configuration apparatus communicates with an upper computer through a serial interface to receive parameter adjustment data, and is used to send the parameter adjustment data to the MIPI chip through an IIC interface, and the parameter adjustment data is used to configure a register of the MIPI chip.

In a possible implementation, the chip to be tested includes a timing control chip.

In one possible embodiment, the test data includes graphical data.

According to an aspect of the present invention, there is provided a chip testing system, the system including:

the upper computer is used for providing test data;

the first register configuration device is communicated with the upper computer through a serial interface to receive test data, and sends the test data to the MIPI chip through the first interface, wherein the test data is used for configuring the registers of the MIPI chip;

the chip testing device.

In one possible embodiment, the system further comprises an oscilloscope and/or a multimeter.

In various aspects of the embodiment of the utility model, the mature MIPI chip is used for testing the chip to be tested, so that the complexity of chip testing can be effectively reduced, and the cost is reduced.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the utility model, as claimed. Other features and aspects of the present invention will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the utility model and, together with the description, serve to explain the principles of the utility model.

Fig. 1 shows a block diagram of a chip testing apparatus according to an embodiment of the present invention.

FIG. 2 shows a schematic diagram of a chip test system according to an embodiment of the utility model.

Detailed Description

Various exemplary embodiments, features and aspects of the present invention will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

In the description of the present invention, it is to be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be construed as limiting the present invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, and may mean including any one or more elements selected from the group consisting of A, B and C.

Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present invention. It will be understood by those skilled in the art that the present invention may be practiced without some of these specific details. In some instances, methods, procedures, components, and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present invention.

For example, the signal generator and the pattern generator which are specially designed are generally adopted in the related art to test the chip to be tested, the signal generator and the pattern generator which are adopted in the related art are generally specially designed for the chip to be tested, the composition of the signal generator and the pattern generator is complicated, and the building is difficult.

The chip testing device provided by the embodiment of the utility model comprises: a device main body; the Mobile Industry Processor Interface (MIPI) chip is arranged on the device main body and comprises a first interface and a second interface, the first interface is used for receiving test data, the second interface is connected to a chip to be tested, and the second interface is used for transmitting the test data to the chip to be tested so as to test the chip to be tested. The chip to be tested is tested through the mature MIPI chip, so that the complexity of chip testing can be effectively reduced, and the cost is reduced.

Referring to fig. 1, fig. 1 is a block diagram of a chip testing apparatus according to an embodiment of the utility model.

The chip testing device of the embodiment of the utility model can test various types of chips, including but not limited to a time sequence control chip.

As shown in fig. 1, the apparatus includes:

a device main body 10;

a mobile industry processor interface MIPI chip 110 disposed on the device body 10, wherein the MIPI chip 110 includes a first interface 120 and a second interface 130, the first interface 120 is used for receiving test data, the second interface 130 is connected to a chip 20 to be tested, and the second interface 130 is used for transmitting the test data to the chip 20 to be tested, so as to test the chip 20 to be tested.

The device main body 10 according to an embodiment of the present invention may include a Printed Circuit Board (PCB), and the MIPI chip 110, the first interface 120, and the second interface 130 may be disposed on the PCB to fix and assemble the MIPI chip 110, the first interface 120, and the second interface 130 to achieve electrical connection.

The test data in the embodiment of the present invention may include graphic data, such as checkerboard patterns, bar patterns, and the like, where the graphic data is related to a pattern (pattern mode) configured when the MIPI chip leaves a factory, for example, when the MIPI chip leaves a factory, a pattern for initialization or chip calibration, such as a checkerboard pattern, may be configured in advance in an initialization circuit, and the MIPI chip may output a corresponding graphic by triggering an input signal, and of course, the input graphic may be the same as the preset pattern, or may be a simplified version of a graphic, such as a bar pattern, and the like, which is not limited in the embodiment of the present invention. Of course, the test data may also include signals related to chip testing, such as a voltage signal, a frequency signal, and the like, which is not limited in the embodiments of the present invention. The embodiment of the utility model utilizes a mature MIPI chip to replace a complex signal generator and a complex pattern generator in the related technology to test the chip to be tested, thereby reducing the test complexity and the test cost.

In one possible implementation, the first interface 120 may include an Inter-Integrated Circuit (IIC) interface, where the IIC is a serial communication bus using a multi-master-slave architecture, and the IIC bus generally has two signal lines, one is a bidirectional data line SDA, and the other is a clock line SCL. All serial data SDA connected to IIC bus equipment are connected to SDA of the bus, and clock lines SCL of all the equipment are connected to SCL of the bus. For specific introduction of the IIC bus and the IIC interface, please refer to the description of the related art, which is not repeated herein.

Referring to fig. 2, fig. 2 is a schematic diagram illustrating a chip testing system according to an embodiment of the utility model.

In one possible implementation, as shown in fig. 2, the first interface 120 is connected to a first register configuration device 30, the first register configuration device 30 communicates with the upper computer 40 through a serial interface to receive test data, and the first register configuration device 30 sends the test data to the MIPI chip 110 through the first interface 120, where the test data is used for configuring registers of the MIPI chip 110.

The first register configuration device 30 according to the embodiment of the present invention may be implemented by using related technologies, and for a specific implementation manner of the first register configuration device 30, the embodiment of the present invention is not limited, and the first register configuration device 30 may interface other types of serial interfaces (a UART interface, a CAN bus interface, an SPI interface, and a USB interface) with an IIC interface, and convert data from the other types of serial interfaces into data in an IIC format, for example, the upper computer 40 sends test data to the first interface, i.e., the IIC interface, of the MIPI chip 110 through the USB interface, and since data cannot be directly transmitted between different types of interfaces, the first register configuration device 30 is configured in the embodiment of the present invention to implement conversion between the USB interface and the IIC interface, so as to successfully transmit the test data to the MIPI chip. For example, the first register configuration device 30 may transmit the test data to a register module (including a plurality of registers) of the MIPI chip 110 through the IIC interface to modify values of the registers, thereby implementing transmission of the test data to the MIPI chip.

The upper computer 40 of the embodiment of the present invention may be a terminal device, where the terminal device may be a User Equipment (UE), a mobile device, a User terminal, a handheld device, a computing device, or a vehicle-mounted device, and for example, some terminals are: a Mobile Phone (Mobile Phone), a tablet computer, a notebook computer, a palm computer, a Mobile Internet Device (MID), a wearable device, a Virtual Reality (VR) device, an Augmented Reality (AR) device, a wireless terminal in Industrial Control (Industrial Control), a wireless terminal in unmanned driving (self driving), a wireless terminal in Remote Surgery (Remote medical Surgery), a wireless terminal in Smart Grid, a wireless terminal in Transportation Safety, a wireless terminal in Smart City (Smart City), a wireless terminal in Smart Home (Smart Home), a wireless terminal in car networking, and the like. For example, the server may be a local server or a cloud server.

In one example, host computer 40 may also be other devices that include processing components including, but not limited to, a single processor, or discrete components, or a combination of a processor and discrete components. The processor may comprise a controller having functionality to execute instructions in an electronic device, which may be implemented in any suitable manner, e.g., by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic components. Within the processor, the executable instructions may be executed by hardware circuits such as logic gates, switches, Application Specific Integrated Circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

In one possible implementation, the second interface 130 includes an LVDS (Low Voltage Differential Signaling) interface, also called an RS-644 bus interface. LVDS is a low swing differential signaling technique that enables signals to be transmitted over differential PCB wire pairs or balanced cables at a rate of several hundred Mbps, with low voltage swing and low current drive output achieving low noise and low power consumption. Taking a liquid crystal display as an example, in the liquid crystal display, the LVDS interface circuit is located between the Scaler circuit of the liquid crystal display and the liquid crystal panel, and is composed of an LVDS signal transmitting circuit (transmitter) on the main board side and a receiving circuit (receiver) on the liquid crystal panel side. The LVDS transmitter converts the TTL level parallel RGB data signals and the control signals into low voltage serial LVDS signals, and then transmits the signals to the LVDS receiver on the liquid crystal panel side through a flexible cable (flat cable) between the main board and the liquid crystal panel, and the LVDS receiver converts the serial signals into TTL level parallel signals and transmits the TTL level parallel signals to a subsequent circuit (generally, a timing controller TCON, including a timing control chip). For a detailed description of the LVDS interface, please refer to the description of the related art, which is not repeated herein.

Illustratively, the chip to be tested according to the embodiment of the present invention may include a chip having an LVDS interface.

In a possible implementation manner, as shown in fig. 2, the chip testing apparatus may further include a second register configuration apparatus 50, where the second register configuration apparatus 50 communicates with the upper computer 40 through a serial interface to receive parameter adjustment data, which is used for sending the parameter adjustment data to the MIPI chip 110 through an IIC interface, and the parameter adjustment data is used for configuring registers of the MIPI chip 110. Illustratively, the parameter adjustment data of the embodiment of the present invention may include, for example, the fluctuation range of the pattern amplitude, the fluctuation range of the voltage, the current, the frequency, and the like. The embodiment of the present invention does not limit the specific implementation manner of the second register configuring apparatus 50, and for the description of the second register configuring apparatus 50, please refer to the introduction of the first register configuring apparatus 30.

The second register configuration device 50 is arranged, so that the method and the device can adapt to chips to be tested of different manufacturers and different models, the flexibility and the adaptability of the test of the chips to be tested are improved, the chips to be tested of different manufacturers and different models, such as time sequence control chips, are different in manufacturing, and therefore certain fluctuation exists in parameters of the chips to be tested, and the corresponding register values in the chips to be tested 20 are adjusted through the second register configuration device 50, so that the method and the device can adapt to different chips to be tested, and whether the chips to be tested have problems or not can be checked.

In a possible implementation manner, as shown in fig. 2, in the embodiment of the present invention, an oscilloscope 60 and a multimeter 70 may be configured to observe parameters of the chip 20 to be tested, for example, the oscilloscope 60 may be used to check an output waveform of the chip 20 to be tested, and compare the output waveform with a standard waveform, or determine whether the chip to be tested has a problem according to experience. By way of example, multimeters, also known as multi-purpose meters, tri-purpose meters, multi-purpose meters, and the like, typically have a primary purpose of measuring voltage, current, and resistance. The multimeter is divided into a pointer multimeter and a digital multimeter according to the display mode. The universal meter can measure direct current, direct current voltage, alternating current, alternating voltage, resistance, audio level and the like, and can also measure alternating current, capacitance, inductance, parameters (such as beta) of a semiconductor and the like, and the universal meter 70 can measure various electrical parameters of the chip 20 to be measured and judge whether the chip 20 to be measured has problems according to standard electrical parameters or experience.

According to an aspect of the present invention, there is provided a chip testing system, as shown in fig. 2, the system including:

the upper computer 40 is used for providing test data;

the first register configuration device 30 is in communication with the upper computer 40 through a serial interface to receive test data, and sends the test data to the MIPI chip 110 through the first interface 120, wherein the test data is used for configuring registers of the MIPI chip 110;

the chip testing device.

In one possible embodiment, the system further includes an oscilloscope 60 and/or a multimeter 70.

A chip testing apparatus, the apparatus comprising:

a device main body 10;

The embodiment of the utility model tests the chip to be tested through the mature MIPI chip, can effectively reduce the complexity of a chip testing system and reduce the cost.

In a possible implementation manner, the first interface 120 includes an IIC interface, the first interface 120 is connected to a first register configuration device 30, the first register configuration device 30 communicates with the upper computer 40 through a serial interface to receive test data, and the first register configuration device 30 sends the test data to the MIPI chip 110 through the first interface 120, where the test data is used for configuring registers of the MIPI chip 110.

In one possible implementation, the second interface 130 includes an LVDS interface.

In a possible implementation manner, the chip testing apparatus further includes a second register configuration apparatus 50, where the second register configuration apparatus communicates with the upper computer 40 through a serial interface to receive parameter adjustment data for sending the parameter adjustment data to the MIPI chip 110 through an IIC interface, and the parameter adjustment data is used to configure a register of the MIPI chip 110.

In one possible embodiment, the chip 20 to be tested includes a timing control chip.

In one possible embodiment, the test data includes graphical data.

For brevity, the detailed description of the chip testing apparatus refers to the foregoing description and will not be repeated herein.

Having described embodiments of the present invention, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A chip testing apparatus, the apparatus comprising:

a device main body;

2. The apparatus of claim 1, wherein the first interface comprises an IIC interface, the first interface is connected to a first register configuration apparatus, the first register configuration apparatus communicates with an upper computer through a serial interface to receive test data, the first register configuration apparatus sends the test data to the MIPI chip through the first interface, and the test data is used to configure registers of the MIPI chip.

3. The apparatus of claim 2, wherein the serial interface comprises any one of a UART interface, a CAN bus interface, an SPI interface, and a USB interface.

4. The apparatus of claim 1, wherein the second interface comprises an LVDS interface.

5. The apparatus of claim 1, wherein the chip testing apparatus further comprises a second register configuration apparatus, the second register configuration apparatus communicating with an upper computer through a serial interface to receive parameter adjustment data for sending the parameter adjustment data to the MIPI chip through an IIC interface, the parameter adjustment data for configuring registers of the MIPI chip.

6. The apparatus of claim 1, wherein the chip under test comprises a timing control chip.

7. The apparatus of claim 1, wherein the test data comprises graphical data.

8. A chip test system, the system comprising:

the upper computer is used for providing test data;

the chip testing device according to any one of claims 1 to 7.