CN216118766U - Protocol converter of USB bus and PC104 bus - Google Patents

Protocol converter of USB bus and PC104 bus Download PDF

Info

Publication number
CN216118766U
CN216118766U CN202122732829.9U CN202122732829U CN216118766U CN 216118766 U CN216118766 U CN 216118766U CN 202122732829 U CN202122732829 U CN 202122732829U CN 216118766 U CN216118766 U CN 216118766U
Authority
CN
China
Prior art keywords
bus
control circuit
usb
protocol converter
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202122732829.9U
Other languages
Chinese (zh)
Inventor
罗贤全
游玲
单成进
邱烨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yango University
Original Assignee
Yango University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yango University filed Critical Yango University
Priority to CN202122732829.9U priority Critical patent/CN216118766U/en
Application granted granted Critical
Publication of CN216118766U publication Critical patent/CN216118766U/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

The utility model discloses a protocol converter of a USB bus and a PC104 bus, which comprises an FPGA main control circuit, a USB interface, an MCU control circuit and a PC104 bus interface, wherein the FPGA main control circuit is respectively and electrically connected with the MCU control circuit and the PC104 bus interface, and the MCU control circuit is electrically connected with the USB interface. The utility model realizes the conversion from the PC104 bus protocol to the USB bus protocol, and the USB bus is used for realizing the communication with the computer through plug and play, thereby realizing the test and fault diagnosis of hardware without disassembling a hardware card, having great convenience, the converter is used as a function test card, the system not only has the advantage that the USB device can be used for plug and play hot plugging, but also has the high reliability and high expansibility of the PC104 bus device, and the single MCU control circuit is arranged for processing the receiving and sending tasks of the USB bus, thereby reducing the operation pressure and the IO interface pressure of the FPGA main control circuit.

Description

Protocol converter of USB bus and PC104 bus
Technical Field
The utility model relates to the technical field of protocol conversion, in particular to a protocol converter of a USB bus and a PC104 bus.
Background
The PC104 is an industrial computer bus standard, and due to the advantages of its unique stacked connection mode, high reliability, high scalability, low power consumption, and its high compatibility with PC software, the hardware boards of many application systems all adopt PC104 bus interfaces, which makes the PC104 bus widely used in military and industrial fields. However, due to the pinhole engagement of the PC104 and the large number of pins, the hardware using the PC104 is inconvenient because of the large disassembly workload during testing and maintenance.
SUMMERY OF THE UTILITY MODEL
The technical problem to be solved by the utility model is as follows: a protocol converter for USB bus and PC104 bus can realize simple test and communication of PC104 bus by computer.
In order to solve the technical problems, the utility model adopts a technical scheme that: a protocol converter of a USB bus and a PC104 bus comprises an FPGA main control circuit, a USB interface and a PC104 bus interface, wherein the FPGA main control circuit is electrically connected with the USB interface and the PC104 bus interface respectively.
Furthermore, the number of the USB interfaces is multiple, and the FPGA main control circuit is electrically connected with each USB interface respectively.
Furthermore, the USB interface control circuit also comprises an MCU control circuit, and the FPGA main control circuit is electrically connected with the USB interface through the MCU control circuit.
Further, the MCU control circuit includes a microprocessor U3 integrated with the USB engine.
Further, the power supply circuit comprises a voltage conversion circuit, and the voltage conversion circuit is electrically connected with the FPGA main control circuit so as to supply power to the FPGA main control circuit after power taking conversion.
Further, the voltage conversion circuit takes power from a USB bus interface and/or a PC104 bus interface.
Furthermore, the power supply circuit further comprises a selection circuit, the selection circuit is provided with two selection ends and a public end, the two selection ends are respectively and electrically connected with the USB bus interface and the PC104 bus interface, and the public end is electrically connected with the voltage conversion circuit.
Furthermore, the output end of the voltage conversion circuit is grounded after passing through the current-limiting resistor and the power indicator lamp.
Furthermore, the output end of the voltage conversion circuit is grounded after passing through the first filter capacitor, and the input end of the voltage conversion circuit is grounded after passing through the second filter capacitor.
The utility model has the beneficial effects that: the converter is used as a function test board card, so that the system not only has the advantage that USB equipment can be plugged and plugged in and out for hot plug, but also has high reliability and high expansibility of PC104 bus equipment, and an independent MCU control circuit is arranged for processing the receiving and transmitting tasks of the USB bus, so that the operation pressure and the IO interface pressure of an FPGA main control circuit are reduced.
Drawings
FIG. 1 is a block diagram of a protocol converter for a USB bus and a PC104 bus according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a selection circuit in the power circuit according to an embodiment of the present invention;
fig. 3 is a circuit diagram of a voltage converting circuit in a power circuit according to an embodiment of the utility model.
Detailed Description
In order to explain technical contents, achieved objects, and effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.
Referring to fig. 1 to fig. 3, an embodiment of the present invention provides a protocol converter for a USB bus and a PC104 bus, including an FPGA main control circuit, a USB interface, an MCU control circuit, and a PC104 bus interface, where the FPGA main control circuit is electrically connected to the MCU control circuit and the PC104 bus interface, respectively, and the MCU control circuit is electrically connected to the USB interface.
As can be seen from the above description, the beneficial effects of the present invention are: the converter is used as a function test board card, so that the system not only has the advantage that USB equipment can be plugged and plugged in and out for hot plug, but also has high reliability and high expansibility of PC104 bus equipment, and an independent MCU control circuit is arranged for processing the receiving and transmitting tasks of the USB bus, so that the operation pressure and the IO interface pressure of an FPGA main control circuit are reduced.
Furthermore, the number of the USB interfaces is multiple, and the FPGA main control circuit is electrically connected with each USB interface respectively.
As can be seen from the above description, by providing a plurality of serial interfaces, serial data can be split and transmitted through a plurality of serial buses and then reassembled at the protocol converter, thereby improving the conversion efficiency of the protocol converter.
Further, the MCU control circuit includes a microprocessor U3 integrated with the USB engine.
As can be seen from the above description, the MCU control circuit integrates the USB engine, and a separate USB chip is not required to be arranged for transceiving the USB bus.
Further, the MCU control circuit also comprises a memory chip with the model number of 24LC01, and the microprocessor is electrically connected with the memory chip.
As can be seen from the above description, the memory chip is specifically a 24LC01 chip, so as to realize that the firmware can be programmed online.
Further, the power supply circuit comprises a voltage conversion circuit, and the voltage conversion circuit is electrically connected with the FPGA main control circuit so as to supply power to the FPGA main control circuit after power taking conversion.
According to the description, the voltage conversion circuit supplies power to the FPGA main control circuit, so that an externally input power supply can be converted into a power supply suitable for the FPGA main control circuit, and the model selection range of the FPGA main control circuit is expanded.
Further, the voltage conversion circuit takes power from a USB bus interface and/or a PC104 bus interface.
According to the description, the voltage conversion circuit gets power from the interface, an independent power interface is omitted, the cost is reduced, the step of plugging and unplugging the power supply is omitted, and the complexity of operation is reduced.
Furthermore, the power supply circuit further comprises a selection circuit, the selection circuit is provided with two selection ends and a public end, the two selection ends are respectively and electrically connected with the USB bus interface and the PC104 bus interface, and the public end is electrically connected with the voltage conversion circuit.
From the above description, the PC104 bus is used for supplying power when the power supply requirement is large, the USB bus is used for supplying power when the power supply requirement is small, and the two modes are switched by the selection circuit to meet different power supply requirements.
Furthermore, the output end of the voltage conversion circuit is grounded after passing through the current-limiting resistor and the power indicator lamp.
As can be seen from the above description, the power indicator indicates whether the protocol converter has the working voltage, and can indicate whether the protocol converter is powered on.
Furthermore, the output end of the voltage conversion circuit is grounded after passing through the first filter capacitor, and the input end of the voltage conversion circuit is grounded after passing through the second filter capacitor.
From the above description, the filter capacitor ensures the stability of the input and output of the voltage conversion circuit.
The protocol converter of the USB bus and the PC104 bus is mainly applied to simply testing and communicating PC104 bus equipment by adopting a computer, and can also be applied to establishing communication with other equipment adopting the USB bus and the PC104 bus equipment.
Example one
Referring to fig. 1, the protocol converter of this embodiment includes a power circuit, a PC104 bus interface, an FPGA (Field-programmable gate array) main control circuit, an MCU control circuit and a plurality of USB bus interfaces, where the MCU control circuit is electrically connected to the FPGA main control circuit and each USB bus interface, so that the MCU control circuit can receive and transmit data from and to the USB bus interfaces and send the received data to the FPGA circuit according to a certain format for storage, the FPGA main control circuit is electrically connected to the PC104 bus interface, so that the FPGA main control circuit converts data sent by the USB bus interfaces into PC104 data packets and sends the PC104 data packets to the PC104 bus, and converts data interfaced with the PC104 bus interface into data of the USB bus interface and sends the data to the MCU control circuit.
The FPGA master control circuit includes a computer program stored in the FPGA master control circuit and operable on the FPGA master control circuit, and the controller implements the steps of the first embodiment when executing the computer program.
The MCU master control circuit comprises a microprocessor U3 and a memory chip U1, the microprocessor U3 is electrically connected with the FPGA master control circuit, the memory chip U1 and each USB circuit respectively, the microprocessor U3 adopts a CY7C68013 chip of an integrated USB engine, and the memory chip U1 specifically adopts a 24LC01 chip, so that online programming of firmware is realized.
2-3, the power supply circuit includes a selection switch J3, two selection terminals IN1 and IN2 of the selection switch J3 are respectively electrically connected with the power supply terminal +5V of the PC104 bus interface and the power supply terminal ADD of the USB bus interface, the common terminals OUT1 and OUT2 are input to the input terminal IN of the voltage conversion chip U2, and the output terminal OUT of the voltage conversion chip U2 is respectively electrically connected with the FPGA main control circuit and the USB control circuit to provide the converted 3.3V voltage for the two. According to the actual power supply requirement, when the power supply requirement is large, the PC104 bus is used for supplying power, when the power supply requirement is small, the USB bus is used for supplying power, and the two modes are switched through the switch J3 to meet different power supply requirements.
The output end OUT of the voltage conversion chip U2 is grounded after passing through the current-limiting resistor R8 and the power indicator lamp D8, when the protocol converter is powered on, the power indicator lamp D8 is lightened to indicate the working state of the protocol converter, the output end of the voltage conversion circuit is grounded after passing through the first filter capacitor C6, and the input end of the voltage conversion circuit is grounded after passing through the second filter capacitor C7, so that the stability of power input and output is ensured.
In summary, the protocol converter for the USB bus and the PC104 bus provided by the present invention realizes conversion from the PC104 bus protocol to the USB bus protocol, and communicates with a computer through the USB bus by plug and play, so that hardware testing and fault diagnosis can be realized without disassembling a hardware card, and great convenience is provided.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent changes made by using the contents of the present specification and the drawings, or applied directly or indirectly to the related technical fields, are included in the scope of the present invention.

Claims (9)

1. A protocol converter of USB bus and PC104 bus is characterized in that: the FPGA main control circuit is electrically connected with the MCU control circuit and the PC104 bus interface respectively, and the MCU control circuit is electrically connected with the USB interface.
2. The protocol converter of claim 1, wherein the protocol converter comprises: the USB interface is a plurality of, FPGA master control circuit electricity respectively connects each USB interface.
3. The protocol converter of claim 1, wherein the protocol converter comprises: the MCU control circuit comprises a microprocessor integrated with the USB engine.
4. A protocol converter for USB bus and PC104 bus according to claim 3, wherein: the MCU control circuit further comprises a memory chip with the model number of 24LC01, and the microprocessor is electrically connected with the memory chip.
5. The protocol converter of claim 1, wherein the protocol converter comprises: the FPGA control circuit further comprises a power circuit, the power circuit comprises a voltage conversion circuit, and the output end of the voltage conversion circuit is electrically connected with the FPGA main control circuit.
6. The protocol converter of claim 5, wherein the protocol converter comprises: the input end of the voltage conversion circuit is electrically connected with the power supply end of the USB bus interface and/or the power supply end of the PC104 bus interface.
7. The protocol converter of claim 6, wherein the protocol converter comprises: the power supply circuit further comprises a selection circuit, the selection circuit is provided with two selection ends and a public end, the two selection ends are respectively and electrically connected with the USB bus interface and the PC104 bus interface, and the public end is electrically connected with the voltage conversion circuit.
8. The protocol converter of claim 5, wherein the protocol converter comprises: the output end of the voltage conversion circuit is grounded after passing through the current-limiting resistor and the power indicator lamp.
9. The protocol converter of claim 5, wherein the protocol converter comprises: the output end of the voltage conversion circuit is grounded after passing through the first filter capacitor, and the input end of the voltage conversion circuit is grounded after passing through the second filter capacitor.
CN202122732829.9U 2021-11-09 2021-11-09 Protocol converter of USB bus and PC104 bus Active CN216118766U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202122732829.9U CN216118766U (en) 2021-11-09 2021-11-09 Protocol converter of USB bus and PC104 bus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202122732829.9U CN216118766U (en) 2021-11-09 2021-11-09 Protocol converter of USB bus and PC104 bus

Publications (1)

Publication Number Publication Date
CN216118766U true CN216118766U (en) 2022-03-22

Family

ID=80714912

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202122732829.9U Active CN216118766U (en) 2021-11-09 2021-11-09 Protocol converter of USB bus and PC104 bus

Country Status (1)

Country Link
CN (1) CN216118766U (en)

Similar Documents

Publication Publication Date Title
CN100468378C (en) SPI apparatus telecommunication circuit
CN101404001B (en) Serial port signal and USB signal compatible control circuit board and communication data cable
CN101530649A (en) Defibrillator and defibrillation electrode with unified electrode interfaces
CN201604665U (en) Communication interface equipment of train control center
CN105335311A (en) Portable electronic device and power management method
CN103098039B (en) High-speed peripheral device interconnection bus port collocation method and equipment
CN202872142U (en) Multifunctional USB (Universal Serial Bus) data line
CN216118766U (en) Protocol converter of USB bus and PC104 bus
US20120054392A1 (en) Data read and write device and method for usb ports of 1-wire devices
CN102693203A (en) Embedded USB (universal serial bus) host
CN205263790U (en) Display control board
CN102467212A (en) Power supply of computer
CN203658990U (en) Debugging device for central processing unit
CN214042097U (en) PLC serial port communication extension module capable of customizing protocol
CN113986807B (en) Protocol conversion method and protocol converter for USB bus and PC104 bus
CN204302969U (en) The USB/RS232-CAN translation debugging device of various configurations mode
CN107391405A (en) Usb circuit and USB device
CN216623005U (en) Embedded industrial controller based on GPIO
CN107565077B (en) Battery pack communication circuit
CN216622983U (en) Locomotive simulation device and locomotive simulation system
CN213094226U (en) CAN communication device based on CPCI bus
CN217767436U (en) Bus backboard for communication of medical instrument module
CN216622984U (en) Tamping car simulation system and network control equipment thereof
CN216016890U (en) Dual-core 4U data communication gateway
CN212256301U (en) Embedded mainboard based on intel Whiskey lake

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant