CN215991008U - Airborne confrontation training information acquisition and evaluation system - Google Patents
Airborne confrontation training information acquisition and evaluation system Download PDFInfo
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- CN215991008U CN215991008U CN202122524915.0U CN202122524915U CN215991008U CN 215991008 U CN215991008 U CN 215991008U CN 202122524915 U CN202122524915 U CN 202122524915U CN 215991008 U CN215991008 U CN 215991008U
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Abstract
The utility model relates to an airborne confrontation training information acquisition and evaluation system, which comprises a task recorder, wherein the task recorder is provided with a data recording memory; the camera component CTVS is used for video recording and is connected with the task recorder through a video recording line and an audio recording line; wherein, the video recording circuit includes camera video input circuit: the composite video circuit is provided with a mark on the audio and video and marks the video output circuit clearly; the input end of the camera component CTVS receives the voltage, the shutdown signal and the synchronous signal output by the task recorder; the output end of the task recorder inputs a camera video signal and a self-checking signal to the task recorder; the task recorder is provided with an electronic disk, and sends data to the training bullets according to needs, and the training bullets transmit the data to the real-time monitoring and evaluating system on the ground in real time. The utility model has reasonable design, compact structure and convenient use.
Description
Technical Field
The utility model relates to an airborne confrontation training information acquisition and evaluation system.
Background
The airborne confrontation training information acquisition and evaluation system is used on an airplane, is a matched device of an air force real soldier confrontation training digital evaluation system, and is mainly used for recording 5-path clear video, 1-path high-definition video, 1-path voice, 200-path various state semaphore and 2-path 1553B bus data on the airplane in real time for a long time for multiple times, realizing multi-source information time scale unification, data recording unification and audio-video and data correlated playback, and can meet the objective and accurate analysis and interpretation of a flight confrontation training effect.
The airborne electronic countermeasure equipment is the main equipment for ensuring the self safety of the airplane, and the flight safety rate of the airplane is greatly influenced by the correctness and proficiency of the pilot on the use of the airborne electronic countermeasure equipment under various complicated combat conditions. Pilots must train more often to ensure proper use in wartime. However, in the usual flight training, the electromagnetic environment is generally simpler, the real battlefield environment cannot be simulated, the electromagnetic environment similar to the battle condition is difficult to appear, and the pilot cannot carry out targeted training, so that the training effect is influenced. Therefore, it is necessary to supplement this training content with a ground simulation trainer to improve the pilot's ability to use the electronic countermeasure equipment in various electromagnetic environments.
The existing airborne electronic countermeasure visual simulation training system can not adjust according to the physical changes of the trainees, and how to calculate the performance of the trainees and select training items, so that the trainees can better adapt to the simulation training system, and the dizzy condition caused by using the simulation training system is avoided.
The prior art has high manufacturing cost, high failure rate, inconvenient use and inaccurate positioning.
SUMMERY OF THE UTILITY MODEL
The utility model aims to solve the technical problem of providing an airborne confrontation training information acquisition and evaluation system.
In order to solve the problems, the technical scheme adopted by the utility model is as follows:
an airborne confrontation training information acquisition and evaluation system comprises
A task recorder having a data recording memory;
the camera component CTVS is used for video recording and is connected with the task recorder through a video recording line and an audio recording line; wherein, the video recording circuit includes camera video input circuit: the composite video circuit is provided with a mark on the audio and video and marks the video output circuit clearly; the input end of the camera component CTVS receives the voltage, the shutdown signal and the synchronous signal output by the task recorder; the output end of the task recorder inputs a camera video signal and a self-checking signal to the task recorder;
the task recorder is provided with an electronic disk, and sends data to the training bullets according to the requirements, and the training bullets transmit the data to the real-time monitoring and evaluating system on the ground in real time;
the task recorder, its recording medium is the solid-state memory; tagging the video picture and audio and superimposing absolute time;
the discrete magnitude processor is matched with the airplane to carry out discrete magnitude acquisition; and the discrete quantity processor converts the discrete quantity into an HDLC interface and then is crosslinked with the task recorder.
As a further improvement of the above technical solution:
the aircraft interface comprises
The output end of the video control panel VCP is electrically connected with the input end of the task recorder so as to transmit the marking signal and the power supply control signal; the input end of the task recorder is electrically connected with the output end of the task recorder so as to transmit a self-checking indication signal;
the output end of the container network interface CNI is electrically connected with the input end of the task recorder so as to transmit CNI audio signals;
the output end of the data communication port DCMP is electrically connected with the input end of the task recorder so as to transmit the VRC virtual signal and the VRM voltage signal;
the output end of the voice port MC is electrically connected with the input end of the task recorder so as to transmit reset synchronization and rear cabin video; the input end of the task recorder is electrically connected with the output end of the task recorder so as to transmit the head-up display video signal;
the 1553B bus port is electrically connected with the task recorder to interactively transmit 1553B signals and has an MT working mode;
the input end of the training bomb is electrically connected with the output end of the task recorder so as to transmit RS422/RS485 signals; 4 paths of serial communication interfaces:
and the power supply module is used for providing power supply input to the task recorder through the power interface airplane.
The task recorder comprises a task recording device and a task recording device,
the electronic disk module HDM is responsible for storing all videos and data and providing a 3-channel USB2.0 interface;
the power supply module PSM is used for supplying electric energy;
the video compression recording module 1VRMSD-1 is provided with an input end connected with the output end of the camera assembly CTVS for receiving the assumed video SD data and is bidirectionally connected with a synchronous signal; the video compression recording module 1VRMSD-1, the output end is electrically connected with the head-up display video; the input end is electrically connected with a display video and a CNI audio in the rear cabin;
the video compression recording module 1VRMSD-1 records 1 path of camera video and 1 path of composite standard definition video, outputs 1 path of composite standard definition video, and stores the video on a USB electronic disk after the compression technology of H.265; VRMSD-1 mainly records, 1 path of camera input, 1 path of CVBS video signal, 1 path of telephone audio signal, and simultaneously outputs 1 path of CVBS video signal; adopting the latest H.265/H.264 compression algorithm; and storing the audio and video data in the electronic disk.
The input end is electrically connected with a CNI audio, a VRC signal and a composite synchronous signal, and the CNI audio, the VRC signal and the composite synchronous signal are stored on a USB electronic disk after the H.265/H.264 compression technology; the device is also provided with a video switching module;
the main control module CPU is electrically connected with the camera assembly CTVS and used for receiving a self-checking signal and sending a shutdown signal; the input end is contacted with a discrete signal HDLC, an RS422 signal, a shooting signal, a marking signal and a power supply control signal; the output end of the video control panel VCP sends a self-checking instruction to the video control panel VCP; exchanging task data with the HDM; the device is connected with a 1553B module MBI through a double-port bus to exchange data and store the data on an electronic disk of a USB; the main control module CPU records 200 paths of discrete magnitude data and serial communication data, analyzes 1553B data and stores the data on a USB electronic disk;
and the 1553B module MBI is responsible for monitoring four paths of 1553B bus data and writing the monitored data into the double-port memory for the CPU module to read.
Compared with the H.264 algorithm, the image recording is clearer, the code stream is smaller and the recording time is longer by adopting the latest H.265 compression algorithm;
the video compression recording module 1VRMSD-1 comprises a chip for an FPGA video processing and control device, a dual-core CORTEX-A9 inner core is contained, and the compression requirement of multi-path audio and video is met by matching with an H.265 logic algorithm;
the decoder is interacted with the composite video signal; the input end of the AUDIO/video signal processing circuit receives an AUDIO signal and a video signal; the output end of the chip is connected with the chip;
the chip is electrically connected with the synchronous signal and the discrete magnitude signal through the optical coupling isolator;
the chip is electrically connected with the USB signal, the UART signal, the power circuit, the DDR circuit, the reset watchdog circuit, the flash circuit and the encryption circuit.
The video compression recording module 2VRMSD-2 collects 8 paths of CVBS composite video and 1 path of audio, and simultaneously records 4 paths of CVBS video signals and 1 path of telephone audio signals in the 8 paths of video signals through video switching.
The 1553B module MBI comprises a JSM320F2812 circuit of a processor, a reset circuit, a 1553B interface circuit, a serial communication circuit, a clock circuit, a discrete magnitude processing circuit, a voltage conversion circuit and a watchdog circuit;
the electronic disk module HDM is provided with a memory of a SATA/USB interface and a real-time clock module, the electronic disk can be conveniently pulled out from the task recording component, the universal USB interface can be conveniently connected with ground equipment, and the data of the electronic disk can be read at high speed and reliably.
The utility model has the advantages of reasonable design, low cost, firmness, durability, safety, reliability, simple operation, time and labor saving, capital saving, compact structure and convenient use. The design of the assembly of the utility model will keep the 6-channel video recording and 1-channel audio recording functions of the original machine, and in addition, the data recording function is added. The video recording function is realized by adopting the most advanced h.265 compression technology and high-integration chip design and designing 2 standard definition video compression recording modules, and is divided into a standard definition video compression module 1 (recording 2-way standard definition and 1-way audio and providing 1-way standard definition output) and a standard definition compression recording module 2 (recording 4 groups of 2-selected 1 standard definition video and 1-way audio); the added data recording function is realized by adopting a PowerPC (personal computer) architecture module based on stability and high performance through a CPU (central processing unit) module (recording 200 paths of various semaphore states and sending data to training) and a 1553B module (recording 2 paths of 1553B bus data on an original machine).
Drawings
FIG. 1 is a diagram of a mission recorder and aircraft system cross-connect of the present invention.
FIG. 2 is a block diagram of a task recorder system of the present invention.
Fig. 3 is a schematic diagram of a front panel structure of a chassis according to the present invention.
Figure 4 is a block diagram of the video compression module VRMSD-1 module of the present invention.
Figure 5 is a software layer diagram of the VRMSD-1 module of the video compression module of the present invention.
Figure 6 is a schematic block diagram of the video compression module VRMSD-2 module of the present invention.
Figure 7 is a software layer diagram of the VRMSD-2 module of the video compression module of the present invention.
Fig. 8 is a functional block diagram of a master control module of the present invention.
FIG. 9 is a schematic block diagram of a 1553B module MBI of the present invention.
Fig. 10 is a functional block diagram of the electronic disk of the present invention.
Fig. 11 is a functional block diagram of a motherboard module of the present invention.
Detailed Description
As shown in FIGS. 1-11, the present invention includes
A task recorder; replacing a VSR recorder component of a VDRS video recording system of the original machine by the task recorder in situ; the task recorder is provided with a data recording memory;
the camera component CTVS is used for video recording and is connected with the task recorder through 6-channel video recording and 1-channel audio recording; wherein the content of the first and second substances,
composite video input 5 ways: wherein 4 paths are 4 groups of composite videos with 1 selected from 2, and the other 1 path is a real-time composite video; video resolution 720 × 576, CVBS signal, 25 frames per second;
outputting 1 path of standard definition video: resolution 720 x 576, CVBS signal, 25 frames per second;
the audio and video is provided with marks;
the audio and video recording module of the task recorder adopts H.265/H.264 compression technology, compared with the original function, the audio and video recording module greatly improves the video compression efficiency and the compression quality, and adopts a high-integration chip to improve the stability of a product;
the input end of the camera component CTVS receives the 28.5V and +/-12V voltage, the shutdown signal and the synchronous signal output by the task recorder; the output end of the task recorder inputs a camera video signal and a self-checking signal to the task recorder;
compared with the prior art, the task recorder is provided with an electronic disk, 200 paths of data in various types of semaphore states processed by a signal processor arranged on an original machine are recorded on the electronic disk, and 2 paths of 1553B bus data on the original machine are recorded on the electronic disk; the task recorder is used for sending data to the training bullets according to needs, and the training bullets transmit the data to the real-time monitoring and evaluating system on the ground in real time;
the task recorder is provided with a solid-state memory as a recording medium, 3 paths of independent tasks are independent, and the capacity of each task recorder is 16 GB; the interface for reading and storing is USB 2.0; adding a marking function to the video picture and the audio, and superposing absolute time; the compressed file adopts H.265/H.264 compression algorithm;
on the airplane, a discrete magnitude processor is matched with the airplane to carry out discrete magnitude acquisition; the discrete quantity processor converts the discrete quantity into an HDLC interface and then is crosslinked with the task recorder; discrete quantity channel with 4-path input and 2-path output
Because the discrete quantity that needs to gather is 200 ways, if the discrete quantity directly gives the task recorder, will consume a large amount of cables and connector, be difficult for installing and connecting on the aircraft. And (3) collecting 200 paths of discrete quantities by using a discrete quantity processor device, converting the discrete quantities into an HDLC interface, and then crosslinking the HDLC interface with a task recorder, thereby solving the problems of installation and connection. The number of the single machines is 1.
The aircraft interface comprises
The output end of the video control panel VCP is electrically connected with the input end of the task recorder so as to transmit the marking signal and the power supply control signal; the input end of the task recorder is electrically connected with the output end of the task recorder so as to transmit a self-checking indication signal;
the output end of the container network interface CNI is electrically connected with the input end of the task recorder so as to transmit CNI audio signals;
the output end of the data communication port DCMP is electrically connected with the input end of the task recorder so as to transmit the VRC virtual signal and the VRM voltage signal;
the output end of the voice port MC is electrically connected with the input end of the task recorder so as to transmit reset synchronization and rear cabin video; the input end of the task recorder is electrically connected with the output end of the task recorder so as to transmit the head-up display video signal; built-in voice; audio response range: 20Hz-20KHz, unbalanced input and impedance matching;
the 1553B bus port is electrically connected with the task recorder to interactively transmit 1553B signals, the route of the 1553B bus port is 4 paths, and the 1553B bus port has an MT working mode;
the input end of the training bomb is electrically connected with the output end of the task recorder so as to transmit RS422/RS485 signals; 4 paths of serial communication interfaces: RS422 signal, the baud rate is adjustable, can reach 460.8 kbps; 2 paths of RS485 interfaces, 4 lines of system (compatible with 2 lines of system), adjustable baud rate which can be up to 460.8 kbps;
the power supply module provides +28.5V power supply input to the task recorder through the power supply 28.5V interface airplane, and meets GJB181A-2003 requirements on airplane power supply characteristics and electric equipment; the power consumption of the power supply is not more than 28.5V/5A, and the power consumption is not more than 8A during heating; the power supply has a power-off delay function: the output of +/-12V is delayed for 10 seconds when the machine is shut down;
the task recorder comprises a task recording device and a task recording device,
the electronic disk module HDM is responsible for storing all videos and data and providing a 3-channel USB2.0 interface;
the power supply module PSM is used for supplying electric energy;
the video compression recording module 1VRMSD-1 is provided with an input end connected with the output end of the camera assembly CTVS for receiving the assumed video SD data and is bidirectionally connected with a synchronous signal; the video compression recording module 1VRMSD-1, the output end is electrically connected with the head-up display video; the input end is electrically connected with a display video and a CNI audio in the rear cabin;
the video compression recording module 1VRMSD-1 records 1 path of camera video and 1 path of composite standard definition video, outputs 1 path of composite standard definition video, and stores the video on a USB electronic disk after the compression technology of H.265; VRMSD-1 mainly records, 1 path of camera input, 1 path of CVBS video signal, 1 path of telephone audio signal, and simultaneously outputs 1 path of CVBS video signal; adopting the latest H.265/H.264 compression algorithm; and storing the audio and video data in the electronic disk. The module reserves 1-path 1080P high-definition recording interface and 4-path RS422 interface.
The input end of the video compression recording module 2VRMSD-2 is electrically connected with CNI audio, VRC signals and composite synchronous signals, and the CNI audio, the VRC signals and the composite synchronous signals are stored on a USB electronic disk after the H.265/H.264 compression technology; the device is also provided with a video switching module;
the main control module CPU is electrically connected with the camera assembly CTVS and used for receiving a self-checking signal and sending a shutdown signal; the input end is contacted with a discrete signal HDLC, an RS422 signal, a shooting signal, a marking signal and a power supply control signal; the output end of the video control panel VCP sends a self-checking instruction to the video control panel VCP; exchanging task data with the HDM; the device is connected with a 1553B module MBI through a double-port bus to exchange data and store the data on an electronic disk of a USB; the main control module CPU records 200 paths of discrete magnitude data and serial communication data, analyzes 1553B data and stores the data on a USB electronic disk;
and the 1553B module MBI is responsible for monitoring four paths of 1553B bus data and writing the monitored data into the double-port memory for the CPU module to read.
The video compression recording module 1VRMSD-1 adopts the latest H.265 compression algorithm, and compared with the H.264 algorithm, the video compression recording module has the advantages of clearer image recording, smaller code stream and longer recording time;
the video compression recording module 1VRMSD-1 comprises a chip for an FPGA video processing and control device, a dual-core CORTEX-A9 inner core is contained, and the compression requirement of multi-path audio and video is met by matching with an H.265 logic algorithm;
the decoder is interacted with the composite video signal; the input end of the AUDIO/video signal processing circuit receives an AUDIO signal and a video signal; the output end of the chip is connected with the chip;
the chip is electrically connected with the synchronous signal and the discrete magnitude signal through the optical coupling isolator;
the chip is electrically connected with the USB signal, the UART signal, the power circuit, the DDR circuit, the reset watchdog circuit, the flash circuit and the encryption circuit;
the basic working principle of the video compression recording module 1VRMSD-1 is as follows: the method comprises the steps of synchronously acquiring 1 path of camera video, 1 path of composite video and 1 path of audio, converting the camera video signal into BT.656 data for FPGA after TW2866 decoding, converting the composite video signal into BT.656 data for FPGA after TW2866 decoding, converting the audio signal into IIS data for FPGA after TW2866 decoding, compressing the audio and video data, timing, packaging and storing the data into an electronic disk according to a synchronous signal, a discrete quantity signal and UART data by an FPGA video processing and controlling device. Meanwhile, the FPGA video processing and controlling device can convert the video signal of the camera into a composite video and send the composite video to the monitor, thereby completing various functions.
The software part of the video compression recording module 1VRMSD-1, the first part is the realization of H.265 compression algorithm, the second part is the realization of audio and video control, including timing, discrete magnitude control box processing and hard disk control;
the video compression recording module 1VRMSD-1 is based on the linux operating system; the hardware comprises three layers of software, wherein a first layer of Linux kernel comprises an image acquisition driver, a USB driver, a network driver, a GPIO driver, an audio driver and a serial driver; the second layer is a program library, including H.265.code library, etc.; the third layer is an application program which comprises image acquisition, serial communication, audio acquisition, GPIO control, image compression, network communication and image audio storage;
the video compression recording module 2VRMSD-2 collects 8 paths of CVBS composite video and 1 path of audio, and simultaneously records 4 paths of CVBS video signals and 1 path of telephone audio signals in the 8 paths of video signals through video switching; the latest h.265 compression algorithm is adopted, the audio and video data are stored in the electronic disk, and 4 RS422 interfaces are reserved in the module;
the video compression recording module 2VRMSD-2 adopts the latest H.265 compression algorithm, and compared with the H.264 algorithm, the video compression recording module has the advantages of clearer image recording, smaller code stream and longer recording time. The latest FPGA chip is used in module design, a dual-core CORTEX-A9 inner core is contained in the chip, and the compression requirement of multi-path audio and video is met by matching with an advanced H.265 logic algorithm. The module also comprises a power supply circuit, a DDR circuit, a reset watchdog circuit, a flash circuit and an encryption circuit.
The module mainly works for synchronously acquiring 8 paths of composite videos, and is divided into 4 groups; the first group is VRC11 and VRC12 video signals, the FPGA detects whether video signals exist in VRC11 and VRC12 through 2 MAX7461, VRC11 and VRC12 are gated by controlling MAX4025, data which are gated to enter TW2866 and decoded into bt.656 enter the FPGA to be compressed and the like, and the FPGA compresses, time marks and packages compressed audio and video according to synchronous signals, discrete quantity and UART signals and stores the data in an electronic disk; TW2866 is a 4-channel video AD, with 1 channel audio AD, 1 channel audio DA, and 1 channel video DA.
The software of the video compression recording module 2VRMSD-2 mainly comprises 2 parts, wherein the first part is the realization of an H.265 compression algorithm, and the second part is the realization of audio and video control, including video switching, time correction, discrete quantity control box processing and hard disk control;
the video compression recording module 2VRMSD-2 is based on the linux operating system embedded; the hardware-based Linux system mainly comprises three layers of software, wherein a first layer of Linux kernel comprises an image acquisition driver, a USB driver, a network driver, a GPIO driver, an audio driver and a serial driver; the second layer is a library, containing the h.265.code library; the third layer is an application program which comprises image acquisition, serial communication, audio acquisition, GPIO control, image compression, network communication and image audio storage;
the main control module CPU is used for controlling the VRMSD-1 and VRMSD-2 modules to record, stop and play back audio and video; processing 1553B bus data acquired by the module; and processing 200 paths of discrete magnitude signals;
a main control module CPU, a Freescale-based PowerPC processor MPC 8377; the processor mainly comprises the following characteristics to completely meet the design requirement. The power PC e300 core in the MPC8377 is provided with a 32K byte instruction cache and a 32K byte data cache, realizes the instruction system structure of the power PC, and provides hardware and software debugging support, in addition, the MPC8377 provides 1 Ethernet controller of 100/1000Mbps, 1 DDR2 SDRAM memory controller, a local bus controller of LBC, two 32 bit/1 64 bit PCI controllers, a special safety engine, a programmable interrupt controller, two I2C controllers, 1 DMA controller of 4 channels, a GPIO port and 1 USB2.0 host and device controller. The high integration in MPC8377 simplifies and simplifies board design and provides very large bandwidth and excellent performance.
The main control module CPU is provided with a power supply circuit, a reset and watchdog circuit, a DDR circuit, a FLASH circuit and a serial port communication circuit; the DDR chip adopts MT47H64M16HR, the capacity is 1Gb (64M multiplied by 16), and 1.8V is used for power supply; the NOR Flash chip selects S29GL512N10TFI020 with capacity of 512Mb and power supply of 3.3V; the NAND Flash chip selects K9F5608U0D, has 32M capacity and supplies power at 3.3V.
The main control module CPU is based on the embedded VXWORKS operating system; the hardware comprises three layers of software, namely a first layer of Linux kernel, a USB driver, a network driver, a GPIO driver, an audio driver and a serial driver; the second layer is a program library which comprises a network library; the third layer is an application program comprising serial communication, GPIO control and network communication;
the 1553B module MBI is used for acquiring data of 4 paths of 1553B buses, the bus transmission rate is 1Mb/s, the error rate of bus transmission words is less than 10-7, and the data is processed by SMJ320F2812 and then is read by the main control module through the double-port memory;
the 1553B module MBI comprises a JSM320F2812 circuit of a processor, a reset circuit, a 1553B interface circuit, a serial communication circuit, a clock circuit, a discrete quantity processing circuit, a voltage conversion circuit and a watchdog circuit.
The 1553B bus signal is converted into a digital signal through a transformer and a protocol chip, the F2812 chip reads and writes the signal through an external bus, and data is put into a dual-port bus according to a 1553B protocol form for use by a cross-linking module. And adopting the embedded C language with high reliability.
The electronic disk module HDM is provided with a memory of a SATA/USB interface and a real-time clock module, the electronic disk can be conveniently pulled out from the task recording component, the universal USB interface can be conveniently connected with ground equipment, and the data of the electronic disk can be read at high speed and reliably.
The software design of the electronic disk is mainly divided into a storage part and a time correction part.
The storage part adopts embedded C language with high reliability. The software design with high reliability is matched with the memory controller, so that the data is completely and unmistakably stored in the FLASH chip, and the data in the electronic disk can be completely and unmistakably read through accurate software control.
The storage part also adopts embedded C language with high reliability. The high-reliability software structure, the accurate time sequence control time processing controller and the accurate acquisition of time data are used for accurately transmitting time to the timed module through the RS422 interface through the organization and the perfect protocol of the time data, and can receive an external time service instruction and provide time for the timed module.
The motherboard module MB employs a high-reliability connector, which ensures seamless transmission of data among the video compression module, the power module, and the electronic disk module. The motherboard module also completes reliable connection with the aviation connector.
The equipment power supply module is developed by adopting a universal DC/DC multi-path output power supply module.
System software design
The device software consists of three parts: application software, BIT software and development environment.
Software design
The application software comprises foreground and background routines, wherein the foreground software realizes the acquisition of VGA video data, and the background software realizes the analysis, compression, processing and storage of the acquired data in the electronic disk. The electronic disk software can also provide time service for the video compression module.
BIT software design
The equipment of the utility model provides perfect BIT test capability, and each module in the equipment is designed with a BIT circuit and BIT software so as to detect the working state of the equipment according to the requirement and display the detected fault through a display panel. The BIT functions are divided into power-up BIT, periodic BIT, Start BIT, and maintenance BIT:
powering on the BIT: the self-checking in the aircraft is automatically carried out during the power-on initialization of the equipment, and the failed equipment can be detected before the XX aircraft leaves the ground;
the period BIT: in the normal working process of the equipment, each module software utilizes the idle time period to carry out self-detection, and can find and report own fault conditions to the main module in time under the condition of not influencing the normal working of the equipment;
starting the BIT: the equipment starts self-checking according to a BIT command sent by an avionic system;
and maintaining BIT: and during ground maintenance, equipment self-test is started in a man-machine conversation mode, and the BIT result can be displayed on the two-wire detection equipment according to the ICD defined format.
The present invention has been described in sufficient detail for clarity of disclosure and is not exhaustive of the prior art.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; it is obvious as a person skilled in the art to combine several aspects of the utility model. And such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (5)
1. An airborne confrontation training information acquisition and evaluation system is characterized in that: comprises that
A task recorder having a data recording memory;
the camera component CTVS is used for video recording and is connected with the task recorder through a video recording line and an audio recording line; wherein, the video recording circuit includes camera video input circuit: the composite video circuit is provided with a mark on the audio and video and marks the video output circuit clearly; the input end of the camera component CTVS receives the voltage, the shutdown signal and the synchronous signal output by the task recorder; the output end of the task recorder inputs a camera video signal and a self-checking signal to the task recorder;
the task recorder is provided with an electronic disk, and sends data to the training bullets according to the requirements, and the training bullets transmit the data to the real-time monitoring and evaluating system on the ground in real time;
the task recorder, its recording medium is the solid-state memory; tagging the video picture and audio and superimposing absolute time;
the discrete magnitude processor is matched with the airplane to carry out discrete magnitude acquisition; and the discrete quantity processor converts the discrete quantity into an HDLC interface and then is crosslinked with the task recorder.
2. The on-board countermeasure training information collection and evaluation system of claim 1, wherein: the aircraft interface comprises
The output end of the video control panel VCP is electrically connected with the input end of the task recorder so as to transmit the marking signal and the power supply control signal; the input end of the task recorder is electrically connected with the output end of the task recorder so as to transmit a self-checking indication signal;
the output end of the container network interface CNI is electrically connected with the input end of the task recorder so as to transmit CNI audio signals;
the output end of the data communication port DCMP is electrically connected with the input end of the task recorder so as to transmit the VRC virtual signal and the VRM voltage signal;
the output end of the voice port MC is electrically connected with the input end of the task recorder so as to transmit reset synchronization and rear cabin video; the input end of the task recorder is electrically connected with the output end of the task recorder so as to transmit the head-up display video signal;
the 1553B bus port is electrically connected with the task recorder to interactively transmit 1553B signals and has an MT working mode;
the input end of the training bomb is electrically connected with the output end of the task recorder so as to transmit RS422/RS485 signals; 4 paths of serial communication interfaces:
and the power supply module is used for providing power supply input to the task recorder through the power interface airplane.
3. The on-board countermeasure training information collection and evaluation system of claim 2, wherein: the task recorder comprises a task recording device and a task recording device,
the electronic disk module HDM is responsible for storing all videos and data and providing a 3-channel USB2.0 interface;
the power supply module PSM is used for supplying electric energy;
the video compression recording module 1VRMSD-1 is provided with an input end connected with the output end of the camera assembly CTVS for receiving the assumed video SD data and is bidirectionally connected with a synchronous signal; the video compression recording module 1VRMSD-1, the output end is electrically connected with the head-up display video; the input end is electrically connected with a display video and a CNI audio in the rear cabin;
the video compression recording module 1VRMSD-1 records 1 path of camera video and 1 path of composite standard definition video, outputs 1 path of composite standard definition video, and stores the video on a USB electronic disk after the compression technology of H.265; VRMSD-1 mainly records, 1 path of camera input, 1 path of CVBS video signal, 1 path of telephone audio signal, and simultaneously outputs 1 path of CVBS video signal; adopting the latest H.265/H.264 compression algorithm; storing the audio and video data in the electronic disc; the module reserves 1 path of 1080P high-definition recording interface and 4 paths of RS422 interface;
the input end of the video compression recording module 2VRMSD-2 is electrically connected with CNI audio, VRC signals and composite synchronous signals, and the CNI audio, the VRC signals and the composite synchronous signals are stored on a USB electronic disk after the H.265/H.264 compression technology; the device is also provided with a video switching module;
the main control module CPU is electrically connected with the camera assembly CTVS and used for receiving a self-checking signal and sending a shutdown signal; the input end is contacted with a discrete signal HDLC, an RS422 signal, a shooting signal, a marking signal and a power supply control signal; the output end of the video control panel VCP sends a self-checking instruction to the video control panel VCP; exchanging task data with the HDM; the device is connected with a 1553B module MBI through a double-port bus to exchange data and store the data on an electronic disk of a USB; the main control module CPU records 200 paths of discrete magnitude data and serial communication data, analyzes 1553B data and stores the data on a USB electronic disk;
the 1553B module MBI is responsible for monitoring four paths of 1553B bus data and writing the monitored data into the double-port memory for the CPU module to read;
the video compression recording module 1VRMSD-1 adopts the latest H.265 compression algorithm, and compared with the H.264 algorithm, the video compression recording module has the advantages of clearer image recording, smaller code stream and longer recording time;
the video compression recording module 1VRMSD-1 comprises a chip for an FPGA video processing and control device, a dual-core CORTEX-A9 inner core is contained, and the compression requirement of multi-path audio and video is met by matching with an H.265 logic algorithm;
the decoder is interacted with the composite video signal; the input end of the AUDIO/video signal processing circuit receives an AUDIO signal and a video signal; the output end of the chip is connected with the chip;
the chip is electrically connected with the synchronous signal and the discrete magnitude signal through the optical coupling isolator;
the chip is electrically connected with the USB signal, the UART signal, the power circuit, the DDR circuit, the reset watchdog circuit, the flash circuit and the encryption circuit.
4. The on-board countermeasure training information collection and evaluation system of claim 3, wherein: the video compression recording module 2VRMSD-2 collects 8 paths of CVBS composite video and 1 path of audio, and simultaneously records 4 paths of CVBS video signals and 1 path of telephone audio signals in the 8 paths of video signals through video switching.
5. The on-board countermeasure training information collection and evaluation system of claim 4, wherein: the 1553B module MBI comprises a JSM320F2812 circuit of a processor, a reset circuit, a 1553B interface circuit, a serial communication circuit, a clock circuit, a discrete magnitude processing circuit, a voltage conversion circuit and a watchdog circuit;
the electronic disk module HDM is provided with a memory of a SATA/USB interface and a real-time clock module, the electronic disk can be conveniently pulled out from the task recording component, the universal USB interface can be conveniently connected with ground equipment, and the data of the electronic disk can be read at high speed and reliably.
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