CN215526028U - Chip detection interface circuit - Google Patents
Chip detection interface circuit Download PDFInfo
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- CN215526028U CN215526028U CN202121046505.3U CN202121046505U CN215526028U CN 215526028 U CN215526028 U CN 215526028U CN 202121046505 U CN202121046505 U CN 202121046505U CN 215526028 U CN215526028 U CN 215526028U
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Abstract
The utility model discloses a chip detection interface circuit, which comprises a power supply transformation circuit, a main control circuit and a chip detection circuit; the power supply transformation circuit is respectively electrically connected with the main control circuit and the chip detection circuit and is used for providing working voltage; the main control circuit is electrically connected with the chip detection circuit, is used for detecting and controlling the chip detection circuit and interacts detection signals with the chip detection host; the chip detection circuit comprises a pulse transformation circuit, a signal detection circuit and a data pin detection circuit, the pulse transformation circuit is electrically connected with the main control circuit, the signal detection circuit is electrically connected with the main control circuit, and the data pin detection circuit is used for electrically connecting the pulse transformation circuit, the signal detection circuit and the chip to be detected. The technical scheme of the utility model is used for improving the compatibility of chip fault detection and the chip detection efficiency.
Description
Technical Field
The utility model relates to the technical field of semiconductor chip detection, in particular to a chip detection interface circuit.
Background
The communication protocol of a series of chips is a non-standard protocol, namely a self-defined protocol, and a common singlechip cannot communicate with the series of chips. In order to detect the series of chips, the general-purpose singlechip can communicate with the chips through corresponding circuits.
The voltage range of the series of chips is between 0 and 5.2V, the voltage identification range of a common singlechip is between 0 and 3.3V, and the high and low voltage identification ranges from 0.7V to high level and from 0.7V to low level. The voltage difference of the series of chips is about 0.2V, so that the universal single chip microcomputer is difficult to communicate with the series of chips, and the chip detection efficiency is low.
SUMMERY OF THE UTILITY MODEL
The utility model mainly aims to provide a chip detection interface circuit, aiming at enabling a single chip microcomputer and a series of chips to communicate by adopting a non-standard communication protocol through a signal detection circuit, a pulse transformation circuit and a data pin detection circuit, and improving the compatibility of chip fault detection and the chip detection efficiency.
In order to achieve the above object, the chip detection interface circuit provided by the present invention comprises a power transformation circuit, a main control circuit and a chip detection circuit; the power supply transformation circuit is respectively electrically connected with the main control circuit and the chip detection circuit and is used for providing working voltage; the main control circuit is electrically connected with the chip detection circuit, is used for detecting and controlling the chip detection circuit, and interacts detection signals with the chip detection host; the chip detection circuit comprises a pulse transformation circuit, a signal detection circuit and a data pin detection circuit, wherein the pulse transformation circuit is electrically connected with the main control circuit, the signal detection circuit is electrically connected with the main control circuit, and the data pin detection circuit is used for electrically connecting the pulse transformation circuit, the signal detection circuit and a chip to be detected.
In an embodiment of the utility model, the data pin detection circuit includes an output signal connection terminal and an input signal connection terminal, the input signal connection terminal is connected in series with the first capacitor, the output signal connection terminal is connected in series with the second capacitor, and the other end of the first capacitor and the other end of the second capacitor are both connected to ground.
In an embodiment of the present invention, the pulse transforming circuit includes a voltage comparing circuit, a rectifying and voltage stabilizing circuit, and a pulse generating circuit; the voltage comparison circuit is respectively electrically connected with the power supply transformation circuit and the main control circuit and is used for outputting a voltage comparison result according to the working voltage; the rectification voltage stabilizing circuit is electrically connected with the voltage comparison circuit and is used for outputting a stable voltage according to the voltage comparison result; the pulse generating circuit is respectively electrically connected with the rectification voltage stabilizing circuit, the main control circuit and the output signal connecting end and is used for converting the stabilized voltage into a pulse signal.
In an embodiment of the present invention, the signal detection circuit includes a sampling voltage division circuit, a first voltage detection circuit, and a second voltage detection circuit; the sampling voltage division circuit is electrically connected with the input signal connecting end and used for receiving a waveform signal sent by a chip to be detected and converting the waveform signal into a voltage sampling signal; the first voltage detection circuit is respectively electrically connected with the sampling voltage division circuit and the main control circuit and is used for comparing the voltage sampling signal with a first reference voltage signal and outputting a first detection signal; and the second voltage detection circuit is respectively electrically connected with the sampling voltage division circuit and the main control circuit and is used for comparing the voltage sampling signal with a second reference voltage signal and outputting a second detection signal.
In an embodiment of the present invention, the power transforming circuit includes a power boosting circuit, a power dropping circuit and a power converting circuit; the input end of the power supply booster circuit is electrically connected with the power supply end of the power supply; and the output end of the power supply boosting circuit is electrically connected with the input end of the power supply voltage reducing circuit and the input end of the power supply conversion circuit respectively.
In an embodiment of the present invention, the power supply voltage boost circuit is configured to boost a voltage of a power supply terminal of a power supply to a 5.5V stable power supply, where the voltage of the power supply terminal of the power supply is 4.2V.
In an embodiment of the utility model, the power supply voltage reducing circuit is configured to reduce the voltage of the 5.5V stable power supply provided by the power supply voltage boosting circuit to obtain a first direct current power supply signal, where the first direct current power supply signal is used to indicate that the main control circuit is provided with the operating voltage.
In an embodiment of the utility model, the power conversion circuit is configured to convert the 5.5V power provided by the power boost circuit into a second dc power signal, where the second dc power signal is used to instruct to provide the operating voltage to the chip detection circuit.
In an embodiment of the present invention, the chip detection interface circuit further includes a data communication interface circuit, which is electrically connected to the main control circuit and the chip detection host, respectively, and is configured to interact with the chip detection host through an RS485 communication manner.
In an embodiment of the present invention, the main control circuit further includes a main control chip, a reset circuit, a debug circuit, a display circuit, a key circuit, a crystal oscillation circuit, and a buffer output circuit; the main control chip is electrically connected with the reset circuit, the debugging circuit, the display circuit, the key circuit, the crystal oscillation circuit and the buffer output circuit respectively.
The chip detection interface circuit provided by the utility model comprises a power supply transformation circuit, a main control circuit and a chip detection circuit; the power supply transformation circuit is respectively electrically connected with the main control circuit and the chip detection circuit and is used for providing working voltage; the main control circuit is electrically connected with the chip detection circuit, is used for detecting and controlling the chip detection circuit, and interacts detection signals with the chip detection host; the chip detection circuit comprises a pulse transformation circuit, a signal detection circuit and a data pin detection circuit, wherein the pulse transformation circuit is electrically connected with the main control circuit, the signal detection circuit is electrically connected with the main control circuit, and the data pin detection circuit is used for electrically connecting the pulse transformation circuit, the signal detection circuit and a chip to be detected. According to the scheme, the single chip microcomputer and the series of chips can be communicated by adopting a non-standard communication protocol through the signal detection circuit, the pulse transformation circuit and the data pin detection circuit, and the compatibility of chip fault detection and the chip detection efficiency are improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a schematic structural diagram of an embodiment of a chip detection interface circuit according to the present invention;
FIG. 2 is a schematic structural diagram of another embodiment of a chip detection interface circuit according to the present invention;
FIG. 3 is a schematic diagram of a voltage comparison circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an embodiment of a rectifying voltage regulator circuit according to the present invention;
FIG. 5 is a schematic diagram of an embodiment of a pulse generating circuit according to the present invention;
FIG. 6 is a schematic diagram of an embodiment of a sampling voltage divider circuit according to the present invention;
FIG. 7 is a schematic diagram of a first voltage detection circuit according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a second voltage detection circuit according to an embodiment of the utility model.
The reference numbers illustrate:
| reference numerals | Name (R) | Reference numerals | Name (R) |
| 1000 | Chip |
250 | |
| 100 | Power supply |
260 | |
| 200 | |
270 | |
| 300 | |
310 | Pulse |
| 400 | |
320 | |
| 500 | Chip to be detected | 330 | Data |
| 600 | Data |
311 | |
| 110 | Power |
312 | Rectification |
| 120 | Power supply |
313 | |
| 130 | Power |
321 | Sampling |
| 210 | |
322 | First |
| 220 | |
323 | Second |
| 230 | |
331 | Output |
| 240 | |
332 | Input signal connecting terminal |
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that all the directional indicators (such as up, down, left, right, front, and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.
In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
Referring to fig. 1, a chip detection interface circuit 1000 according to the present invention includes a power transformer circuit 100, a main control circuit 200, and a chip detection circuit 300; the power transformer circuit 100 is electrically connected to the main control circuit 200 and the chip detection circuit 300, respectively, and is configured to provide a working voltage; the main control circuit 200 is electrically connected to the chip detection circuit 300, and is configured to perform detection control on the chip detection circuit 300 and interact with the chip detection host 400 to generate detection signals; the chip detection circuit 300 includes a pulse transformation circuit 310, a signal detection circuit 320 and a data pin detection circuit 330, wherein the pulse transformation circuit 310 is electrically connected to the main control circuit 200, the signal detection circuit 320 is electrically connected to the main control circuit 200, and the data pin detection circuit 330 is used for electrically connecting the pulse transformation circuit 310, the signal detection circuit 320 and the chip 500 to be detected.
The power transforming circuit 100 is used to indicate a voltage stabilizing circuit that is transformed, rectified and filtered. Further, the power transforming circuit 100 includes an input terminal and an output terminal (not shown), the input terminal of the power transforming circuit 100 is electrically connected to a power supply terminal (not shown), and the output terminal of the power transforming circuit 100 is electrically connected to a power supply pin (not shown) of the main control circuit 200, for converting an input ac voltage or a dc voltage into a dc voltage. The power transformer circuit 100 may boost or buck, and is not limited herein. For example, the power transformer circuit 100 may convert a dc voltage of 4.2V input from the power supply terminal into a dc voltage of 5.5V, or convert a dc voltage of 12V or an ac voltage of 220V input from the power supply terminal into a dc voltage of 5.5V, which is not limited herein.
The main control circuit 200 is electrically connected to the chip detection circuit 300 through a data pin, receives the power supply voltage of the power transformer circuit 100, and is configured to perform detection control on the chip detection circuit 300, that is, the main control circuit 200 may control signal input of the chip detection circuit 300, and may also receive and process signal output of the chip detection circuit 300 to obtain detection signals, where each detection signal is used to indicate working parameter data of the chip 500 to be detected. The main control circuit 200 is wirelessly connected to the chip detection host 400, and transmits each detection signal to the chip detection host 400 in real time. The chip detection host 400 is configured to perform data analysis processing on each detection signal reported by the main control circuit 200 in real time, so as to detect whether the chip 500 to be detected is a normal chip or an abnormal chip.
The chip detection circuit 300 includes a pulse transformation circuit 310, a signal detection circuit 320, and a data pin detection circuit 330. Further, the pulse transforming circuit 310 is electrically connected to the main control circuit 200 through two data pins, the pulse transforming circuit 310 is configured to generate a clock pulse signal, and set the clock pulse signal as an input signal of the chip 500 to be detected, and both the frequency of the clock pulse signal and the voltage range of the clock pulse signal are controlled by the main control circuit 200.
The input end of the signal detection circuit 320 is electrically connected to the data pin detection circuit 330, the output end of the signal detection circuit 320 is electrically connected to the main control circuit 200, the signal detection circuit 320 is configured to collect an output signal of the chip 500 to be detected and convert the output signal of the chip 500 to be detected into each detection signal, and further, the signal detection circuit 320 transmits each detection signal to the main control circuit 200.
The data pin detection circuit 330 is electrically connected to the chip 500 to be detected. Further, the chip 500 to be detected is connected to the output terminal of the pulse transformer circuit 310 and the input terminal of the signal detection circuit 320, respectively, so as to realize chip detection under the non-standard communication protocol. The type and the number of pins of the chip 500 to be detected are not limited. The number of the data pin detection circuit 330 may be 1 or more, and is not limited herein. Preferably, the number of the data pin detection circuit 330 is 2, and includes an output terminal of the pulse transformer circuit 310 and an input terminal of the signal detection circuit 320.
According to the technical scheme, the chip detection interface circuit comprises a power supply transformation circuit, a main control circuit and a chip detection circuit; the power supply transformation circuit is respectively electrically connected with the main control circuit and the chip detection circuit and is used for providing working voltage; the main control circuit is electrically connected with the chip detection circuit, is used for detecting and controlling the chip detection circuit and interacts detection signals with the chip detection host; the chip detection circuit comprises a pulse transformation circuit, a signal detection circuit and a data pin detection circuit, the pulse transformation circuit is electrically connected with the main control circuit, the signal detection circuit is electrically connected with the main control circuit, and the data pin detection circuit is used for electrically connecting the pulse transformation circuit, the signal detection circuit and the chip to be detected. The single chip microcomputer and the series of chips can communicate by adopting a non-standard communication protocol through the signal detection circuit, the pulse transformation circuit and the data pin detection circuit, and the compatibility of chip fault detection and the chip detection efficiency are improved.
In an embodiment of the present invention, referring to fig. 1 to 2, the data pin detection circuit 330 includes an output signal connection terminal 331 and an input signal connection terminal 332, the input signal connection terminal 332 is connected in series with one end (not shown) of a first capacitor, the output signal connection terminal 331 is connected in series with one end (not shown) of a second capacitor, and the other end of the first capacitor and the other end of the second capacitor are both connected to ground. Further, the output signal connection terminal 331 and the input signal connection terminal 332 are electrically connected to corresponding pins of the chip 500 to be tested through connection ports.
In an embodiment of the present invention, in order to implement communication with the chip 500 to be tested, please refer to fig. 2, the pulse transforming circuit 310 includes a voltage comparing circuit 311, a rectifying and voltage stabilizing circuit 312, and a pulse generating circuit 313; the voltage comparison circuit 311 is electrically connected to the power transformation circuit 100 and the main control circuit 200, and is configured to output a voltage comparison result according to the working voltage; the rectifying and voltage stabilizing circuit 312 is electrically connected to the voltage comparing circuit 311, and is configured to output a stable voltage according to the voltage comparison result; the pulse generating circuit 313 is electrically connected to the rectifying and voltage stabilizing circuit 312, the main control circuit 200 and the output signal connection end 331, respectively, and is configured to convert the stabilized voltage into a pulse signal.
Referring to fig. 3, the voltage comparison circuit 311 includes a voltage amplifier and a plurality of voltage dividing resistors, one end of the voltage dividing resistor R1 is electrically connected to the output terminal Vcc of the power transformer circuit 100 (e.g., 3.3V voltage), the other end of the voltage dividing resistor R1 is connected in series to the voltage dividing resistor R2, the voltage dividing resistor R2 is electrically connected to the low level enable pin CLK _ EN of the main control circuit 200, and the connection point between the voltage dividing resistor R1 and the voltage dividing resistor R2 is electrically connected to the positive electrode (i.e., pin 3) of the voltage comparator U1 (e.g., LM 358M); the voltage dividing resistor R3 is connected in series with the voltage dividing resistor R4, one end of the voltage dividing resistor R3 is connected with a power supply V1 (which may be 1.6V), the other end of the voltage dividing resistor R4 is electrically connected with a ground GND, a connection point between the voltage dividing resistor R3 and the voltage dividing resistor R4 is electrically connected with a negative electrode (namely a pin 2) of the voltage amplifier U1, a pin 8 of the voltage amplifier U1 is electrically connected with a power supply V2, a capacitor C1 is connected in series between the pin 8 of the power amplifier U1 and the ground GND, and the output end of the voltage amplifier U1 is connected with a resistor R5. The voltage comparison circuit 311 has high circuit signal processing precision, accurate output threshold value and small error. The voltage amplifier U1 may be of a model LM358, an LM393, or another model, and is not limited herein. Taking LM358 as an example, when the voltage at the positive electrode (i.e. pin 3) of the voltage amplifier LM358 is 0.8V to 0.85V, the voltage of 0.8V to 0.85V is obtained by dividing the voltage by R1 and R2, the voltage difference at the input end of the negative feedback linear amplifier is applied to be 0 (virtual short), and accordingly, the output signal Vout1 at the output end of the voltage comparing circuit 311 is at low level of 0V.
Referring to fig. 4, the rectifying and voltage-stabilizing circuit 312 includes a transistor Q1 (e.g., 2N3904), a base of a transistor Q1 is connected in series with a resistor R5, that is, the base of the transistor Q1 receives an output signal Vout1 from the output terminal of the voltage comparing circuit 311, an emitter of the transistor Q1 is grounded, a collector of the transistor Q1 is connected in series with a resistor R6 and a cathode of a schottky diode D1, the other end of the resistor R6 is connected to a power source V2, an anode of the schottky diode is connected in series with one end of the resistor R7, the other end of the resistor R7 is electrically connected to the power source V2, a capacitor C2 is connected in series between the cathode of the schottky diode D1 and the low GND, and a connection point between the anode of the schottky diode D1 and the resistor R7 is led out of the output signal connection terminal 331, and outputs a voltage signal Vout 2. For example, the voltage between R1 and D1 is about 1.6V, the forward voltage drop of D1 is about 0.3V, and the output voltage signal Vout2 is 1.9V.
Referring to fig. 5, the pulse generating circuit 313 includes a transistor Q2 (e.g., 2N3904), a collector of the transistor Q2 is electrically connected to the output signal connection terminal 331, an emitter of the transistor Q2 is electrically connected to ground GND, a base of the transistor Q2 is connected in series to a resistor R8, and another end of the resistor R8 is electrically connected to a signal output pin (PWM _ OUT) of the main control circuit 200. A capacitor C4 and a resistor R9 are respectively connected between the base electrode of the triode Q2 and the ground in series, and a capacitor C3 is connected between the collector electrode of the triode Q2 and the ground in series.
It can be understood that the pulse transformer circuit 310 controls the positive voltage signal of the voltage amplifier U1 to approximate the negative voltage signal of the voltage amplifier U1, so that the voltage amplifier U1 outputs a low level, the transistor Q1 in the rectifying and voltage stabilizing circuit 312 is in a cut-off state (if the transistor Q1 is turned on, the resistor R6 is directly grounded, the output voltage is 0V, the output signal Vout2 between the positive electrode of the schottky diode D1 and the connection point between the resistor R7 is not 1.6V), the voltage between the resistor R6 and the collector of the transistor Q1 is about 1.6V, the schottky diode D1 is in a conducting state, the voltage of the schottky diode D1 is about 0.2V-0.4V, and the output voltage signal connection point Vout 331 (i.e., the connection point Vout2 between the positive electrode of the schottky diode D1 and the resistor R7) is about 2V. When the signal output pin of the main control circuit 200 outputs a PWM pulse signal (i.e., PWM _ OUT), the transistor Q2 is periodically in an off or on state, and further controls the output signal connection terminal 331 to output a pulse signal V-, which may include 2V and 0V. Further, the output pulse signal V-from the output signal connection terminal 331 can be adjusted according to the output signal Vout2 and the output pulse signal PWM _ OUT from the signal output pin of the main control circuit 200.
In an embodiment of the present invention, referring to fig. 2, the signal detecting circuit 320 includes a sampling voltage dividing circuit 321, a first voltage detecting circuit 322 and a second voltage detecting circuit 323; the sampling voltage-dividing circuit 321 is electrically connected to the input signal connection terminal 332, and is configured to receive a waveform signal sent by the chip 500 to be detected and convert the waveform signal into a voltage sampling signal; the first voltage detection circuit 322 is electrically connected to the sampling voltage dividing circuit 321 and the main control circuit 200, respectively, and configured to compare the voltage sampling signal with a first reference voltage signal and output a first detection signal; the second voltage detection circuit 323 is electrically connected to the sampling voltage division circuit 321 and the main control circuit 200, respectively, and configured to compare the voltage sampling signal with a second reference voltage signal and output a second detection signal.
Referring to fig. 6, the sampling voltage divider 321 is electrically connected to the input signal connection terminal 332, the input signal connection terminal 332 is connected in series to the capacitor C5, the capacitor C5 is electrically connected to ground GND, and the capacitor C5 is used for performing filtering on the input signal connection terminal 332. After each detection signal V + input by the input signal connecting terminal 332 is subjected to voltage division processing by the resistor R10 and the resistor R11, a first voltage signal connecting terminal Vdd1 is led out from a connecting point between the resistor R10 and the resistor R11 and is used for outputting a voltage sampling signal; the other end of the resistor R10 is connected in series with one end of the resistor R12, the other end of the resistor R12 is connected with the power supply V2, and the resistance value of the resistor R12 can be 0 ohm.
Referring to fig. 7, the first voltage detection circuit 322 includes a voltage comparator U2, a plurality of voltage dividing resistors and a plurality of capacitors, and the positive electrode (pin 3) of the voltage comparator U2 is electrically connected to the first voltage signal connection terminal Vdd 1. Specifically, a voltage dividing resistor R13, a voltage dividing resistor R14 and a voltage dividing resistor R15 are sequentially connected in series, the other end of the voltage dividing resistor R13 is electrically connected with a power supply V2, the other end of the voltage dividing resistor R12 is electrically connected with ground GND, a voltage dividing resistor R15 and a capacitor C6 are connected in parallel, a second voltage signal connection terminal Vdd2 is led out from a connection point between the voltage dividing resistor R14 and the voltage dividing resistor R15 and used for outputting a first reference voltage signal, a second voltage signal connection terminal Vdd2 is electrically connected with a negative electrode (pin 2) of a voltage comparator U2, and a capacitor C6 is connected in series between a pin 8 of the voltage comparator U2 and the ground GND. A pull-up resistor R16 is connected between the output terminal (pin 1) of the voltage comparator U2 and the power supply Vcc, and the output terminal of the voltage comparator U2 is electrically connected to the DATA pin DATA1 of the main control circuit 200.
Referring to fig. 8, the second voltage detection circuit 323 includes a voltage comparator U3, a plurality of voltage dividing resistors and a plurality of capacitors, and the positive electrode (pin 3) of the voltage comparator U3 is electrically connected to the first voltage signal connection terminal Vdd 1. Specifically, a voltage dividing resistor R17, a voltage dividing resistor R18 and a voltage dividing resistor R19 are sequentially connected in series, the other end of the voltage dividing resistor R17 is electrically connected with a power supply V2, the other end of the voltage dividing resistor R19 is electrically connected with ground GND, a voltage dividing resistor R19 and a capacitor C8 are connected in parallel, a third voltage signal connection terminal Vdd3 is led out from a connection point between the voltage dividing resistor R17 and the voltage dividing resistor R18 and used for outputting a second reference voltage signal, the third voltage signal connection terminal Vdd3 is electrically connected with a negative electrode (pin 2) of a voltage comparator U3, and a capacitor C9 is connected in series between a pin 8 of the voltage comparator U3 and the ground GND. A pull-up resistor R20 is connected between the output terminal (pin 1) of the voltage comparator U3 and the power supply Vcc, and the output terminal of the voltage comparator U3 is electrically connected to the DATA pin DATA2 of the main control circuit 200.
It can be understood that the sampling voltage circuit mainly performs data interception with the first voltage detection circuit 322 and the second voltage detection circuit 323 by collecting the waveform signals returned by the detection chip. The main control circuit 200 controls the positive electrode voltage signal (i.e., the voltage sampling signal) of the voltage comparator U2 in the first voltage detection circuit 322 to be higher than the negative electrode voltage signal (i.e., the first reference voltage signal) of the voltage comparator U2, so that the voltage comparator U2 outputs a high level (e.g., 5.20V); the main control circuit 200 controls the positive electrode voltage signal (i.e., the voltage sampling signal) of the voltage comparator U3 in the second voltage detection circuit 323 to be lower than the negative electrode voltage signal (i.e., the second reference voltage signal) of the voltage comparator U3, so that the voltage comparator U3 outputs a low level (e.g., 5.05V).
In an embodiment of the present invention, referring to fig. 2, the power transforming circuit 100 includes a power boosting circuit 110, a power dropping circuit 120 and a power converting circuit 130; wherein, the input terminal of the power supply boost circuit 110 is electrically connected to the power supply terminal (not shown); the output terminal of the power boost circuit 110 is electrically connected to the input terminal of the power buck circuit 120 and the input terminal of the power conversion circuit 130, respectively.
And the power supply boosting circuit 110 is used for boosting the voltage of the power supply end of the power supply to a 5.5V stabilized power supply, and the voltage of the power supply end of the power supply is 4.2V. The power boost circuit 110 includes a voltage conversion chip (e.g., TPS61022RWUR), an inductor, a plurality of capacitors, and a plurality of resistors, wherein the voltage conversion chip, the inductor, the capacitors, and the resistors are connected in series or in parallel (not shown). The power boost circuit 110 boosts the 4.2V power provided by the chip detection host 400 to a 5.5V regulated power.
The power supply voltage reducing circuit 120 is configured to reduce the voltage of the 5.5V stable power supply provided by the power supply voltage boosting circuit 110 to obtain a first dc power supply signal, where the first dc power supply signal is used to indicate that the working voltage is provided to the main control circuit 200. The power supply voltage dropping circuit 120 includes a voltage conversion chip (e.g., ASM117), a plurality of capacitors, light emitting diodes, and resistors, which are connected in series or in parallel (not shown). The power step-down circuit 120 steps down the 5.5V power provided by the power boost circuit 110 to obtain a plurality of 3.3V stable power supply terminals (including Vcc) for supplying power to the main control circuit 200.
The power conversion circuit 130 is configured to convert the 5.5V power provided by the power boost circuit 110 into a second dc power signal, where the second dc power signal is used to instruct to provide the working voltage to the chip detection circuit 300. The power supply voltage reducing circuit 120 includes a PMOS transistor (e.g., AO3415), a plurality of capacitors, and a plurality of resistors, which are connected in series (not shown). The power conversion circuit 130 converts the 5.5V power provided by the power boost circuit 110 into a plurality of stable power supply terminals, so as to supply power to the chip detection circuit 300. The input voltage of the PMOS transistor may be 5.5V, the output voltage may be 5.2V (i.e., V2), or may be 3.3V, which is not limited herein.
In an embodiment of the present invention, referring to fig. 2, the chip detection interface circuit 1000 further includes a data communication interface circuit 600 electrically connected to the main control circuit 200 and the chip detection host 400, respectively, for interacting with the detection signals of the chip detection host 400 in an RS485 communication manner. The chip detection interface circuit 1000 is connected to the chip detection host 400 through a charging interface (e.g., a micro universal serial bus (microsub) interface) for supplying power (e.g., a supply voltage of 3.7V to 4.2V) to the chip detection interface circuit 1000. And the chip detection interface circuit 1000 performs data interaction with the chip detection host 400 in an RS485 communication manner.
Further, referring to fig. 2, optionally, the main control circuit 200 further includes a main control chip 210, a reset circuit 220, a debug circuit 230, a display circuit 240, a key circuit 250, a crystal oscillation circuit 260, and a buffer output circuit 270; the main control chip 210 is electrically connected to the reset circuit 220, the debug circuit 230, the display circuit 240, the key circuit 250, the crystal oscillation circuit 260, and the buffer output circuit 270, respectively. The main control chip 210 may be a single chip or an ARM processor, and is not limited herein.
The reset circuit 220 is electrically connected to a reset pin of the main control chip 210. The reset circuit 220 may include a pull-up resistor, a charge-discharge capacitor, and a reset switch, one end of the pull-up resistor is connected to the 3.3V power supply, one end of the reset switch is electrically connected to the other end of the pull-up resistor, the charge-discharge capacitor and the reset switch are connected in parallel, and the other end of the charge-discharge capacitor and the other end of the reset switch are both electrically connected to ground. The reset circuit 220 is used for monitoring the working voltage of the main control chip 210 in real time, and when the working voltage is unstable or has an instantaneous power failure condition, the reset circuit can perform reset operation on the main control chip 210, and can also perform reset operation on the main control chip 210 through a reset switch.
And the debugging circuit 230 is configured to burn the application program into the main control chip 210 through the JTAG interface, receive a debugging signal, and perform breakpoint debugging on the main control chip 210 according to the debugging signal.
The display circuit 240 comprises a light emitting diode and a resistor, wherein one end of the light emitting diode is connected with 3.3V, the other end of the light emitting diode is connected with one end of the resistor in series, and the other end of the resistor is connected with a data pin of the main control chip 210 and is used for visually displaying the working state of the main control chip 210 through the light emitting state of the light emitting diode.
The key circuit 250 includes a key switch and a resistor, one end of the key switch is connected to the control pin of the main control chip 210, the other end of the key switch is electrically connected to one end of the resistor, the other end of the resistor is connected to ground, and the key circuit 250 is used for controlling the operating state of the main control chip 210.
The crystal oscillation circuit 260 includes a crystal and a plurality of capacitors, and is used for providing a timing clock required by the main control chip 210.
And a buffer output circuit 270 for asynchronous communication with the chip detection host 400 based on a universal serial data bus protocol. The universal serial data bus protocol may enable full duplex transmission and reception.
According to the technical scheme, the chip detection interface circuit comprises a power supply transformation circuit, a main control circuit and a chip detection circuit; the output end of the power supply transformation circuit is electrically connected with a power supply pin of the main control circuit and is used for converting input alternating current or direct current voltage into direct current voltage; the power supply voltage transformation circuit is electrically connected with the chip detection circuit, is used for detecting and controlling the chip detection circuit and interacts detection signals with the chip detection host; the chip detection circuit comprises a pulse voltage transformation circuit, a signal detection circuit and a data pin detection circuit, wherein the pulse voltage transformation circuit is electrically connected with a main control circuit through an enabling pin, the signal detection circuit is electrically connected with the main control circuit through two data pins, the pulse voltage transformation circuit is used for generating clock pulse, the clock pulse is set to be an input signal of the chip to be detected, the signal detection circuit is used for collecting an output signal of the chip to be detected, the output signal of the chip to be detected is converted into each detection signal, and the data pin detection circuit is used for electrically connecting the pulse voltage transformation circuit, the signal detection circuit and the chip to be detected. The single chip microcomputer and the series of chips can communicate by adopting a non-standard communication protocol through the signal detection circuit, the pulse transformation circuit and the data pin detection circuit, and the compatibility of chip fault detection and the chip detection efficiency are improved.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications and equivalents of the technical solutions of the present invention, which are made by using the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A chip detection interface circuit is characterized by comprising a power supply transformation circuit, a main control circuit and a chip detection circuit; wherein the content of the first and second substances,
the power supply transformation circuit is respectively and electrically connected with the main control circuit and the chip detection circuit and is used for providing working voltage;
the main control circuit is electrically connected with the chip detection circuit, is used for detecting and controlling the chip detection circuit, and interacts detection signals with the chip detection host;
the chip detection circuit comprises a pulse transformation circuit, a signal detection circuit and a data pin detection circuit, wherein the pulse transformation circuit is electrically connected with the main control circuit, the signal detection circuit is electrically connected with the main control circuit, and the data pin detection circuit is used for electrically connecting the pulse transformation circuit, the signal detection circuit and a chip to be detected.
2. The chip detection interface circuit according to claim 1, wherein the data pin detection circuit comprises an output signal connection terminal and an input signal connection terminal, the input signal connection terminal is connected in series with the first capacitor, the output signal connection terminal is connected in series with the second capacitor, and the other end of the first capacitor and the other end of the second capacitor are both connected to ground.
3. The chip detection interface circuit according to claim 2, wherein the pulse transforming circuit comprises a voltage comparing circuit, a rectifying and voltage stabilizing circuit and a pulse generating circuit; wherein the content of the first and second substances,
the voltage comparison circuit is respectively electrically connected with the power supply transformation circuit and the main control circuit and is used for outputting a voltage comparison result according to the working voltage;
the rectification voltage stabilizing circuit is electrically connected with the voltage comparison circuit and is used for outputting a stable voltage according to the voltage comparison result;
the pulse generating circuit is respectively electrically connected with the rectification voltage stabilizing circuit, the main control circuit and the output signal connecting end and is used for converting the stabilized voltage into a pulse signal.
4. The chip detection interface circuit according to claim 2, wherein the signal detection circuit comprises a sampling voltage division circuit, a first voltage detection circuit and a second voltage detection circuit; wherein the content of the first and second substances,
the sampling voltage division circuit is electrically connected with the input signal connecting end and is used for receiving a waveform signal sent by a chip to be detected and converting the waveform signal into a voltage sampling signal;
the first voltage detection circuit is respectively electrically connected with the sampling voltage division circuit and the main control circuit and is used for comparing the voltage sampling signal with a first reference voltage signal and outputting a first detection signal;
and the second voltage detection circuit is respectively electrically connected with the sampling voltage division circuit and the main control circuit and is used for comparing the voltage sampling signal with a second reference voltage signal and outputting a second detection signal.
5. The chip detection interface circuit according to claim 1, wherein the power transforming circuit comprises a power boosting circuit, a power dropping circuit and a power converting circuit; wherein the content of the first and second substances,
the input end of the power supply booster circuit is electrically connected with the power supply end of the power supply;
and the output end of the power supply boosting circuit is electrically connected with the input end of the power supply voltage reducing circuit and the input end of the power supply conversion circuit respectively.
6. The chip detection interface circuit according to claim 5, wherein the power supply voltage boost circuit is configured to boost a voltage of a power supply terminal of the power supply to a 5.5V regulated power supply, and the voltage of the power supply terminal of the power supply is 4.2V.
7. The chip detection interface circuit of claim 6, wherein the power supply voltage reduction circuit is configured to reduce a voltage of a 5.5V stable power supply provided by the power supply voltage boost circuit to obtain a first DC power supply signal, and the first DC power supply signal is used to instruct the main control circuit to provide the operating voltage.
8. The chip detection interface circuit according to claim 6, wherein the power conversion circuit is configured to convert the 5.5V power provided by the power boost circuit into a second DC power signal, and the second DC power signal is used to instruct the chip detection circuit to provide the operating voltage.
9. The chip detection interface circuit according to any one of claims 1 to 8, further comprising a data communication interface circuit electrically connected to the main control circuit and the chip detection host, respectively, for interacting with the chip detection host through RS485 communication.
10. The chip detection interface circuit according to claim 9, wherein the main control circuit further comprises a main control chip, a reset circuit, a debug circuit, a display circuit, a key circuit, a crystal oscillation circuit, and a buffer output circuit; wherein the content of the first and second substances,
the main control chip is electrically connected with the reset circuit, the debugging circuit, the display circuit, the key circuit, the crystal oscillation circuit and the buffer output circuit respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121046505.3U CN215526028U (en) | 2021-05-14 | 2021-05-14 | Chip detection interface circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121046505.3U CN215526028U (en) | 2021-05-14 | 2021-05-14 | Chip detection interface circuit |
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| Publication Number | Publication Date |
|---|---|
| CN215526028U true CN215526028U (en) | 2022-01-14 |
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| CN202121046505.3U Active CN215526028U (en) | 2021-05-14 | 2021-05-14 | Chip detection interface circuit |
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| CN (1) | CN215526028U (en) |
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