CN215299254U - Semiconductor device with a plurality of transistors - Google Patents

Abstract

The utility model provides a semiconductor device, including the substrate, the bit line structure and being located storage node contact plug between the bit line structure, the lateral wall of bit line structure is formed with first interval layer, second interval layer, wherein, the second interval layer includes silicon. Compare single material interval side wall structure, the utility model provides an among the semiconductor device, including silicon in the second interval layer of bit line structure lateral wall, can effectively reduce bit line electric capacity to improve the RC delay of bit line, make the device have higher performance.

Description

Semiconductor device with a plurality of transistors

Technical Field

The utility model relates to the field of semiconductor technology, especially, relate to a semiconductor device.

Background

With the development of semiconductor technology, the density of semiconductor devices in an integrated circuit increases, and the spacing between adjacent semiconductor devices also decreases, so that the parasitic effect generated between adjacent conductive portions is not negligible.

Specifically, for a Dynamic Random Access Memory (DRAM), the DRAM generally includes a Memory cell array including a plurality of Memory cells arranged in an array, and the DRAM further includes a plurality of bit lines, each bit line is electrically connected to a corresponding Memory cell, and the DRAM further includes a storage capacitor for storing charges representing stored information, and the Memory cells may be electrically connected to the storage capacitor through a contact plug, so as to implement a storage function of each Memory cell. As described above, as the semiconductor size is continuously reduced, the arrangement density of the semiconductor devices is increased, and accordingly, a large parasitic effect and RC delay may exist between adjacent bit lines, between adjacent contact plugs, and the like, which may affect the performance of the device.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a semiconductor device to reduce the bit line electric capacity, improve the RC delay of bit line, improve the performance of device.

To achieve the above object, the present invention provides a semiconductor device including:

correspondingly, the utility model also provides a semiconductor device, include:

a substrate, a first electrode and a second electrode,

a bit line structure over the substrate, wherein the bit line structure includes a bit line node contact plug and a bit line;

storage node contact plugs between the bit line structures;

a first spacer layer between a sidewall of the bit line structure and the storage node contact plug;

a second spacer layer between the first spacer layer and the storage node contact plug;

wherein the second spacer layer comprises silicon.

Optionally, the second spacer layer comprises discontinuous silicon.

Optionally, the discontinuous silicon is separated by air gaps.

Optionally, the air gap is located between the silicon and the storage node contact plug.

Optionally, the display device further comprises a third spacer layer located between the first spacer layer and the second spacer layer.

Optionally, a fourth spacer layer is further included between the second spacer layer and the storage node contact plug.

Optionally, a bit line node contact hole is formed around the bit line structure, the bit line node contact plug is located in the bit line node contact hole, and the first spacer layer and the third spacer layer cover an inner wall of the bit line node contact hole.

Optionally, a fifth spacer layer is further included, the fifth spacer layer fills the bit line node contact hole, and the second spacer layer and the fourth spacer layer are connected to a top surface of the fifth spacer layer.

Optionally, a top surface of the fifth spacer layer is lower than a top end of the bit line node contact plug.

Optionally, the bit line structure further includes a mask pattern on the bit line, wherein a topmost portion of the silicon in the second spacer is higher than a bottommost portion of the mask pattern.

To sum up, the utility model provides a semiconductor device, including the substrate, the bit line structure and being located storage node contact plug between the bit line structure, the lateral wall of bit line structure is formed with first interval layer, second interval layer, wherein, the second interval layer includes silicon. Compare single material interval side wall structure, the utility model provides an among the semiconductor device, including silicon in the second interval layer of bit line structure lateral wall, can effectively reduce bit line electric capacity to improve the RC delay of bit line, make the device have higher performance. Furthermore, an air gap is formed in a second interlayer of the spacer side wall, the air gap is located between the silicon and the storage node contact plug, and the silicon in the second interlayer is isolated by the air gap, so that the electrical characteristics between the storage node plug and the bit line are effectively improved, and the device performance is improved.

Drawings

Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

fig. 2 is a simplified layout of a semiconductor device according to a first embodiment of the present invention;

fig. 3A to fig. 3K are schematic structural diagrams of a corresponding flow of a manufacturing method of a semiconductor device according to an embodiment of the present invention, and fig. 3L is a schematic partial structural diagram of the semiconductor device according to the embodiment of the present invention, where fig. 3A to fig. 3L are schematic sectional diagrams of the structure in fig. 2 along a-a';

fig. 4 is a schematic partial structural diagram of a semiconductor device according to a second embodiment of the present invention;

fig. 5A is a schematic partial structural view of a spacer wall in a semiconductor device according to an embodiment of the present invention;

fig. 5B is a schematic partial structural view of a spacer wall in a semiconductor device according to an embodiment of the present invention.

Wherein the reference numerals are:

100. 200-a substrate; 101. 202-a first insulating layer; 110. 220-trench isolation structure;

120. 220-bit line architecture; 120a, 220 a-bit line node contact holes; 121. 221-bit line node contact plugs; 122. 222-bit line; 123. 223-mask pattern;

130. 230-spacer sidewalls; 131. 231-a first spacer layer; 132. 232-third spacer layer; 133. 233-a fifth spacer layer; 134. 234-second spacer layer; 135. 235-a fourth spacer layer;

134a, 234 a-silicon; 134 b-silicon oxide; 234 b-air gap;

140. 240-storage node contact plugs; 140a, 240 a-storage node contact hole; 241-opening; 251-a lower electrode;

a BL-bit line structure; WL-word line; SC-storage node contact plugs; a DC-bit line node contact hole; S/D1-first doped region; S/D2-second doped region.

Detailed Description

The following description of the embodiments of the present invention will be described in more detail with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in simplified form and are not to precise scale, and are provided for convenience and clarity in order to facilitate the description of the embodiments of the present invention.

Example one

Fig. 3K is a schematic diagram of a partial structure of the semiconductor device provided in this embodiment, and fig. 2 is a simplified layout of the semiconductor device in fig. 3K, where fig. 3K is a schematic cross-sectional diagram of the semiconductor device structure in fig. 2 in a direction a-a'. As shown in fig. 2 and 3K, the semiconductor device includes:

a substrate 100;

a bit line structure 120 located over the substrate 100, wherein the bit line structure 120 includes a bit line node contact plug 121 and a bit line 122;

storage node contact plugs 140 between the bit line structures 120;

a first spacer 131 between a sidewall of the bit line structure 120 and the storage node contact plug 140;

a second spacer layer 134 between the first spacer layer 131 and the storage node contact plug 140;

wherein the second spacer layer 134 comprises silicon.

Specifically, the substrate 100 has a plurality of active areas AA extending in a first direction (Z direction) and trench isolation Structures (STI)110 formed therein, the trench isolation structures STI separating adjacent active areas AA. The active areas AA are arranged in an array mode, and the active areas AA are mutually independent through the groove isolation structure STI, so that mutual interference among the active areas AA is avoided.

The substrate 100 further has a plurality of word lines WL formed therein, the word lines extending along a second direction (X direction) and intersecting with corresponding active regions AA, and first and second doped regions S/D1 and S/D2 formed in the active regions AA, and the first and second doped regions S/D1 and S/D2 disposed at both sides of the word lines WL, respectively.

A plurality of bit line structures (BL)120 are formed on the substrate 100 to extend along a third direction (Y direction) to pass through the respective active areas AA. Referring to fig. 3K, the bit line structure 120 includes a bit line node contact plug 121, a bit line 122 and a mask pattern 123 stacked in sequence. Wherein the content of the first and second substances,the bit line 122 is located on a first insulating layer 101 on the substrate 100, and a material of the first insulating layer 101 includes silicon oxide (SiO), for example₂) Silicon nitride (SiN), or silicon oxynitride (SiON), the material of the bit line node contact plug 121 includes, for example, doped polysilicon, the bit line 122 includes stacked bit line conductive layers including, for example, at least one of tungsten (W), aluminum (Al), copper (Cu), nickel (Ni), or cobalt (Co), and a diffusion barrier layer including at least one of titanium nitride (TiN), titanium/titanium nitride (Ti/TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), or tungsten nitride (WN). The material of the mask pattern 123 includes, for example, at least one of a silicon nitride (SiN) layer or a silicon oxynitride (SiON) layer.

The bit line structure 120 may define a bit line node contact hole (DC)120a, the bit line node contact hole 120a receiving a bit line node contact plug 121. Wherein at least a portion of the bottom of the bit line node contact plug 121 may further extend into the substrate 100 to connect with the second doped region S/D2. A storage node contact hole 140a exposing the first doping region S/D1 is also formed in the substrate 100, a storage node contact plug (SC)140 is formed in the storage node contact hole 140a between the bit line structures 120 and connected to the first doping region S/D1, and a material of the storage node contact plug 140 includes, for example, doped polysilicon.

Further, spacer sidewalls 130 are further formed on sidewalls of the bit line structures 120, and the spacer sidewalls 130 at least cover sidewalls of the bit lines 122 and sidewalls of the mask patterns 123 stacked in sequence. The spacer 130 is located between the bit line node contact plug 140 and the storage node contact plug 121, so that leakage current between the bit line node contact plug 121 and the storage node contact plug 140 is effectively reduced or prevented.

The spacer sidewall spacers 130 include first spacers 131 and second spacers 134, the first spacers 131 are located between the sidewalls of the bit line structures 120 and the storage node contact plugs 140, the second spacers 134 are located between the first spacers 131 and the storage node contact plugs 140, and the second spacers 134 include silicon.

Optionally, the spacer sidewall 130 further includes a third spacer 132, and the third spacer 132 is located between the first spacer 131 and the second spacer 134. Optionally, the spacer sidewall spacers 130 further include a fourth spacer layer 135, and the fourth spacer layer 135 is located between the second spacer layer 134 and the storage node contact plug 140. Optionally, the spacer sidewall 130 further includes a fifth spacer layer 133, and the bit line node contact hole 120a is filled with the fifth spacer layer 133. Wherein the first spacer layer 131 and the third spacer layer 132 cover the inner wall of the bit line node contact hole 120a, the second spacer layer 134 and the fourth spacer layer 135 are connected to the top surface of the fifth spacer layer 133, and the top surface of the fifth spacer layer 133 is lower than the top end of the bit line node contact plug 121.

Fig. 5A is a schematic partial structural view of the spacer 130 in the semiconductor device provided in this embodiment. As shown in fig. 5A, the second spacers 134 in the spacer sidewalls 130 comprise silicon, and preferably, the second spacers 134 comprise discontinuous silicon. Specifically, the second spacer layer 134 includes silicon 134a and silicon oxide 134b, the discontinuous silicon 134a and the silicon oxide 134b are randomly staggered, and the discontinuous silicon 134a is disposed adjacent to the first spacer layer 131. The silicon oxide 134b is located between the discontinuous silicon 134a and the storage node contact plug 140, in this embodiment, between the discontinuous silicon 134a and the fourth spacer layer 135, and the discontinuous silicon 134a is isolated by the silicon oxide 134 b. For example, a silicon layer may be deposited on the sidewalls of the third spacers 132, and then the silicon layer may be processed by an Atomic Layer Deposition (ALD) process and an in-situ water vapor oxidation (ISSG) process, in order, to form the second spacers 134 containing silicon.

Compared with the existing memory structure in which a single material spacer structure is adopted, in the semiconductor device provided by this embodiment, the second spacer in the spacer of the bit line structure includes silicon, and the silicon dioxide are distributed at intervals on the sidewall of the bit line structure, so that the bit line capacitance is effectively reduced, the RC delay of the bit line is improved, and the device has higher performance.

Correspondingly, the embodiment also provides a preparation method of the semiconductor device. Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to this embodiment. As shown in fig. 1, the method for manufacturing a semiconductor device includes:

step S01: providing a substrate;

step S02: forming a bitline structure 120 on the substrate 100;

step S03: sequentially forming a first spacer 131 and a second spacer 134 on sidewalls of the bit line structure 120, wherein the second spacer 134 comprises silicon; and the number of the first and second groups,

step S04: storage node contact plugs 140 are formed between the bit line structures 120.

The method for manufacturing the semiconductor device provided in this embodiment will be described in detail below with reference to fig. 3A to 3K.

Referring to fig. 2 and fig. 3A, step S01 is performed to provide the substrate 100. The substrate 100 is, for example, a silicon substrate (silicon substrate), a silicon containing substrate (silicon containing substrate), an epitaxial silicon substrate (epitaxial silicon substrate), a silicon-on-insulator substrate (silicon-on-insulator substrate), or the like. A trench isolation Structure (STI)110 is formed in the substrate 100, and a plurality of active regions AA are defined by the STI structure. The active regions AA are distributed in an array, and each active region AA comprises two source/drain regions, namely a first doping region S/D1 and a second doping region S/D2. The STI is formed by, for example, forming at least one isolation trench in the substrate 100 by etching, and then filling the isolation trench with an insulating material (such as silicon oxide or silicon oxynitride), but not limited thereto.

The substrate 100 further has a plurality of word lines WL formed therein, the word lines extending along a second direction (X direction) and intersecting with corresponding active regions AA, and the first and second doped regions S/D1 and S/D2 in the active regions AA are disposed at both sides of the word lines WL, respectively.

Next, referring to fig. 3A and 3B, step S02 is performed to form the bit line structure 120 on the substrate 100.

Specifically, the first insulating layer 101 is formed over the substrate 100, and the first insulating layer 101 may be formed of one or more insulating films, for example, the first insulating layer 101 may be formed of at least one film layer of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. Then, the first insulating layer 101 and a portion of the substrate 100 are etched to form an opening exposing a portion of the second doping region S/D2 to form a bit line node contact hole 120a, then a conductive layer and a mask layer are formed on the first insulating layer 101, and then a mask pattern 123, a bit line 122 and a bit line node contact plug 121 located in the bit line contact hole 120a are sequentially formed through a patterning process to form a bit line structure 120.

The material of the first insulating layer 101 includes, for example, silicon oxide (SiO)₂) Silicon nitride (SiN), or silicon oxynitride (SiON), the material of the bit line node contact plug 121 includes, for example, doped polysilicon, the bit line 122 includes stacked bit line conductive layers including, for example, at least one of tungsten (W), aluminum (Al), copper (Cu), nickel (Ni), or cobalt (Co), and a diffusion barrier layer including at least one of titanium nitride (TiN), Ti/TiN, titanium silicon nitride (TiSiN), tantalum nitride (TaN), or tungsten nitride (WN). The material of the mask pattern 123 includes, for example, at least one of a silicon nitride (SiN) layer or a silicon oxynitride (SiON) layer. In this embodiment, the first insulating layer 101, the mask pattern 123, the bit lines 122, and the bit line node contact plugs 121 may be formed by a chemical vapor deposition process (CVD) or a physical vapor deposition Process (PVD).

Next, referring to fig. 3C and fig. 3I, step S03 is performed to form spacer sidewalls 130 on the sidewalls of the bit line structures 120. The spacer sidewalls 130 cover sidewalls of the mask pattern 123, the bit lines 122, and the bit line node contact plugs 121.

Specifically, referring to fig. 3C, the first spacer layer 131 is formed, the first spacer layer 131 covers the first insulating layer 101 and the bit line structure 120, and the material of the first spacer layer 101 is, for example, silicon nitride.

Next, referring to fig. 3D, third spacer layers 132 are formed on the first spacer layers 131, the material of the third spacer layers 132 is, for example, silicon oxide, and the first spacer layers 131 and the third spacer layers 132 cover the inner walls of the bit line node contact holes 120 a.

Next, referring to fig. 3E, the fifth spacer layer 133 is formed, for example, the third spacer layer 132 may be covered with the fifth spacer layer 133 thick enough to fill the bit line node contact hole 120a, and then a portion of the fifth spacer layer 133 is etched away, leaving a portion located in the bit line node contact hole 120 a. The material of the fifth spacer layer 133 is, for example, silicon nitride. Wherein the top surface of the fifth spacer layer 133 is lower than the top end of the bit line node contact plug 121.

Next, referring to fig. 3F, the second spacer layer 134 is formed. The second spacer 134 in the spacer sidewall 130 comprises silicon, and preferably, the second spacer 134 comprises discontinuous silicon. Specifically, the second spacer 134 includes silicon 134a and silicon oxide 134b, the silicon 134a and the silicon oxide 134b are randomly distributed in a staggered manner, the silicon 134a is disposed near the first spacer 131, the silicon oxide 134b is disposed between the silicon 134a and the storage node contact plug 140, in this embodiment, between the silicon 134a and the fourth spacer 135, and the silicon 134a is isolated by the silicon oxide 134b, as shown in fig. 5 a. For example, a silicon layer may be deposited on the sidewalls of the third spacers 132, and then the silicon layer may be processed by an Atomic Layer Deposition (ALD) process and an in-situ water vapor oxidation (ISSG) process, in order, to form the second spacers 134 including silicon 134 a. Of course, in other embodiments of the present invention, other methods may be used to form the discontinuous silicon-containing second spacer layer, and the present invention is not limited thereto.

Next, referring to fig. 3G, the third spacer 132 and the second spacer 134 are etched, so that the third spacer 132 and the second spacer 134 cover the sidewalls of the first spacer 131, wherein the third spacer 132 and the second spacer 134 after etching are in contact with the fifth spacer 133, the topmost of the third spacer 132 and the second spacer 134 is higher than the bottommost of the mask pattern 123 in the bit line structure 120, and the topmost of the silicon 134a in the second spacer 134 is higher than the bottommost of the mask pattern 123.

Next, referring to fig. 3H and fig. 3I, forming the fourth spacer 135, for example, forming the fourth spacer 135 covering the bit line structure 120 and the first insulating layer 101 on the substrate 100, and then, etching to make the fourth spacer 135 cover the sidewalls of the bit line structure 120 and stack the sidewalls of the second spacer 134 (including the top position covering the second spacer 134), thereby completing the formation of the spacer sidewalls 120. The fourth spacer layer 135 is positioned between the second spacer layer 134 and the storage node contact plug 140, and the second spacer layer 134, the fourth spacer layer 135 and the top surface of the fifth spacer layer 133 are connected. The material of the fourth spacer layer 135 is, for example, silicon nitride.

Next, referring to fig. 3J, a portion of the first insulating layer 101 and the substrate 100 is etched to form a storage node contact hole 140a exposing the first doping region S/D1, wherein the storage node contact hole 140a may expose the fourth spacer layer 135 and the fifth spacer layer 133, but not the second spacer layer 134. Then, a conductive layer is filled in the storage node contact hole 140a and a planarization process is performed to form a storage node contact plug 140. The spacer 130 is located between the bit line node contact plug 140 and the storage node contact plug 121, so that leakage current between the bit line node contact plug 121 and the storage node contact plug 140 is effectively reduced or prevented.

In addition, the spacer sidewall 130 may also be a stacked structure composed of a first spacer 131, a fifth spacer 133, a second spacer 134, and a fourth spacer 135, as shown in fig. 3L. The first spacer 131 covers sidewalls of the bit line structure 120 and inner walls of the bit line node contact holes 120a, the fifth spacer 133 fills the bit line node contact holes 120a, the second spacer 134 and the fourth spacer 135 are sequentially formed on the sidewalls of the first spacer 131 and contact top surfaces of the fifth spacer 133, a topmost portion of the second spacer 134 is higher than a bottommost portion of the mask pattern 123 in the bit line structure 120, and a topmost portion of the silicon 134a in the second spacer 134 is higher than a bottommost portion of the mask pattern 123. In other embodiments of the present invention, the structure of the spacer 130 may also be in other forms, for example, the spacer 130 includes a stacked structure composed of a first spacer 131, a fifth spacer 133 and a second spacer 134, that is, the sidewall of the bit line structure 120 is a stacked first spacer 131 and second spacer 134, and the second spacer 134 includes silicon. Correspondingly, when the laminated structures of the spacer sidewalls 130 are different, the material and the thickness of each spacer layer in the laminated structures are correspondingly changed, and the corresponding design can be performed according to the structural requirements of specific devices.

It should be noted that, in this embodiment, the spacer 130 is a stacked structure composed of a first spacer 131, a third spacer 132, a fifth spacer 133, a second spacer 134 and a fourth spacer 135, wherein the first spacer 131, the third spacer 132, the second spacer 134, the fourth spacer 135 and the fifth spacer 135 are sequentially a silicon nitride layer, a silicon oxide layer, a silicon nitride layer, a silicon oxide layer containing silicon and a silicon nitride layer, that is, a composite layer structure of a silicon nitride layer-a silicon oxide layer-a silicon nitride layer sequentially stacked from inside to outside from the bit line structure 120. The spacer 130 is of a structure in which a silicon nitride layer, a silicon oxide layer and a silicon nitride layer are sequentially stacked from inside to outside, and the width of the spacer 130 in the extending direction of the active region is much smaller than that of a spacer structure of a single material layer, so that the widths of the storage node contact plug and the bit line can be increased on the premise of effectively reducing leakage current and parasitic capacitance, and the performance of the memory can be improved.

Example two

The present embodiment provides a semiconductor device and a method for manufacturing the same, where fig. 4 is a schematic partial structure diagram of the semiconductor device provided in the present embodiment, and fig. 5B is a schematic partial structure diagram of a spacer in the semiconductor device provided in the present embodiment, referring to fig. 4 and fig. 5B, the semiconductor device provided in the present embodiment includes: a substrate 200; a bit line structure 220 over the substrate 200, wherein the bit line structure 220 includes a bit line node contact plug 221, a bit line 222, and a mask pattern 223; and storage node contact plugs 240 between the bit line structures 220. Spacer sidewalls 230 are formed on sidewalls of the bit line structures 220, a first spacer 231 and a second spacer 234 are included between the bit line structures 220, the first spacer 231 is located between the sidewalls of the bit line structures 220 and the storage node contact plugs 240, the second spacer 234 is located between the first spacer 231 and the storage node contact plugs 240, and the second spacer 234 includes silicon.

The substrate 200 has a plurality of active areas AA and trench isolation Structures (STI)210 formed therein, the trench isolation structures STI separating adjacent active areas AA. The active region AA has a first doping region S/D1 and a second doping region S/D2 formed therein. The bit line structure 220 may define a bit line node contact hole (DC)220a, the bit line node contact hole 220a receiving a bit line node contact plug 221. Wherein at least a portion of the bottom of the bit line node contact plug 221 may further extend into the substrate 100 to connect with the second doped region S/D2. A storage node contact hole 240a exposing the first doping region S/D1 is also formed in the substrate 100, and the storage node contact plug (SC)240 is formed at the storage node contact hole 240a, between the bit line structures 220, and connected to the first doping region S/D1.

Further, the spacer sidewall 230 located on the sidewall of the bit line structure 220 at least covers the sidewall of the sequentially stacked bit line 222 and the sidewall of the mask pattern 223. The spacer 230 is located between the bit line node contact plug 240 and the storage node contact plug 221, so that leakage current between the bit line node contact plug 221 and the storage node contact plug 240 is effectively reduced or prevented.

Optionally, the spacer sidewall 230 further includes a third spacer 232, a fourth spacer 235 and the fifth spacer 233, the third spacer 232 is located between the first spacer 231 and the second spacer 234, the fourth spacer 235 is located between the second spacer 234 and the storage node contact plug 240, and the fifth spacer 233 fills the bit line node contact hole 220 a. Wherein the first spacer 231 and the third spacer 232 cover the inner wall of the bit line node contact hole 220a, the second spacer 234 and the fourth spacer 235 are connected to the top surface of the fifth spacer 233, and the top surface of the fifth spacer 233 is lower than the top end of the bit line node contact plug 221.

The difference from the first embodiment is that in the present embodiment, the second spacer 234 in the spacer sidewall 230 includes silicon 234a and an air gap 234B, preferably, the silicon 234a is discontinuous silicon, the silicon 234a is disposed near the first spacer 231, the silicon oxide 234B is located between the silicon 234a and the storage node contact plug 240, i.e., between the silicon 234a and the fourth spacer 235, and the silicon 234a is isolated by the air gap 234B, as shown in fig. 5B. The top surface of the fifth spacer layer 233 may be partially exposed through the air gap 234b, and the air gap 234b formed in the spacer sidewall 130 effectively improves electrical characteristics between the storage node plug 240 and the bit line structure 220, thereby improving electrical characteristics of the device.

For example, a silicon layer may be deposited on the sidewalls of the third spacer 232, and then the silicon layer may be processed by an Atomic Layer Deposition (ALD) process and an in-situ water vapor oxidation (ISSG) process to form a silicon oxide, and then the silicon oxide in the second spacer 234 is etched back to form an air gap 234b in the second spacer 234, and the air gap 234b formed after etching back isolates the silicon 234 a. Preferably, the silicon 234a is discontinuous silicon, and of course, in other embodiments of the present invention, other methods may be used to form the second spacer layer including discontinuous silicon and air gap spacing arrangement, which is not limited herein.

As shown in fig. 4, after the storage node contact plugs 240 are formed, a portion of the storage node contact plugs 240, a portion of the mask pattern 223 on the top of the bit line structure 220, and a portion of the height of the spacer sidewalls 230 are etched to form a plurality of openings 241. The opening 241 corresponds to the bit line structure BL and the spacer sidewall 230, and a portion of the opening 241 extends from a position flush with the top of the storage node contact plug 240 to the mask pattern 223 at the top of the bit line structure BL (and cuts off a portion of the mask pattern 223); and another portion of the opening 241 extends from a position flush with the top of the mask pattern 223 into the spacer 230 (and cuts off a portion of the spacer 230), so that the adjacent storage node contact plugs 240 are separated by the opening 241.

The formation of the air gap 234b in the second spacer 234 can be performed by removing the silicon oxide in the second spacer 234 in the spacer sidewall 230 through the opening 241, that is, an air gap 234b is formed between the first spacer 231 and the fourth spacer 235, and the top opening of the air gap 234b is the corresponding opening 241 connected to the top thereof. Accordingly, a second insulating layer (not shown) is formed in the opening 241, covering the air gap 234 b.

In a further aspect, a capacitor structure is formed, the capacitor structure including a lower electrode, a capacitor dielectric layer, and an upper electrode stacked in sequence on the substrate. Wherein the lower electrode 251 is in contact with the storage node contact plug 240, and the capacitor dielectric layer and the upper electrode are formed over the lower electrode. The capacitor structure may be formed by using the prior art, and will not be described herein.

To sum up, the utility model provides a semiconductor device, semiconductor device includes the substrate, the bit line structure and is located storage node contact plug between the bit line structure, the lateral wall of bit line structure is formed with first interval layer, second interval layer, wherein, the second interval layer includes silicon. Compare single material interval side wall structure, the utility model provides an among the semiconductor device, including silicon in the second interval layer of bit line structure lateral wall, can effectively reduce bit line electric capacity to improve the RC delay of bit line, make the device have higher performance. Furthermore, an air gap is formed in a second interlayer of the spacer side wall, the air gap is located between the silicon and the storage node contact plug, and the silicon in the second interlayer is isolated by the air gap, so that the electrical characteristics between the storage node plug and the bit line are effectively improved, and the device performance is improved.

It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.

It should also be noted that, although the present invention has been described with reference to the preferred embodiments, the above-mentioned embodiments are not intended to limit the present invention. To anyone skilled in the art, without departing from the scope of the present invention, the technical solution disclosed above can be used to make many possible variations and modifications to the technical solution of the present invention, or to modify equivalent embodiments with equivalent variations. Therefore, any simple modification, equivalent change and modification made to the above embodiments by the technical entity of the present invention all still belong to the protection scope of the technical solution of the present invention, where the technical entity does not depart from the content of the technical solution of the present invention.

It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.

It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

The above description is only for the preferred embodiment of the present invention, and does not limit the present invention. Any technical personnel who belongs to the technical field, in the scope that does not deviate from the technical scheme of the utility model, to the technical scheme and the technical content that the utility model discloses expose do the change such as the equivalent replacement of any form or modification, all belong to the content that does not break away from the technical scheme of the utility model, still belong to within the scope of protection of the utility model.

Claims (10)

1. A semiconductor device, comprising:

a substrate, a first electrode and a second electrode,

a bit line structure over the substrate, wherein the bit line structure includes a bit line node contact plug and a bit line;

storage node contact plugs between the bit line structures;

a first spacer layer between a sidewall of the bit line structure and the storage node contact plug;

a second spacer layer between the first spacer layer and the storage node contact plug;

wherein the second spacer layer comprises silicon.

2. The semiconductor device of claim 1, wherein the second spacer layer comprises discontinuous silicon.

3. The semiconductor device of claim 2, wherein the discontinuous silicon is separated by air gaps.

4. The semiconductor device of claim 3, wherein the air gap is between the silicon and the storage node contact plug.

5. The semiconductor device of claim 4, further comprising a third spacer layer between the first spacer layer and the second spacer layer.

6. The semiconductor device according to claim 5, further comprising a fourth spacer layer between the second spacer layer and the storage node contact plug.

7. The semiconductor device according to claim 6, wherein a bit line node contact hole is provided on a peripheral side of the bit line structure, the bit line node contact plug is located in the bit line node contact hole, and the first spacer layer and the third spacer layer cover an inner wall of the bit line node contact hole.

8. The semiconductor device according to claim 7, further comprising a fifth spacer layer filling the bit line node contact hole, the second spacer layer, the fourth spacer layer being connected to a top surface of the fifth spacer layer.

9. The semiconductor device according to claim 8, wherein a top surface of the fifth spacer layer is lower than a top end of the bit line node contact plug.

10. The semiconductor device of claim 1, wherein the bitline structure further comprises a mask pattern on the bitline, wherein a topmost portion of the silicon in the second spacer is higher than a bottommost portion of the mask pattern.

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