CN214746354U

CN214746354U - Power line carrier communication system and air conditioning system

Info

Publication number: CN214746354U
Application number: CN202120201663.5U
Authority: CN
Inventors: 梁董腾; 叶铁英; 刘泉洲; 谢金桂; 杨佳宇
Original assignee: Gree Electric Appliances Inc of Zhuhai
Current assignee: Gree Electric Appliances Inc of Zhuhai
Priority date: 2021-01-25
Filing date: 2021-01-25
Publication date: 2021-11-16
Anticipated expiration: 2031-01-25

Abstract

The utility model discloses a power line carrier communication system and air conditioning system. Wherein, this system includes: the system comprises at least two upper computers and at least two lower computers; the host computer includes: the input end of the first controller chip is connected with the power supply system through the first power supply module, and the output end of the first controller chip is connected with the first end of the first transceiver; the first power supply module is also connected with a multiplexing bus; a first transceiver, the second end of which is connected with the multiplexing bus; the lower computer comprises: the input end of the second controller chip is connected with the multiplexing bus through a second power supply module, and the output end of the second controller chip is connected with the first end of the second transceiver; the second power supply module is also connected with a multiplexing bus; the second transceiver, its second end is connected multiplex bus, through the utility model discloses, can realize the two to one or many to one communication of host computer and lower computer, realize the selectivity power supply of host computer to the lower computer simultaneously.

Description

Power line carrier communication system and air conditioning system

Technical Field

The utility model relates to an electron power technology field particularly, relates to power line carrier communication system and air conditioning system.

Background

Currently, 485 communication modes in the industry are mainly two: one is a four-core twisted pair, two are used for communication, and the other two are used for power supply; the other one is a two-core twisted pair, and the communication and power supply time division multiplexing is realized. The adoption of four-core communication requires rewiring by users, prevents reverse connection between a power supply and the ground, has higher requirements on after-sale installation, and needs in-plant wiring.

The two-core wire power line is adopted, a power supply and communication time division multiplexing scheme is adopted, an upper computer needs larger instantaneous current power supply capacity, a lower computer needs larger energy storage capacitor, the occupied space is occupied, the existing 485 communication scheme is poor in differential mode interference resistance, error data are easily generated, and communication failure is caused, so that only one control can be realized when the wire controller controls an inner machine, and one or more controls cannot be realized.

Aiming at the problem that only one control can be realized when a line controller controls an internal machine in the prior art, and one control can not be realized by two or more controls, an effective solution is not provided at present.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides an in provide a power line carrier communication system and air conditioning system to can only realize one accuse when solving the line controller control internal unit among the prior art, can't realize two accuse one or more accuse one problem.

In order to solve the technical problem, the utility model provides a power line carrier communication system, wherein, the system comprises at least two upper computers and at least one lower computer; the host computer includes:

the input end of the first controller chip is connected with the power supply system through the first power supply module, and the output end of the first controller chip is connected with the first end of the first transceiver; the first power supply module is also connected with a multiplexing bus;

the second end of the first transceiver is connected with the multiplexing bus and is used for transmitting communication signals between the first controller chip and the multiplexing bus through modulation and demodulation;

the lower computer comprises:

the input end of the second controller chip is connected with the multiplexing bus through a second power supply module, and the output end of the second controller chip is connected with the first end of the second transceiver; the second power supply module is also connected with the multiplexing bus;

and the second end of the second transceiver is connected with the multiplexing bus and is used for transmitting communication signals between the second controller chip and the multiplexing bus through modulation and demodulation.

Further, the first transceiver comprises:

the first on-off keying modulator is used for modulating the binary signal output by the first controller chip and then generating an on-off keying signal; the on-off keying signal is a square wave signal with the Baud rate duration of the binary signal as the pulse width;

a first differential signal generator, configured to generate a differential signal based on the ook signal generated by the first ook modulator, and transmit the differential signal to the multiplexed bus;

the first differential signal demodulator is used for demodulating the differential signals transmitted on the multiplexing bus to generate an on-off keying signal;

and the first on-off keying demodulator is used for generating a binary signal based on the on-off keying signal generated by the first differential signal demodulator and transmitting the binary signal to the first controller chip.

Further, the first ook modulator includes:

the voltage-controlled oscillator is used for generating a local oscillator signal with preset frequency;

a mixer for generating an on-off keying signal based on the local oscillator signal and the binary signal.

Further, the mixer outputs an on-off keying signal of a preset frequency when the value of the binary signal output by the first controller chip is 1, and outputs a low level signal when the value of the binary signal output by the first controller chip is 0.

Further, the first ook demodulator includes:

the baud rate timer is used for generating baud rate duration and transmitting the baud rate duration to the clock sampler;

the clock sampler is used for sampling and detecting the on-off keying signals within each baud rate duration and determining a zone bit according to the detected values of the on-off keying signals;

a buffer to generate a binary signal based on the flag bits of the clock sampler.

Further, the clock sampler is further to:

performing sampling detection on the on-off keying signal for multiple times within each baud rate duration;

within a baud rate duration, marking a position 1 each time a high level is detected;

at least once a low level is detected within one baud rate duration, a flag is set to 0.

Further, the first transceiver further comprises:

and the first logic controller is used for controlling the frequency of the local oscillation signal generated by the voltage-controlled oscillator or the baud rate duration generated by the baud rate timer.

Further, the first controller chip is also connected with the first power supply module through a control line, and the first controller chip is used for generating a random number so as to determine whether the first power supply module has power supply authority through the random number.

Further, the second transceiver comprises:

the second on-off keying modulator is used for modulating the binary signal output by the second controller chip to generate an on-off keying signal;

a second differential signal generator, configured to generate a differential signal based on the on-off keying signal generated by the second on-off keying modulator, and transmit the differential signal to the multiplexing bus;

a second differential signal demodulator for demodulating the differential signal transmitted on the multiplexed bus to generate an on-off keying signal,

and the second on-off keying demodulator is used for generating a binary signal based on the on-off keying signal generated by the second differential signal demodulator and transmitting the binary signal to the second controller chip.

Further, the system further comprises:

the first isolation circuit is arranged between the first power supply module and the multiplexing bus and used for blocking communication signals on a communication bus from being coupled to the first power supply module;

and the second isolation circuit is arranged between the second power supply module and the multiplexing bus and used for blocking the communication signals on the communication bus from being coupled to the second power supply module.

Further, the first isolation circuit includes:

a first unidirectional element disposed between the first terminal of the first power module and the first line of the multiplexed bus, the first unidirectional element having an anode connected to the first terminal of the first power module and a cathode connected to the first line of the multiplexed bus;

a first inductor disposed between the first unidirectional element and a first line of the multiplexed bus;

a second unidirectional element disposed between the second terminal of the first power module and the second line of the multiplexed bus, having an anode connected to the second terminal of the first power module and a cathode connected to the second line of the multiplexed bus;

a second inductance disposed between the second unidirectional element and a second line of the multiplexed bus.

Further, the second isolation circuit includes:

a third unidirectional element, a fourth unidirectional element, a fifth unidirectional element, and a sixth unidirectional element;

the anode of the third unidirectional element is connected with the cathode of the fifth unidirectional element and then connected with the first line of the multiplexing bus;

the anode of the fourth unidirectional element is connected with the cathode of the sixth unidirectional element and then connected with the second line of the multiplexing bus;

after the cathode of the third unidirectional element is connected with the cathode of the fourth unidirectional element, the cathode of the third unidirectional element is connected with the first terminal of the second power supply module;

after the anode of the fifth unidirectional element is connected with the anode of the sixth unidirectional element, the anode of the fifth unidirectional element is connected with the second terminal of the second power supply module;

further, the second isolation circuit further includes:

a third inductor having a first terminal connected to the first line of the multiplexed bus and a second terminal connected between the anode of the third unidirectional element and the cathode of the fifth unidirectional element;

a fourth inductor having a first terminal connected to the second line of the multiplexed bus and a second terminal connected between the anode of the fourth unidirectional element and the cathode of the sixth unidirectional element.

Further, the system further comprises:

a first capacitance disposed between a first output terminal of the first transceiver and a first line of the multiplexed bus,

a second capacitor disposed between a first output terminal of the first transceiver and a second line of the multiplexed bus;

the first capacitor and the second capacitor are used for coupling communication signals on the multiplexing bus to the first transceiver or coupling communication signals emitted by the first transceiver to the multiplexing bus.

Further, the system further comprises:

a third capacitance disposed between the first output terminal of the second transceiver and the first line of the multiplexed bus,

a fourth capacitor disposed between the first output terminal of the second transceiver and the second line of the multiplexed bus;

the third capacitor and the fourth capacitor are used for coupling communication signals on the multiplexing bus to the second transceiver or coupling communication signals sent out by the second transceiver to the multiplexing bus.

The utility model also provides an air conditioning system, including above-mentioned power line carrier communication system, wherein, the host computer is the line controller, the host computer is the air conditioner.

Use the technical scheme of the utility model, modulate and demodulate through first transceiver, make communication signal transmit between first controller chip and multiplexing bus, modulate and demodulate through the second transceiver, make communication signal be in the second controller chip with transmission between the multiplexing bus avoids communication signal anti differential mode interference ability poor, produces wrong data easily, causes the problem of communication failure, makes communication signal transmit between second controller chip and multiplexing bus, realizes the two to one or many to one communication of host computer and lower computer, realizes the selective power supply of host computer to the lower computer simultaneously.

Drawings

Fig. 1 is a block diagram of a power carrier communication system according to an embodiment of the present invention;

fig. 2 is an internal circuit diagram of the upper computer according to the embodiment of the present invention;

fig. 3 is an internal circuit diagram of a lower computer according to an embodiment of the present invention;

fig. 4 is a block diagram of a first transceiver in accordance with an embodiment of the present invention;

fig. 5 is an internal circuit diagram of a first on-off keying modulator according to an embodiment of the present invention;

fig. 6 is an internal circuit diagram of a first ook demodulator according to an embodiment of the present invention;

fig. 7 is an internal circuit diagram of an upper computer according to another embodiment of the present invention;

fig. 8 is an internal circuit diagram of a lower computer according to another embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail with reference to the accompanying drawings, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the embodiments of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, and "a plurality" typically includes at least two.

It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

It should be understood that although the terms first, second, etc. may be used to describe the controller chips in the embodiments of the present invention, the controller chips should not be limited to these terms. These terms are only used to distinguish between controller chips disposed within different machines. For example, the first controller chip may also be referred to as a second controller chip, and similarly, the second controller chip may also be referred to as a first controller chip without departing from the scope of embodiments of the present invention.

The words "if", as used herein, may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to a detection", depending on the context. Similarly, the phrases "if determined" or "if detected (a stated condition or event)" may be interpreted as "when determined" or "in response to a determination" or "when detected (a stated condition or event)" or "in response to a detection (a stated condition or event)", depending on the context.

It is also noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in the article or device in which the element is included.

The following describes in detail alternative embodiments of the present invention with reference to the accompanying drawings.

Example 1

This embodiment provides a power line carrier communication system, and fig. 1 is according to the utility model discloses a power line carrier communication system's structure chart, as shown in fig. 1, this system includes: the system comprises at least two upper computers 1 and at least one lower computer 2; fig. 2 is an internal circuit diagram of the upper computer according to the embodiment of the present invention, as shown in fig. 2, the upper computer 1 includes:

the input end of the first controller chip 11 is connected with the power supply system through a first power module 13, and the output end of the first controller chip is connected with the first end of the first transceiver 12; as shown in fig. 1, the first power module 13 is also connected to the multiplexed bus; a second terminal of the first transceiver 12 is connected to the multiplexed bus for transmitting communication signals between the first controller chip 11 and the multiplexed bus by modulation and demodulation.

Fig. 3 is an internal circuit diagram of the lower computer according to the embodiment of the present invention, as shown in fig. 3, the lower computer 2 includes: the input end of the second controller chip 21 is connected with the multiplexing bus through a second power module 23, and the output end of the second controller chip 21 is connected with the first end of the second transceiver 22; the second power supply module 23 is also connected with a multiplexing bus; and a second end of the second transceiver 22 is connected with the multiplexed bus, and is used for transmitting communication signals between the second controller chip 21 and the multiplexed bus through modulation and demodulation.

In this embodiment, the multiplexed bus can implement time-division multiplexing of two functions of power supply and communication, and the first power module 13 in the upper computer 1 has one end connected to the positive terminal L and the negative terminal N of the power supply system, and has the other end connected to the first line a of the multiplexed bus through the positive terminal OUTP1 and connected to the second line a of the multiplexed bus through the negative terminal OUTN1, so as to obtain electric energy from the power supply system and supply the electric energy to the multiplexed bus and further to the lower computer. The second power module 23 in the lower computer 2 is connected to the first line a of the multiplexed bus through the positive terminal INP and connected to the second line B of the multiplexed bus through the negative terminal INN, and is used for obtaining electric energy on the multiplexed bus.

The power carrier communication system of this embodiment modulates and demodulates through first transceiver, makes communication signal transmit between first controller chip and multiplexing bus, modulates and demodulates through the second transceiver, makes communication signal be in the second controller chip with transmit between the multiplexing bus, avoids communication signal anti-differential mode interference ability poor, produces wrong data easily, causes the problem of communication failure, makes communication signal transmit between second controller chip and multiplexing bus, has realized the two-to-one or many-to-one communication of host computer and lower computer, has realized the selective power supply of host computer to the lower computer simultaneously.

In order to select one or more first power modules 13 to supply power to the lower computer, as shown in fig. 2, the first controller chip 11 includes a control pin PC connected to the control pin PC of the first power module 13 via a control line for generating a random number, so as to determine whether the first power module 13 has power supply authority via the random number, thereby selecting a power supply module.

Example 2

This embodiment provides another power carrier communication system, fig. 4 is a structural diagram of a first transceiver according to an embodiment of the present invention, and in order to implement modulation and demodulation of signals, as shown in fig. 4, the first transceiver 12 includes: the first on-off keying Modulator OOK Modulator1 is configured to input the binary signal 301 through the transmission pin TX, and modulate the binary signal 301 to generate the on-off keying signal 302; the on-off keying signal 302 is a square wave signal with the baud rate duration of the binary signal 301 as the pulse width; a first differential signal generator T1, configured to generate

differential signals

401 and 402 based on the on-off keying signal 302 in two ways, and respectively transmit the differential signals to a first line a of the multiplexed bus and a second line B of the multiplexed bus; a first differential signal demodulator R1, configured to demodulate the

differential signals

401 and 402 transmitted on the multiplexed bus to generate the on-off keying signal 202; the first OOK Demodulator1 is configured to generate a binary signal 201 based on the OOK signal 202, and transmit the binary signal to the first controller chip 11 through the receiving pin RX.

Fig. 5 is an internal circuit diagram of a first on-off keying Modulator according to an embodiment of the present invention, and as shown in fig. 5, the first on-off keying Modulator OOK Modulator1 includes: the VCO is used for generating a local oscillation signal 106 with a preset frequency; and the Mixer is used for synthesizing the binary serial stream signal 301 input by the inlet end In and the local oscillation signal 106 input by the port Lo to generate an OOK signal 302, and outputting the OOK signal 302 by the outlet end Out. The Mixer outputs an on-off keying signal 302 with a preset frequency when the value of the binary signal 301 output by the first controller chip is 1, and outputs a low level signal when the value of the binary signal 301 output by the first controller chip 11 is 0.

Fig. 6 is an internal circuit diagram of a first ook demodulator according to an embodiment of the present invention, and as shown in fig. 6, the first ook demodulator includes: the Baud Rate Timer is used for generating Baud Rate duration and transmitting the Baud Rate duration to the clock sampler; the Clock Sampler is used for sampling and detecting the open key control signal 202 in each baud rate duration and determining a zone bit according to the value of the detected on-off key control signal; buffer 1bit RX Buffer to generate the binary signal 201 based on the flag bits of the Clock Sampler.

Since in practical applications there may be interference signals in the signals transmitted by the multiplexed bus, resulting in errors in the binary signals finally generated, the Clock Sampler is also used to: performing sampling detection on the on-off keying signal for multiple times within each baud rate duration; within a baud rate duration, marking a position 1 each time a high level is detected; at least once a low level is detected within one baud rate duration, a flag is set to 0.

Since the first OOK Modulator1 needs to have a certain frequency when generating the OOK signal 302 and the first OOK Modulator1 needs to have a certain baud rate duration when generating the binary signal 201 in the above scheme, the first transceiver 12 further includes, as shown in fig. 4: a first Logic controller Logic 1 for controlling the frequency of the local oscillator signal 106 generated by the voltage controlled oscillator VCO or the duration of the Baud Rate generated by the Baud Rate Timer, the first Logic controller Logic 1 being further configured to output a first control signal 103 for controlling whether the first differential signal generator T1 is operating, wherein the first control signal 103 comprises a high level signal for controlling the first differential signal generator T1 to operate, and a low level signal for controlling the first differential signal generator T1 to not operate, and output a second control signal 104 for controlling whether the first differential signal demodulator R1 is operating, wherein the second control signal 104 comprises a high level signal for controlling the first differential signal demodulator R1 to operate, and a low level signal for controlling the first differential signal demodulator R1 to not operate, so that when the existing devices of the bus are operating, and new equipment is accessed under the condition of no power failure, so that the chip is ensured not to generate interference on the multiplexing bus before the chip works normally.

The second transceiver 22 in the lower computer is identical in structure and function to the first transceiver 12 in the upper computer 1, and the second transceiver includes: the second on-off keying modulator is used for modulating the binary signal output by the second controller chip and then generating an on-off keying signal; the second differential signal generator is used for generating differential signals based on the on-off keying signals generated by the second on-off keying modulator and transmitting the differential signals to the multiplexing bus; the second differential signal demodulator is used for demodulating the differential signals transmitted on the multiplexing bus to generate on-off keying signals; and the second on-off keying demodulator is used for generating a binary signal based on the on-off keying signal generated by the second differential signal demodulator and transmitting the binary signal to the second controller chip. The structure and function of the second OOK Modulator are the same as those of the first OOK Modulator1, and the second OOK Modulator is the same as that of the first OOK Modulator1, which is not repeated herein.

Fig. 7 is an internal circuit diagram of the upper computer according to another embodiment of the present invention, since the multiplexing bus connects the first power module, the communication signal on the multiplexing bus may be coupled to the first power module to affect power supply, and therefore, as shown in fig. 7, the power carrier communication system further includes: and a first isolation circuit 14, disposed between the first power module 13 and the multiplexed bus, for blocking a communication signal on the communication bus from being coupled to the first power module. The first isolation circuit 14 includes: a first unidirectional device D1 disposed between the first terminal of the first power module 13 and the first line a of the multiplexed bus, having an anode connected to the first terminal of the first power module 13 and a cathode connected to the first line of the multiplexed bus; a first inductance L1 disposed between the first unidirectional element and a first line of the multiplexed bus; a second unidirectional device D2, disposed between the second terminal of the first power module and the second line B of the multiplexed bus, having an anode connected to the second terminal of the second power module and a cathode connected to the second line of the multiplexed bus; a second inductance L2 disposed between the second unidirectional element and a second line of the multiplexed bus. The generation of a large inductive reactance XL through the first inductor L1 and the second inductor L2 blocks the coupling of the high frequency carrier communication signals on the two multiplexed buses to the first power module 13.

Since the communication signal on the multiplexed bus is generally higher in frequency and the capacitor has a characteristic of low impedance, in order to couple the high-frequency communication signal on the multiplexed bus to the first transceiver 12 and simultaneously couple the communication signal emitted by the first transceiver 12 to the multiplexed bus, as shown in fig. 7, the system further includes: a first capacitor C1 disposed between the first output terminal of the first transceiver 12 and the first line a of the multiplexed bus, and a second capacitor C2 disposed between the first output terminal of the first transceiver and the second line of the multiplexed bus; the first capacitor C1 and the second capacitor C2 are used to couple communication signals on the multiplexed bus to the first transceiver 12 or to couple communication signals transmitted by the first transceiver 12 to the multiplexed bus.

Fig. 8 is an internal circuit diagram of a lower computer according to another embodiment of the present invention, since the multiplexing bus connects the second power module, the communication signal on the multiplexing bus may be coupled to the second power module to affect power supply, and therefore, as shown in fig. 8, the power carrier communication system further includes:

and a second isolation circuit 24, disposed between the second power module and the multiplexed bus, for blocking the communication signals on the communication bus from being coupled to the second power module.

In order to realize the non-polar power supply, the second isolation circuit comprises: a third unidirectional element D3, a fourth unidirectional element D4, a fifth unidirectional element D5, and a sixth unidirectional element D6; after the anode of the third unidirectional element D3 is connected with the cathode of the fifth unidirectional element D5, the first line A of the multiplexing bus is connected; the anode of the fourth unidirectional element D4 is connected with the cathode of the sixth unidirectional element and then connected with the second line of the multiplexing bus; the cathode of the third unidirectional element D3 is connected to the cathode of the fourth unidirectional element D4, and then connected to the first terminal of the second power module 23; the anode of the fifth unidirectional element D5 is connected to the anode of the sixth unidirectional element D6, and then connected to the second terminal of the second power module 23;

in order to achieve the isolation function, the second isolation circuit 24 further includes: a third inductor L3 having a first terminal connected to the first line a of the multiplexed bus and a second terminal connected between the anode of the third unidirectional element D3 and the cathode of the fifth unidirectional element D5; a fourth inductor L4 has a first terminal connected to the second line B of the multiplexed bus and a second terminal connected between the anode of the fourth unidirectional element D4 and the cathode of the sixth unidirectional element D6.

Since the communication signal on the multiplexed bus is generally higher in frequency and the capacitor has a characteristic of low impedance, in order to couple the high-frequency communication signal on the multiplexed bus to the first transceiver 12 and simultaneously couple the communication signal emitted by the first transceiver 12 to the multiplexed bus, as shown in fig. 8, the system further includes: a third capacitor C3 disposed between the first output terminal of the second transceiver 22 and the first line a of the multiplexed bus, and a fourth capacitor C4 disposed between the first output terminal of the second transceiver 22 and the second line B of the multiplexed bus; the third capacitor C3 and the fourth capacitor C4 are used to couple communication signals on the multiplexed bus to the second transceiver 22 or to couple communication signals transmitted by the second transceiver 22 to the multiplexed bus.

Example 3

The present embodiment provides another power carrier communication system, including: the system comprises at least two upper computers and at least one lower computer, wherein the connection block diagram of the at least two upper computers and the at least one lower computer is shown in the above-mentioned figure 1. As shown in fig. 2 mentioned above, the upper computer 1 includes the first power supply module 13, the isolation circuit 14, the first transceiver 12, and the first controller chip 11, the above-described core components. The lower computer 2 includes a second power module 23, a second isolation circuit 24, a second transceiver 22, and a second controller chip 21, which are core components.

As shown in fig. 7 mentioned above, a first inductor L1 and a second inductor L2 are respectively connected in series between the first power module 13 of the upper computer 1 and the two multiplexed buses, and a large inductive reactance XL is generated through the first inductor L1 and the second inductor L2 to block the high-frequency carrier communication signals on the two multiplexed buses from being coupled to the first power module 13; a first capacitor C1 and a second capacitor C2 are respectively connected between the first transceiver 12 and the two multiplexed buses in series, and a small capacitive reactance XC is generated by the first capacitor C1 and the second capacitor C2 to couple high-frequency carrier communication signals on the two multiplexed buses to the first transceiver 12 or couple high-frequency carrier communication signals sent by the first transceiver 12 to the two multiplexed buses; after the upper computer 1 is powered on, power is not supplied to the lower computer 2 for the moment, the first controller chip 11 in the upper computer 1 generates random numbers to compete for the power supply authority of the first power module 13, the first controller chip 11 obtaining the power supply authority controls the first power module 13 connected with the first controller chip to supply power to the two multiplexing buses, and then the power is supplied to the lower computer.

As shown in fig. 8 mentioned above, a third inductor L3 and a fourth inductor L4 are respectively connected in series between the second power module 23 of the lower computer and the two multiplexed buses, and the third inductor L3 and the fourth inductor L4 are used for blocking the coupling of the high-frequency carrier communication signals on the two multiplexed buses to the second power module 23; a third capacitor C3 and a fourth capacitor C4 are respectively connected in series between the second transceiver 22 and the two multiplexed buses, and are used for coupling the high-frequency carrier communication signals on the communication buses to the second transceiver 22 or coupling the high-frequency carrier communication signals of the signal transceiving chips to the two multiplexed buses.

In order to avoid reverse connection of power supply lines, a unidirectional element group is further added between the second power module 23 and the multiplexing bus, so that nonpolar power supply is realized.

As shown in fig. 4 mentioned above, the above-mentioned first transceiver 12 includes: a first OOK Modulator1, a first OOK Demodulator1, a first differential signal generator R1, a first differential signal Demodulator T1, and a first Logic controller 1. When the first controller chip 11 sends a communication signal to the multiplexed bus, a binary serial signal 301 sent by the first controller chip 11 enters an OOK Modulator1 and is modulated into an OOK (on-off keying) signal 302, the OOK signal 302 enters a differential signal generator T through a sending pin TX to generate two differential carrier signals 401 and 402, and the two differential carrier signals are respectively transmitted to a first line a of the multiplexed bus and a second line B of the multiplexed bus; when the first controller chip 11 receives the communication signal from the multiplexed bus, the two differential carrier signals 401 and 402 enter the differential signal Demodulator R and are demodulated into the OOK signal 202, and the OOK signal 202 enters the OOK Demodulator1 and is restored into a binary serial stream signal, and is transmitted to the first controller chip 11 through the receive/compare RX.

As shown in fig. 5 mentioned above, the OOK Modulator1 includes a Mixer, a voltage controlled oscillator VCO; the VCO generates a local oscillation signal 106 with frequency Fc according to frequency information 105 output by a Logic controller1, the Mixer synthesizes a binary serial stream signal 301 input by an inlet end In and the local oscillation signal 106 input by a port Lo to generate an OOK signal 302, and the OOK signal 302 is output by an outlet end Out, wherein the generated OOK signal 302 is a square wave signal with a pulse width being the baud rate duration of the binary serial stream signal 301; when the value of the binary serial stream signal is 1, the OOK signal 302 with the frequency Fc is output, and when the value of the binary signal is 0, the continuous low level is output, and the binary serial stream signal 301 is converted into the OOK302 signal through the above steps.

The differential signal generator T converts the OOK signal 302 into a differential signal. Based on one path of OOK signal 302, two paths of sine/

cosine signals

401 and 402 with 180-degree phase difference are generated; when the OOK signal 302 does not change, the two output sine/

cosine signals

401 and 402 do not change; when the OOK signal 302 changes, the output two sine/

cosine signals

401 and 402 also change accordingly.

The differential signal demodulator demodulates the

differential signals

401 and 402 into the OOK signal 202. Generating a path of OOK signal 202 based on two paths of sine/

cosine signals

401 and 402 with a phase difference of 180 degrees, wherein the generated OOK signal 202 is a square wave signal with a half period of a differential signal 401 and a half period of a differential signal 402 as a pulse width; when the voltage difference Vdif between the two sine/

cosine signals

401 and 402 with the phase difference of 180 degrees exceeds a set value Vt, the value of the OOK signal 202 is at a high level; when the voltage difference Vdif between the two sine/

cosine signals

401 and 402 with a phase difference of 180 ° is lower than the set value Vt, the OOK signal 202 is at a low level.

As shown in fig. 6 mentioned above, the OOK Demodulator1 includes a Clock Sampler, Baud Rate Timer, and a 1-bit RX Buffer, 1bit RX Buffer.

The clock sampler is internally stored with an invalid flag position 0, an effective flag position 1 and an integrator, and is used for sampling and detecting the OOK signal 202 by taking a baud rate duration as a sampling period, so as to judge whether the detected signal value is a high level or a low level, if the detected signal value is the high level, the effective flag position 1 of the integrator is determined, and if the detected signal value is the low level, the effective flag position 0 of the integrator is determined, and the clock sampler is also used for determining whether the input signal is an interference signal, so as to realize the function of filtering the interference signal. Specifically, sampling is performed for multiple times in a sampling period, whether signal values detected in the sampling period are all high levels is judged, if yes, the OOK signal 202 is judged to be a normal signal, the integrator is cleared after recording an effective mark position 1, if not, the input signal is judged to be an interference signal, and the mark position of the integrator is cleared after 0.

The 1-bit RX buffer outputs a 1-bit binary digit 1 at the valid flag position 1 of the integrator, and outputs a 1-bit binary digit 0 at the valid flag position 0 of the integrator.

The baud rate timer is used for generating baud rate duration according to baud rate duration information 102 output by the Logic controller, providing the baud rate duration to the clock sampler, judging whether the baud rate duration reaches one time, and controlling the 1-bit RX buffer to output 1-bit binary digits after the baud rate duration reaches one time.

The power carrier communication system of the embodiment can realize 485 nonpolarity communication and high-power nonpolarity power supply, and can be popularized and applied to all products using 485 communication.

The above-described system embodiments are merely illustrative, wherein the modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.

Example 4

The embodiment provides an air conditioning system, including the power line carrier communication system in the above-mentioned embodiment, at this air conditioning system, the host computer is the line controller, and the next machine is the air conditioner, through above-mentioned power line carrier communication system, has realized the many-to-one communication of host computer and next machine, has realized the selective power supply of host computer to the next machine simultaneously.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.

Claims

1. A power carrier communication system is characterized by comprising at least two upper computers and at least one lower computer; the host computer includes:

the lower computer comprises:

2. The system of claim 1, wherein the first transceiver comprises:

3. The system of claim 2, wherein the first ook modulator comprises:

4. The system of claim 3, wherein the mixer outputs an on-off keying signal of a preset frequency when the value of the binary signal output from the first controller chip is 1, and outputs a low level signal when the value of the binary signal output from the first controller chip is 0.

5. The system of claim 2, wherein the first ook demodulator comprises:

6. The system of claim 5, wherein the clock sampler is further to:

7. The system of claim 3 or 5, wherein the first transceiver further comprises:

8. The system of claim 1, wherein the first controller chip is further connected to the first power module through a control line, and the first controller chip is configured to generate a random number, so as to determine whether the first power module has power supply authority through the random number.

9. The system of claim 1, wherein the second transceiver comprises:

10. The system of claim 1, further comprising:

11. The system of claim 10, wherein the first isolation circuit comprises:

12. The system of claim 10, wherein the second isolation circuit comprises:

and after the anode of the fifth unidirectional element is connected with the anode of the sixth unidirectional element, the anode of the fifth unidirectional element is connected with the second terminal of the second power supply module.

13. The system of claim 12, wherein the second isolation circuit further comprises:

14. The system of claim 1, further comprising:

15. The system of claim 1, further comprising:

16. An air conditioning system comprising the power carrier communication system of any one of claims 1 to 15, wherein the upper computer is a line controller and the lower computer is an air conditioner.