CN214101223U - Multi-path motor control system for flow type fluorescence - Google Patents

Abstract

The utility model provides a multichannel motor control system for STREAMING fluorescence belongs to medical equipment technical field. The multi-path motor control system for the flow fluorescence comprises a main controller in a chip type structure, wherein the main controller is connected with a plurality of execution assemblies in a cascade mode through a data transmission network, each execution assembly comprises a motor driver connected with the data transmission network and a motor electrically connected with the motor driver, and the motor driver converts received pulse signals which are sent by the main controller through the data transmission network and used for instructing the motor to rotate and direction signals of the rotation direction of the motor into current signals and sends the current signals to one corresponding motor. The multi-path motor control system for the flow fluorescence has the advantages that: the use of the system level chip reduces the number of single chips, changes external communication into bus communication of a CPU and an FPGA in the chip, improves communication bandwidth, ensures that nodes are not limited, is not interfered by the outside, and improves instantaneity, stability and reliability.

Description

Multi-path motor control system for flow type fluorescence

Technical Field

The utility model belongs to the technical field of medical equipment, especially, relate to a multichannel motor control system for STREAMING fluorescence.

Background

As shown in fig. 1, for an existing multi-path motor control system, in the prior art, a single chip microcomputer is generally used to control one path of motor, and the single chip microcomputer realizes the functions of acceleration, deceleration, initial position searching and the like of the motor, and converts a signal of the single chip microcomputer into a coil current signal for driving the motor through a motor driver.

The input signals of the motor driver are generally a pulse signal (step) and a direction control signal (dir), wherein the step signal generally represents that the motor rotates for a fixed angle every time the step signal is turned, and the direction signal controls the forward motion or the reverse motion of the motor. Due to the characteristics of the motor, a change process is needed from stopping the motor to running the motor to a higher speed, otherwise the motor is out of control, the change process is called as a motor acceleration process, and similarly, the motor may be in a deceleration process from running the motor at the high speed to stopping the motor. The details of the control process are realized by a single chip microcomputer, and the single chip microcomputer generates specific acceleration, uniform speed step and dir to a motor driver through an in-chip timer generator so as to drive a motor.

When an application (such as a mechanical arm) needs a plurality of motors to move in a matching way, a plurality of single-chip microcomputers are cascaded in a mode shown in figure 1, a main control chip is usually needed because the plurality of motors need to work in a synchronous matching way, the main control chip is generally realized by using the single-chip microcomputers or computers, and the main control enables the single-chip microcomputers to generate specific motor speed and acceleration signals to control a driver by issuing control instructions.

There are the following problems:

1. the system is complex, a plurality of singlechips are needed for controlling a plurality of motors, the system is complex, the cost is high, and the reliability is low

2. Poor synchronization or real-time: because the multi-path single chip microcomputer is interconnected through a field bus (usually low-speed communication signals such as a serial port, a CAN and the like), the condition that the matching between the motors is not tight enough is easily generated in the multi-path and high-speed motion control occasion

3. The control precision of the single chip microcomputer is not enough, because the single chip microcomputer needs to receive or return control commands at the same time of controlling the motor, the sequential execution characteristic of the single chip microcomputer framework cannot process two or more things in one time slice, the control speed and the acceleration precision of the motor are easily influenced, and us-ms time jitter is usually generated

SUMMERY OF THE UTILITY MODEL

It is an object of the present invention to provide a multi-way motor control system for flow-type fluorescence that addresses at least some of the above problems.

In order to achieve the above purpose, the utility model adopts the following technical proposal: the utility model discloses a multichannel motor control system for STREAMING fluorescence, including the main control unit that is chip formula structure, main control unit has a plurality of executive component through the data transmission network cascade connection, every executive component by the motor drive with data transmission network connection, and rather than the motor constitution of electricity connection, motor drive sends after converting the instruction motor pivoted pulse signal that received main control unit sent through the data transmission network and instruction motor direction of rotation to current signal for the motor rather than the one-to-one.

In the above multi-channel motor control system for streaming fluorescence, the main controller is a system-on-chip, and includes a CPU in the chip and an FPGA logic module connected thereto, where the FPGA logic module sends a corresponding motor control instruction for controlling a motor to a motor driver in each execution component after receiving a control command of the CPU.

In the above-mentioned multi-path motor control system for flow fluorescence, the system-on-chip is an SOC chip.

In the above-described multiplex motor control system for streaming fluorescent light, the data transmission network comprises a field bus.

In the above-mentioned multi-path motor control system for flow fluorescence, the motor is a stepping motor.

Compared with the prior art, the multi-path motor control system for the flow fluorescence has the advantages that:

1. the use of the system level chip greatly reduces the use number of the single chip microcomputer;

2. the existing external communication is changed into bus communication of a CPU and an FPGA in a chip, so that the communication bandwidth is greatly improved, nodes are not limited and are not interfered by the outside, and the real-time performance, the stability and the reliability are greatly improved;

3. the FPGA has the characteristic of completely paralleling logic, the pulse generation precision cannot be reduced due to the increase of the number of motor circuits, the time precision of the pulse frequency can be controlled at ns level generally, and 2 to 3 orders of magnitude improvement can be realized compared with a single chip microcomputer.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 provides a schematic diagram of the operation of a prior art multiple motor.

Fig. 2 provides a working principle diagram of a multi-path motor in the embodiment of the present invention

Fig. 3 provides a working schematic diagram of the embodiment of the present invention in which the FPGA logic generates the motor control pulse signal

Detailed Description

The present invention will be described in further detail by way of examples with reference to the accompanying drawings, which are illustrative of the present invention and are not intended to limit the present invention.

System On Chip, SOC contains logic cores (including CPU, clock circuits, timers, interrupt controllers, serial-parallel interfaces, other peripherals, I/O ports, and glue logic for use between various IP cores, etc.), memory cores (including various volatile, non-volatile, and Cache memories, etc.), analog cores (including analog circuits used in ADC, DAC, PLL, and some high-speed circuits), and the like. A key advantage of SOC technology is that it can reduce the performance limitations on the system board due to the delay of signals going in and out between multiple chips, it also improves system reliability and reduces overall system cost.

FPGA is Field Programmable Gate Array with Field Programmable Gate Array. The FPGA mainly adopts parallel operation and is realized by hardware description language, and compared with a PC or a singlechip (whether in a Von Neumann structure or a Harvard structure), the FPGA has great difference in sequential operation. The FPGA adopts a concept of a Logic Cell array lca (Logic Cell array), and includes three parts, namely, a configurable Logic module clb (configurable Logic block), an input Output module iob (input Output block), and an internal connection (Interconnect). A Field Programmable Gate Array (FPGA) is a programmable device that has a different structure than traditional logic circuits and gate arrays (such as PAL, GAL and CPLD devices). The FPGA utilizes small lookup tables (16 × 1RAM) to realize combinational logic, each lookup table is connected to the input end of a D flip-flop, and the flip-flops drive other logic circuits or drive I/O (input/output) circuits, so that basic logic unit modules capable of realizing both combinational logic functions and sequential logic functions are formed, and the modules are connected with each other or connected to an I/O (input/output) module by utilizing metal connecting wires. The logic of the FPGA is implemented by loading programming data into the internal static memory cells, the values stored in the memory cells determine the logic function of the logic cells and the way of the connections between the modules or between the modules and the I/O and finally the functions that can be implemented by the FPGA, which allows an unlimited number of programming.

CAN: controller Area Network. CAN is a serial communication protocol that is ISO international standardized. It is widely used in industrial automation, ships, medical equipment, industrial equipment, and the like. Is one of the hot spots of the technical development in the current automation field, and is known as a computer local area network in the automation field. The occurrence of the method provides powerful technical support for realizing real-time and reliable data communication among all nodes of a distributed control system.

As shown in fig. 2, the multi-channel motor control system for flow fluorescence comprises a main controller in a chip structure, wherein the main controller is connected with a plurality of execution assemblies in a cascade mode through a data transmission network, each execution assembly comprises a motor driver connected with the data transmission network and a motor electrically connected with the motor driver, and the motor driver converts received pulse signals which are sent by the main controller through the data transmission network and used for instructing the motor to rotate and direction signals for instructing the motor to rotate into current signals and then sends the current signals to the motors in one-to-one correspondence with the pulse signals and the direction signals.

As a specific structure of the main controller in a chip-type structure, in one or some embodiments, the main controller is a system-on-chip, and includes a CPU located in the chip and an FPGA logic module connected thereto, where the FPGA logic module sends a corresponding motor control instruction for controlling a motor to a motor driver in each execution component after receiving a control command of the CPU.

It should be noted that, the CPU part implements flow control and issuing of multiple motor instructions, and the FPGA logic module implements the original functions of multiple singlechips.

In addition, the principle that the FPGA logic module generates the motor control pulse signal is greatly different from the principle that the original single chip microcomputer generates the pulse signal by using a timer, as shown in fig. 3, the pulse generation of the FPGA logic module is generated by using a counter high-order overflow. Specifically, each clock cycle of the pulse control word k is accumulated, an overflow signal is generated at a certain moment due to the limited bit width of the accumulator, when the pulse control word is maintained unchanged, the overflow signal is generated periodically, the period of the overflow signal is T, where T is M/k, the overflow frequency f is k/M, where M is a constant related to the system clock frequency and the counter bit width, the overflow signal is a pulse signal of the driver, and at this time, the motor operates at a constant speed. When the acceleration pulse and the deceleration pulse need to be generated, only the pulse control k needs to be changed, and when the pulse control word becomes large, the frequency of the overflow signal will rise, namely the acceleration process; when the pulse control word is reduced, the frequency of the overflow signal is reduced, namely a deceleration process; if the pulse control word varies linearly with time by one time, k ═ C × t, the pulse frequency will be a uniform acceleration motion, and the acceleration a of the uniform acceleration is a constant: if A is C/M, if the pulse signal controls the wordWhen the change is quadratic linear, i.e. the parabola k equals Ct²The process, the acceleration a of the variable acceleration is: a, C/M t, namely an S-shaped speed curve can be realized; the S-shaped curve can reduce the impact of a motion control system, and has great benefits for improving the motion stability and prolonging the service life of a mechanical system. The acceleration and deceleration control required by the motor can be realized by taking the secondary as a theoretical basis and matching with a necessary control process.

As a specific embodiment of the system-on-chip, the system-on-chip is an SOC chip.

It should be noted that, this system uses a SOC as the main control chip, instead of the original multiple singlechips and main control chip, greatly simplifying the control part circuit, and the circuits such as the motor driver are kept the same as the original one, so that the system can make smooth transition, and improve the compatibility.

It should be noted that the data transmission network refers to a connection network between the soc and the peripheral devices, and is usually interconnected by using a field bus (e.g., a low-speed communication network such as a serial port and a CAN bus).

Also to facilitate control of the motor, in one or some embodiments, a stepper motor is used.

The specific embodiments described herein are merely illustrative of the spirit of the invention. Various modifications, additions and substitutions for the specific embodiments described herein may be made by those skilled in the art without departing from the spirit of the invention or exceeding the scope of the invention as defined in the accompanying claims.

It should be noted that the above terms are used herein only for the convenience of describing and explaining the essence of the present invention, and do not exclude the possibility of using other terms. They are to be construed in a manner that is inconsistent with the spirit of the invention.

Claims (5)

1. A multi-channel motor control system for flow-type fluorescence, characterized by: the motor driver converts received pulse signals of command motor rotation sent by the main controller through the data transmission network and direction signals of command motor rotation direction into current signals and then sends the current signals to the motors in one-to-one correspondence with the pulse signals.

2. The multi-channel motor control system for streaming fluorescent light of claim 1, wherein the main controller is a system-on-chip, and comprises a CPU and an FPGA logic module connected thereto, and the FPGA logic module sends a corresponding motor control command for controlling the motor to the motor driver in each execution module after receiving a control command from the CPU.

3. The multi-channel motor control system for flow fluorescence of claim 2, wherein the system-on-chip is a SOC chip.

4. The multi-motor control system for streaming fluorescence of claim 1, wherein the data transmission network comprises a fieldbus.

5. The multiplexed motor control system for flow fluoroscopy as recited in claim 1 wherein said motor is a stepper motor.

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