CN213276460U

CN213276460U - Double-circuit server mainboard and server

Info

Publication number: CN213276460U
Application number: CN202022754143.5U
Authority: CN
Inventors: 李书通; 李晶晶; 柳胜杰; 袁飞; 杨晓君
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2020-11-25
Filing date: 2020-11-25
Publication date: 2021-05-25
Anticipated expiration: 2030-11-25

Abstract

The utility model provides a two-way server mainboard and server, this server mainboard include a mainboard. The mainboard is provided with a first central processing unit and a second central processing unit which are interconnected through an X16 XGMI bus. The main board is also provided with a first PICE X16 slot which is connected with the second central processing unit through an X8 signal. The main board is also provided with an analog switch which is connected with the second central processing unit through an X8 signal, and the analog switch is also connected with the first PICE X16 slot through an X8 signal. Still be provided with second PICE X16 slot on the mainboard, be connected with analog switch through X8 signal, have the plug-in card simultaneously and be connected at present signal and the GPIO interface of first central processing unit. The system judges whether a second PICE X16 slot has a plug-in card or not through GPIO, and automatically adjusts the PICE slot connected with the second central processing unit into two PICE X8 slots or one PICE X16 slot.

Description

Double-circuit server mainboard and server

Technical Field

The utility model relates to a computer technology field especially relates to a double-circuit server mainboard and server.

Background

The dual-path CPU main board is produced mainly for meeting the professional application requirements of a server, a graphic workstation and the like, so that the workstation main board is greatly different from a common main board, and system compatibility, BIOS function extension and the like are designed for the fields of the server, the graphic workstation and the like. Dual CPU motherboards typically use a server processor that supports dual CPU. The main board is logically a single computer, and an operating system can directly call the resources of two CPUs. If the single-path CPU main board of two ordinary computers is used, more problems are faced. Such as: there is not more display cards of space installation, two ordinary ATX mainboard connection lines are complicated and have a large amount of repeated hardware, need two power supplies to supply power, the space is compact for a long time operation simultaneously and is influenced stability. Data transmission efficiency between the double CPUs of the existing double-path CPU mainboard is low, the PICE slot type connected with the CPUs and arranged on the mainboard is fixed, and once the PICE slot type is determined, adjustment cannot be carried out, so that compatibility of the double-path CPU mainboard is reduced.

SUMMERY OF THE UTILITY MODEL

The utility model provides a double-circuit server mainboard and server for improve the flexibility of PICE slot on the mainboard, improve the compatibility of double-circuit server mainboard.

In a first aspect, the present invention provides a two-way server motherboard, which comprises a motherboard. The mainboard is provided with a first central processing unit and a second central processing unit, wherein the first central processing unit and the second central processing unit are interconnected through a X16 XGMI bus. The main board is also provided with a first PICE X16 slot which is connected with the second central processing unit through an X8 signal. An analog switch (anaglog switch) connected with the second central processing unit through an X8 signal is further arranged on the main board, and the analog switch is further connected with the first PICE X16 slot through an X8 signal. Still be provided with second PICE X16 slot on the mainboard, be connected with analog switch through X8 signal, have the plug-in card simultaneously and be connected at present signal and the GPIO interface of first central processing unit.

In foretell scheme, through set up first PICE X16 slot and second PICE X16 slot on the mainboard, still set up analog switch, the system judges whether there is the plug-in card in second PICE X16 slot through GPIO, automatic PICE slot adjustment that will be connected with second central processing unit is two PICE X8 slots or a PICE X16 slot, the flexibility of PICE slot on the improvement mainboard, improve the compatibility of two-way server mainboard.

In a specific embodiment, the main board is further provided with a plurality of PICE X4 slots connected with the first central processing unit, and each PICE X4 slot is connected with the first central processing unit through an X1 signal. The main board is also provided with a PICE X8 slot which is connected with the first central processing unit through an X8 signal. Through setting up the PICE slot of different grade type on the mainboard to the flexibility of PICE slot on the further mainboard improves the compatibility of dual-circuit server mainboard.

In a specific embodiment, the main board is further provided with at least one 7PIN SATA connector connected to the first central processing unit, wherein each 7PIN SATA connector is used for being plugged into a SATA disk. The main board is also provided with a mini SAS HD connector connected with the first central processing unit. The server mainboard can be connected with the SATA disk in a plug-in mode and can be connected with the NVME solid-state disk in a plug-in mode, and compatibility of the server mainboard with different memories is improved.

In a specific embodiment, the motherboard is further provided with an ALC4042H chip connected to the first central processing unit through a USB interface, and the motherboard is further provided with an Audio Jack connected to the ALC4042H chip, where the Audio Jack is located at the rear end of the server chassis. The dual-path server mainboard can take the PC application field into consideration, and the compatibility of the dual-path server mainboard to different audio type interfaces is improved.

In a specific embodiment, the ALC274 chip connected to the ALC4042H chip is further connected to the main board, the audiohead connected to the ALC274 chip is further disposed on the main board, and the audiohead is connected to the Audio Jack at the front end of the server chassis. Therefore, the front end and the rear end of the server case are provided with the Audio Jack, and different Audio Jacks on different server cases can be selected according to position orientation, distance and the like.

In a specific embodiment, an I350 chip connected with the first central processing unit is further disposed on the motherboard; the mainboard is also provided with at least one double-layer USB3.0+ RJ45 network cable connector, and the at least one double-layer USB3.0+ RJ45 network cable connector is positioned at the rear end of the server case; and the RJ45 network cable interface in each double-layer USB3.0+ RJ45 network cable connector is connected with the I350 chip, and the USB3.0 interface in each double-layer USB3.0+ RJ45 network cable connector is connected with the second central processing unit. Through setting up the USB interface of different grade type, and a plurality of RJ45 net twine interface, make the application configuration requirement of double-circuit server mainboard can satisfy different occasions, improve the function of double-circuit server mainboard.

In a specific embodiment, a USB header including USB3.0&2.0 is further disposed on the motherboard, and the USB header is connected to a USB connector at the front end of the server chassis, when the server motherboard is installed in the chassis, USB interfaces are disposed at the front end and the rear end of the server chassis, and different USB interfaces on the server chassis can be selected according to location, orientation, distance, and the like.

In a specific embodiment, a BMC chip is further disposed on the motherboard, and a UART Serial port interconnection is provided between the first central processor and the BMC chip, so as to implement Serial Over Lan communication between the first central processor and the BMC chip. Compare with the scheme that realizes Serial Over Lan communication through LPC's virtual Serial ports among the prior art, the utility model discloses a UART Serial ports that straighten out with first central processing unit in the scheme realize SOL (Serial Over Lan communication), though 1 more interface, but can debug more information.

In a specific implementation manner, the motherboard is further provided with a data selector connected with the first central processing unit through an SPI bus, and a BIOS chip connected with the data selector through the SPI bus, and the data selector is further connected with the BMC chip through the SPI bus. Therefore, the BIOS chip can be remotely controlled to be connected with the first central processing unit or the BMC chip through the BMC chip.

In a specific embodiment, the motherboard is further provided with a temperature sensor and a fan module interface connected with the BMC chip. So that the temperature of remote monitoring double-circuit server mainboard, the remote control fan module of being convenient for dispels the heat.

In a second aspect, the present invention further provides a server, which comprises a case and any one of the above two-way server mainboards disposed in the case. Through setting up first PICE X16 slot and second PICE X16 slot on the mainboard, still set up analog switch, the system judges whether there is the plug-in card in second PICE X16 slot through GPIO, automatic PICE slot adjustment that will be connected with second central processing unit is two PICE X8 slots or a PICE X16 slot, improve the flexibility of PICE slot on the mainboard, improve the compatibility of two-way server mainboard.

Drawings

Fig. 1 is a block diagram schematically illustrating a structure of a two-way server motherboard according to an embodiment of the present invention;

fig. 2 is a schematic diagram illustrating connection of an analog switch, two central processing units, and two PICE X16 slots on a motherboard of a two-way server according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a two-way server motherboard according to an embodiment of the present invention, where two cpus are connected to a DDR memory;

fig. 4 is a schematic diagram of a connection between a first central processing unit on a motherboard of a two-way server and a 7PIN SATA connector and a mini SAS HD connector according to an embodiment of the present invention;

fig. 5 is a schematic diagram of a connection between a first central processing unit and an Audio Jack on a motherboard of a two-way server according to an embodiment of the present invention;

fig. 6 is a schematic diagram of a two-way server motherboard provided with a USB interface and an RJ45 network interface according to an embodiment of the present invention;

fig. 7 is a schematic diagram of a structure provided by an embodiment of the present invention, in which a first central processing unit is connected to a BMC chip on a motherboard of a two-way server.

Reference numerals:

10-mainboard 11-first central processing unit 12-second central processing unit

20-analog switch 21-first PICE X16 slot 22-second PICE X16 slot

23-PICE X4 slot 24-PICE X8 slot

31-7PIN SATA connector and 32-mini SAS HD connector

41-ALC4042H chip 42-Audio Jack 43-ALC274 chip 44-Audio header

51-I350 chip 52-double-layer USB3.0+ RJ45 network cable connector 53-USB header

61-BMC chip 62-data selector 63-BIOS chip 64-temperature sensor

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

For conveniently understanding the utility model provides a two-way server mainboard, first explain below the utility model provides an application scene of two-way server mainboard, this two-way server mainboard is applied to in the server to as the hardware that realizes each function of server. The two-way server motherboard will be described in detail with reference to the accompanying drawings.

Referring to fig. 1 and fig. 2, a two-way server motherboard according to an embodiment of the present invention includes a motherboard 10. The motherboard 10 is provided with a first central processing unit 11 and a second central processing unit 12, wherein the first central processing unit 11 and the second central processing unit 12 are interconnected through a X16 XGMI bus. The main board 10 is further provided with a first PICE X16 slot 21 connected to the second cpu 12 through an X8 signal. The main board 10 is further provided with an analog switch 20 in signal connection with the second cpu 12 through X8, and the analog switch 20 is further in signal connection with the first PICE X16 slot 21 through X8. The main board 10 is further provided with a second PICE X16 slot 22 connected with the analog switch 20 through an X8 signal, and the second PICE X16 slot 22 is connected with the GPIO interface of the first central processing unit 11 through a plug-in-place signal.

In foretell scheme, through set up first PICE X16 slot 21 and second PICE X16 slot 22 on mainboard 10, still set up analog switch 20, the system judges whether there is the plug-in card in second PICE X16 slot 22 through GPIO, automatic PICE slot adjustment with being connected with second central processing unit 12 is two PICE X8 slots or a PICE X16 slot, improve the flexibility of PICE slot on mainboard 10, improve the compatibility of two-way server mainboard. The arrangement of the above components will be described in detail with reference to the accompanying drawings.

When the motherboard 10 is provided, referring to fig. 1 and 2, the motherboard 10 is a printed circuit board capable of being provided with devices such as a central processing unit. The mainboard 10 is provided with a first central processing unit 11 and a second central processing unit 12, and the first central processing unit 11 and the second central processing unit 12 are interconnected through a path of X16 XGMI bus, so that the transmission rate of GOPs between two CPUs on the two-way CPU mainboard 10 can reach 12.8GT/S at most, and the transmission rate of GOPs between the two CPUs in the two-way CPU mainboard 10 is improved. When the first central processing unit 11 and the second central processing unit 12 are disposed on the motherboard 10, two CPU slots may be disposed on the motherboard 10, and the first central processing unit 11 and the second central processing unit 12 are respectively mounted on the two CPU slots. The two CPU slots may be sockets or slots. When the first central processing unit 11 and the second central processing unit 12 are disposed, the first central processing unit 11 may be a main central processing unit, and the second central processing unit 12 may be a sub-central processing unit. Specifically, when the models of the first central processing unit 11 and the second central processing unit 12 are selected, two pieces of the Hai-Fi 3100/3200CPU chips can be selected as the first central processing unit 11 and the second central processing unit 12.

Referring to fig. 1 and 2, the main board 10 is further provided with a first PICE X16 slot 21 connected to the second cpu 12 through an X8 signal. The main board 10 is further provided with an analog switch 20 in signal connection with the second cpu 12 through X8, and the analog switch 20 is further in signal connection with the first PICE X16 slot 21 through X8. The main board 10 is further provided with a second PICE X16 slot 22 connected with the GPIO interface of the first central processing unit 11 through a card-in-place signal, and the second PICE X16 slot 22 is connected with the analog switch 20 through an X8 signal. Through set up first PICE X16 slot 21 and second PICE X16 slot 22 on mainboard 10, still set up analog switch 20, the system judges whether there is the plug-in card in second PICE X16 slot 22 through GPIO, automatic PICE slot adjustment that will be connected with second central processing unit 12 is two PICE X8 slots or a PICE X16 slot, the flexibility of PICE slot on the improvement mainboard 10, the compatibility of improvement dual-path server mainboard. That is, the second cpu 12 is connected to 2 PICEX16 slots and is connected to X8 signals, respectively. Also, two sets of X8 signals may be combined into a PICEX16 slot, which constitutes a set of X16 signals. As shown in the right side of FIG. 2, when no expansion Card is inserted into the second PICE X16 slot 22 located at the bottom, the Card Present signal is high, and the analog switch 20 switches the A8-15 of the second CPU 12 to the first PICE X16 slot 21 located at the top, and the A0-7 constitute an X16 signal. Meanwhile, the signal is connected to a GPIO interface of the first central processing unit, and when software detects that the next second PICE X16 slot 22 is not inserted with an expansion card through the state of the GPIO interface, the A0-15 of the second central processing unit 12 is configured into a PICEX16 slot connected with an X16 signal. When the next second PICE X16 slot 22 is plugged with an expansion Card, the Card Present signal is low, the analog switch 20 switches the A8-15 of the second CPU 12 to the next second PICE X16 slot 22, and the software automatically configures the A0-15 of the second CPU 12 into 2 PICEX16 slots with X8 signals. Through the mode, the flexibility of PICE slots on the mainboard 10 can be improved, and the compatibility of the double-circuit server mainboard is improved.

With continued reference to fig. 2, a plurality of PICE X4 slots 23 connected to the first cpu 11 may be further disposed on the main board 10, and each of the PICE X4 slots 23 is connected to the first cpu 11 through an X1 signal. Specifically, when the number of the PICE X4 slots 23 is determined, the number of the PICE X4 slots 23 may be 3 as shown in fig. 2, or may be any number not less than 2. As shown in fig. 2, a PICE X8 slot 24 connected to the first cpu 11 through an X8 signal may be further disposed on the main board 10. Through the PICE slot that sets up the different grade type on mainboard 10 to the flexibility of PICE slot on further mainboard 10 improves the compatibility of dual-path server mainboard.

As shown in fig. 3, a plurality of DDR channels may be connected to the first central processor 11, and a plurality of DDR channels may be connected to the second central processor 12. Wherein, each DDR Channel is connected with two DIMM memory slots. The memory frequency of the main board 10 can reach 2933MHz to improve the memory frequency of the main board 10. The number of the DDR channels connected to each central processing unit may be 2, 3, 4, 5, and the like, which improves the memory frequency of the motherboard 10. When each central processing unit is connected with 2 DDR channels, the main board 10 supports 8 DDR4 memory slots altogether, the memory frequency can reach 3200MHz at most, and supports RDIMM and LRDIMM. The connection relationship is shown in the following figure 3, each central processor mounts 4 DDR4 DIMM slots, supports UDIMM/RDIMM/LRDIMM/NVDIMM, and supports DDR 4-3200.

Referring to fig. 4, at least one 7PIN SATA connector 31 connected to the first central processing unit 11 may be further disposed on the main board 10, wherein each 7PIN SATA connector 31 is used for plugging and connecting a SATA disk. Specifically, when the number of 7PIN SATA connectors 31 is determined, the number of 7PIN SATA connectors 31 may be 2 as shown in fig. 4, or may be not less than 2 arbitrary values such as 3, 4, and the like.

With continued reference to fig. 4, a mini SAS HD connector 32 connected to the first central processor 11 may also be provided on the main board 10. The signals on the mini SAS HD connector 32 may be configured as 4 SATA signals to connect to 4 SATA disks, and may also be configured as a PICE signal of X4 to connect to an NVME solid state disk. The server mainboard 10 can be connected with the SATA disk in a plug-in mode and can be connected with the NVME solid-state disk in a plug-in mode, and compatibility of the server mainboard 10 with different memories is improved.

Referring to fig. 5, the motherboard 10 also has designed onboard Audio for PC applications. Specifically, as shown in fig. 5, an ALC4042H chip 41 connected to the first central processing unit 11 through a USB interface may be further disposed on the main board 10, and an Audio Jack42 connected to the ALC4042H chip 41 is further disposed on the main board 10, and the Audio Jack42 is located at the rear end of the server chassis. Specifically, the ALC4042H chip 41 may be connected to the first central processing unit 11 through USB 2.0, the ALC4042H chip 41 supports 2 line in inputs, 2 mic in inputs, and 2 headset phones outputs, these Audio interfaces are connected to the Audio Jack42 on one board side, and when the server chassis is installed, this Audio Jack42 is located at the back end of the chassis. The dual-path server mainboard can take the PC application field into consideration, and the compatibility of the dual-path server mainboard to different audio type interfaces is improved.

With continued reference to fig. 5, an ALC274 chip 43 connected to the ALC4042H chip 41 may be connected to the main board 10, an Audio header44 connected to the ALC274 chip 43 is further disposed on the main board 10, and the Audio header44 is connected to an Audio Jack42 at the front end of the server chassis. Specifically, the ALC4042H chip 41 has an I2S interface, and is connected to the Audio codec ALC274 chip 43 through an I2S interface extension, the ALC274 chip 43 is connected to a mic in and two-way headset out, these signals are connected to a headset, and when the two-way server motherboard is installed in the chassis, the headset is connected to the Audio Jack42 at the front end of the server chassis through a cable. Therefore, the front end and the rear end of the server case are provided with the Audio Jack42, and different Audio Jack42 on the server case can be selected and used according to position orientation, distance and the like.

Referring to fig. 6, an I350 chip 51 connected to the first central processing unit 11 may be further provided on the main board 10; at least one double-layer USB3.0+ RJ45 network cable connector 52 is also arranged on the mainboard 10, and the at least one double-layer USB3.0+ RJ45 network cable connector 52 is positioned at the rear end of the server case; and the RJ45 network cable interface of each dual-layer USB3.0+ RJ45 network cable connector 52 is connected to the I350 chip 51, and the USB3.0 interface of each dual-layer USB3.0+ RJ45 network cable connector 52 is connected to the second cpu 12. Through setting up the USB interface of different grade type, and a plurality of RJ45 net twine interface, make the application configuration requirement of double-circuit server mainboard can satisfy different occasions, improve the function of double-circuit server mainboard. With reference to fig. 6, the motherboard 10 is further provided with a USB header53 including USB3.0&2.0 connected to the first cpu 11, and the USB header53 is connected to a USB connector at the front end of the server chassis, when the server motherboard 10 is installed in the chassis, the front end and the rear end of the server chassis are provided with USB interfaces, and different USB interfaces on the server chassis can be selected according to position orientation, distance, and the like.

Specifically, as shown in fig. 6, the on-board I350 chip 51 is connected to the first central processing unit 11 through X2 PICE 3.0 signals, and two gigabit electrical port (MDI) signals are respectively connected to 2 "USB 3.0 × 2+ RJ 45" connectors below the I350 chip 51, and have 6 USB3.0 interfaces. The first cpu 11 outputs 2 USB3.0&2.0 channels to connect to a USB header53, and when the two-channel server motherboard is placed in the server chassis, the USB signal on this header is connected to the USB connector at the front end of the chassis via a cable. The 4 USB3.0&2.0 signals on the second cpu 12 are connected to 2 "USB 3.0 × 2+ RJ 45" connectors, respectively, to form 4 USB3.0 interfaces. When the two-way server mainboard is installed in a chassis of a server, the 4 interfaces are located at the rear end of the chassis. Through setting up the USB interface of different grade type, and a plurality of RJ45 net twine interface, make the application configuration requirement of double-circuit server mainboard can satisfy different occasions, improve the function of double-circuit server mainboard.

Referring to fig. 7, a BMC chip 61 may also be provided on the motherboard 10, and the BMC chip 61 may be an onboard ASPEED AST2500 management chip. The onboard ASPEED AST2500 management chip supports network interfaces to allow remote management of the system, and the BMC chip 61 is designed for server applications. A plurality of rich interfaces can be arranged between the BMC chip 61 on the motherboard 10 and the first central processor 11 to realize interaction of various information.

For example, as shown in fig. 7, a UART Serial port interconnection may be provided between the first central processor 11 and the BMC chip 61, so as to implement Serial Over Lan communication between the first central processor 11 and the BMC chip 61. Compare with the scheme that realizes Serial Over Lan communication through LPC's virtual Serial ports among the prior art, the utility model discloses a UART Serial ports that straighten out with first central processing unit 11 in the scheme realize SOL (Serial Over Lan communication), though 1 more interface has been had, but more information of debug.

In addition, referring to fig. 7, the BMC chip 61 and the first central processor 11 may be interconnected through an LPC bus, and the first central processor 11 may be configured to transmit an IPMI instruction, an 80port post code, a BMC register, system serial port information, and the like to the BMC chip 61. The BMC chip 61 and the first central processing unit 11 can be interconnected through a PICE X1 signal, so as to realize the function of system display. The BMC chip 61 and the first central processor 11 may be interconnected through a USB interface for implementing KVM function. The BMC chip 61 may also be enabled to read the temperature sensor 64 inside the first central processor 11 by I2C signaling interconnection between the BMC chip 61 and the first central processor 11. The GPIO interface of the BMC chip 61 may also be interconnected with the power interface of the first central processing unit 11 to directly control signals of the first central processing unit 11, such as power on/off and restart, so as to implement power on/off and restart control of the system.

With continued reference to fig. 7, a data selector 62 connected to the first central processing unit 11 through the SPI bus may be further provided on the motherboard 10, and the data selector 62 is an alternative data selector 62. The main board 10 is further provided with a BIOS chip 63, and the data selector 62 is connected to the BIOS chip 63 through the SPI bus. And the data selector 62 is also connected to the BMC chip 61 through the SPI bus. Therefore, whether the BIOS chip 63 is connected with the first central processor 11 or the BMC chip 61 can be selected through the remote control of the BMC chip 61. Specifically, the data selector 62 may select the flash interface of the BIOS chip 63 to connect to the first central processing unit 11 or connect to the BMC chip 61 under the control of the GPIO interface of the BMC chip 61. When the system normally operates, the BIOS chip 63 is connected to the first central processing unit 11; when the BIOS chip 63 is to be burned through the BMC chip 61, the BIOS chip 63 is connected to the BMC chip 61.

As shown in fig. 7, the motherboard 10 may be further provided with a temperature sensor 64 and a fan module interface connected to the BMC chip 61. So that the temperature of remote monitoring double-circuit server mainboard, the remote control fan module of being convenient for dispels the heat.

Through set up first PICE X16 slot 21 and second PICE X16 slot 22 on mainboard 10, still set up analog switch 20, the system judges whether there is the plug-in card in second PICE X16 slot 22 through GPIO, automatic PICE slot adjustment that will be connected with second central processing unit 12 is two PICE X8 slots or a PICE X16 slot, the flexibility of PICE slot on the improvement mainboard 10, the compatibility of improvement dual-path server mainboard.

In addition, the embodiment of the utility model provides a still provide a server, refer to fig. 1 and fig. 2, this server includes quick-witted case and sets up any one kind of above-mentioned double-circuit server mainboard at quick-witted incasement. Through set up first PICE X16 slot 21 and second PICE X16 slot 22 on mainboard 10, still set up analog switch 20, the system judges whether there is the plug-in card in second PICE X16 slot 22 through GPIO, automatic PICE slot adjustment that will be connected with second central processing unit 12 is two PICE X8 slots or a PICE X16 slot, the flexibility of PICE slot on the improvement mainboard 10, the compatibility of improvement dual-path server mainboard.

The above description is only for the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A two-way server motherboard, comprising:

a main board;

the first central processing unit and the second central processing unit are arranged on the mainboard, wherein the first central processing unit and the second central processing unit are interconnected through a X16 XGMI bus;

a first PICE X16 slot which is arranged on the mainboard and is in signal connection with the second central processing unit through an X8;

the analog switch is arranged on the mainboard and is in signal connection with the second central processing unit through an X8 signal, and the analog switch is also in signal connection with the first PICE X16 slot through an X8 signal;

the second PICE X16 slot is arranged on the mainboard and is connected with the analog switch through an X8 signal, and the second PICE X16 slot is connected with the GPIO interface of the first central processing unit through a card-in-place signal.

2. The two-way server motherboard of claim 1, wherein the motherboard further comprises a plurality of PICE X4 slots connected to the first cpu, and each PICE X4 slot is connected to the first cpu via an X1 signal;

the main board is also provided with a PICE X8 slot which is connected with the first central processing unit through an X4 signal.

3. The two-way server motherboard of claim 1, wherein the motherboard is further provided with at least one 7PIN SATA connector connected to the first central processing unit, wherein each 7PIN SATA connector is used for being plugged into a SATA disk;

the main board is also provided with a mini SAS HD connector connected with the first central processing unit.

4. The two-way server mainboard of claim 1, wherein an ALC4042H chip connected with the first central processing unit through a USB interface is disposed on the mainboard;

and the mainboard is also provided with an Audio Jack connected with the ALC4042H chip, and the Audio Jack is positioned at the rear end of the server case.

5. The two-way server main board according to claim 4, wherein the ALC274 chip connected to the ALC4042H chip is further connected to the main board, an Audioheader connected to the ALC274 chip is further disposed on the main board, and the Audioheader is connected to an Audio Jack at the front end of the server chassis.

6. The two-way server motherboard of claim 1, wherein the motherboard further comprises an I350 chip connected to the first cpu;

the mainboard is provided with at least one double-layer USB3.0+ RJ45 network cable connector, and the at least one double-layer USB3.0+ RJ45 network cable connector is positioned at the rear end of the server case;

and the RJ45 network cable interface in each double-layer USB3.0+ RJ45 network cable connector is connected with the I350 chip, and the USB3.0 interface in each double-layer USB3.0+ RJ45 network cable connector is connected with the second central processing unit.

7. The two-way server motherboard as recited in claim 6, wherein the motherboard further comprises a USB header including USB3.0&2.0, connected to the first cpu, and the USB header is connected to the USB connector at the front end of the server chassis.

8. The two-way server motherboard of claim 1, further comprising a BMC chip disposed thereon, wherein the first central processor and the BMC chip are interconnected via a UART Serial port, and are configured to implement Serial Over Lan communication between the first central processor and the BMC chip.

9. The two-way server motherboard of claim 8, wherein the motherboard is further provided with a data selector connected to the first central processing unit via an SPI bus, and a BIOS chip connected to the data selector via the SPI bus;

and the data selector is also connected with the BMC chip through an SPI bus.

10. A server, comprising:

a chassis;

the two-way server main board of any one of claims 1 to 9 arranged in the chassis.