CN212850496U

CN212850496U - Power line carrier communication device of circuit breaker detection system

Info

Publication number: CN212850496U
Application number: CN202022157236.XU
Authority: CN
Inventors: 罗光鸿; 许国龙; 罗啟俊; 何顺全
Original assignee: Yunnan Power Grid Co ltd Dehong Power Supply Bureau
Current assignee: Yunnan Power Grid Co ltd Dehong Power Supply Bureau
Priority date: 2020-09-27
Filing date: 2020-09-27
Publication date: 2021-03-30
Anticipated expiration: 2030-09-27

Abstract

The utility model relates to a circuit breaker detecting system's power cord carrier communication device. The utility model discloses be equipped with first PLC module, second PLC module respectively in centralized power supply system and circuit breaker detecting system, first PLC module includes first modem module, first coupling circuit, and the second PLC module includes second modem module, second coupling circuit; the first modulation and demodulation module is connected with the first coupling circuit, the first coupling circuit is connected with the direct-current 24V power supply bus, the second modulation and demodulation module is connected with the second coupling circuit, and the second coupling circuit is connected with the direct-current 24V power supply bus. The utility model provides a channel for information transmission while supplying electric energy to each breaker detection system; the information transmission is not carried out through a field bus, but is converted into a high-frequency signal through a carrier communication (PLC) module and then coupled to a power line, so that the power line can supply power and can realize information transmission.

Description

Power line carrier communication device of circuit breaker detection system

Technical Field

The utility model relates to a circuit breaker detecting system's power cord carrier communication device belongs to circuit breaker technical field.

Background

The rapid development of the smart power grid enables the traditional low-voltage distribution equipment to no longer meet all requirements of users, and the intelligent development of a low-voltage distribution system becomes a necessary trend. The electric appliance serving as an important node in the power grid has the basic characteristics of digitization, informatization, automation and interaction besides the traditional functions so as to adapt to the development requirements of the smart power grid. Along with the popularization of the intelligent concept of the power grid, the research on the intellectualization of the low-voltage circuit breaker in the power distribution network is concerned more and more.

As is well known, in the conventional intelligent low-voltage distribution system, the power supply of each circuit breaker detection system inside the system is a power bus, and the information transmission is a field bus. That is to say, the power bus and the field bus are operated separately and separated from each other. A simplified diagram of a conventional intelligent low-voltage power distribution system is shown in fig. 1, wherein a power bus supplies power to each breaker detection system, and a field bus provides a channel for information transmission; consider the demand of aspects such as circuit breaker detecting system communication to real-time, rapidity, the utility model discloses a carrier communication scheme based on RS485 link standard that uses FPGA data processing chip as the core has been proposed to the direct current channel characteristics. The whole hardware circuit is designed, comprises a coupling circuit, an RS485 carrier interface circuit and the like, and parameter selection of relevant elements such as a coupling transformer and the like is given. In order to solve the problems of direct current components and the like in carrier signals, a signal modulation mode is analyzed, and finally differential Manchester coding is adopted. A data processing chip FPGA is introduced, the model of the FPGA is selected, and a JTAG configuration mode and an EPCS4 are selected as configuration chips. And finally, designing auxiliary circuits such as a power supply circuit, an RS485 interface circuit and the like.

Disclosure of Invention

The to-be-solved technical problem of the utility model is: the utility model provides a circuit breaker detecting system's power cord carrier communication device for the power cord not only can supply power but also can realize the transmission of information.

The utility model adopts the technical scheme that: a power line carrier communication device of a circuit breaker detection system is characterized in that a first PLC module and a second PLC module are respectively arranged in a centralized power supply system and the circuit breaker detection system, the first PLC module comprises a first modulation and demodulation module and a first coupling circuit, and the second PLC module comprises a second modulation and demodulation module and a second coupling circuit; the first modulation and demodulation module is connected with the first coupling circuit, the first coupling circuit is connected with the direct-current 24V power supply bus, the second modulation and demodulation module is connected with the second coupling circuit, and the second coupling circuit is connected with the direct-current 24V power supply bus.

As a further aspect of the present invention, the first modem module includes a first FPGA data processing chip, a first RS485 carrier interface circuit, and a first voltage stabilizing module; the first FPGA data processing chip is connected with the first RS485 carrier interface circuit, the first RS485 carrier interface circuit is connected with the first coupling circuit, and the first voltage stabilizing module is used for converting the 24V voltage into 5V and 3.3V voltages which enable the first FPGA data processing chip and the first RS485 carrier interface circuit to work normally;

the second modulation and demodulation module comprises a second FPGA data processing chip, a second RS485 carrier interface circuit and a second voltage stabilizing module; the second FPGA data processing chip is connected with the second RS485 carrier interface circuit, the second RS485 carrier interface circuit is connected with the second coupling circuit, and the second voltage stabilizing module is used for converting the 24V voltage into 3.3V voltage for enabling the second FPGA data processing chip and the second RS485 carrier interface circuit to normally work.

As a further aspect of the present invention, the second modem module in the circuit breaker detection system is used for performing corresponding encoding processing on binary data to be transmitted, and converting the binary data into corresponding high-frequency signals, and the second coupling circuit is used for loading the high-frequency signals onto the dc 24V power bus;

the direct-current 24V power bus is used for transmitting the modulated high-frequency signal to a centralized power supply system;

the first coupling circuit in the centralized power supply system intercepts the modulated high-frequency signal and transmits the signal to the first modulation and demodulation module for decoding processing, and the information is restored into original information.

As a further aspect of the present invention, the first coupling circuit and the second coupling circuit adopt inductive coupling.

As a further scheme of the utility model, first voltage stabilizing module second voltage stabilizing module all adopts LM2576-5 chip to provide stable 5V voltage and adopts AMS1117-3.3SOT-223 chip to realize the conversion to 3.3V voltage.

As a further aspect of the present invention, the first RS485 carrier interface circuit and the second RS485 carrier interface circuit all adopt SN65HVD 78.

The utility model has the advantages that: the utility model provides a channel for information transmission while supplying electric energy to each breaker detection system; the information transmission is not performed through a field bus, but is converted into a high-frequency signal through a carrier communication (PLC) module and then coupled to a power line, so that the power line can supply power and realize information transmission, and the combination of a power bus and the field bus is completed.

Drawings

Fig. 1 is a simplified structural schematic diagram of a conventional intelligent low-voltage power distribution system of the present invention;

fig. 2 is a simplified schematic diagram of the structure of the present invention;

fig. 3 is a schematic diagram of the specific structure of the PLC module of the present invention;

FIG. 4 is a schematic diagram of the coupling circuit of the present invention;

FIG. 5 is a JTAG circuit diagram of the present invention;

FIG. 6 is a schematic circuit diagram of the FPGA configuration chip of the present invention;

FIG. 7 is a schematic diagram of the 5V voltage stabilizing circuit of the present invention;

FIG. 8 is a schematic diagram of the 3.3V voltage regulator circuit of the present invention;

fig. 9 is a schematic diagram of the RS485 carrier interface circuit of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.

Example 1: as shown in fig. 2, a first PLC module and a second PLC module are respectively disposed in the centralized power supply system and the circuit breaker detection system, the first PLC module includes a first modem module and a first coupling circuit, and the second PLC module includes a second modem module and a second coupling circuit; the first modulation and demodulation module is connected with the first coupling circuit, the first coupling circuit is connected with the direct-current 24V power supply bus, the second modulation and demodulation module is connected with the second coupling circuit, and the second coupling circuit is connected with the direct-current 24V power supply bus. The centralized power supply system comprises a power supply module and a first PLC module;

as shown in fig. 3, as a further aspect of the present invention, the first modem module includes a first FPGA data processing chip, a first RS485 carrier interface circuit, and a first voltage stabilizing module; the first FPGA data processing chip is connected with the first RS485 carrier interface circuit, the first RS485 carrier interface circuit is connected with the first coupling circuit, and the first voltage stabilizing module is used for converting the 24V voltage into 5V and 3.3V voltages which enable the first FPGA data processing chip and the first RS485 carrier interface circuit to work normally;

the second modulation and demodulation module comprises a second FPGA data processing chip, a second RS485 carrier interface circuit and a second voltage stabilizing module; the second FPGA data processing chip is connected with the second RS485 carrier interface circuit, the second RS485 carrier interface circuit is connected with the second coupling circuit, and the second voltage stabilizing module is used for converting the 24V voltage into 3.3V voltage for enabling the second FPGA data processing chip and the second RS485 carrier interface circuit to normally work. The specific structures of the PLC modules in the centralized power supply system and the circuit breaker detection systems are the same. The FPGA data processing chip and the RS485 carrier interface circuit part are equivalent to a modulation and demodulation part in the figure 2, the FPGA data processing chip modulates and demodulates information, and the RS485 carrier interface converts an original signal into a differential signal and sends the differential signal into a following coupling circuit. The voltage stabilizing module converts the 24V voltage into 3.3V voltage for the FPGA, RS485 and other chips to work normally.

the utility model adopts differential Manchester coding to modulate the original data information; the differential man code not only contains data but also contains a clock synchronization signal when being transmitted. And, the differential man code is continuously hopped by '01' or '10', which means that the differential signal converted by the RS485 is also continuously alternated. The frequency of the differential signal is increased, so that no direct current component exists, and the influence of interference on communication is small.

In general, differential Manchester encoding can enable the transmitted differential signal to have no direct current component, and solves the problem that only one byte can be transmitted by RS485 at a time.

As a further aspect of the present invention, in order to realize the carrier communication function of the power line in the dc environment, the wave-blocking inductor and the coupling circuit are added between the signal receiving/transmitting ends and the power transmission line to pass through the low-frequency-resistance high-frequency signal. The function of the coupling circuit is to carry a signal to a power line, the process can be realized by an inductor or a capacitor, and the first coupling circuit and the second coupling circuit adopt inductive coupling.

Inductive coupling is also referred to as transformer coupling. The transformer is a power transformer applied to the field of power systems, and is a communication transformer applied to the field of communication. The working principle of the communication transformer is as follows: the signal to be transmitted is connected to the primary side of the transformer as the primary winding. The power line is connected with the secondary side of the transformer and is used as a secondary coil. The primary and secondary coils are wound around a magnetic core, and the magnetic permeability of the magnetic core is not low. Both the transmission and reception devices for high-frequency signals can be regarded as current sources, and signals are carried to a power line through a communication transformer by the principle of electromagnetic induction during transmission, which corresponds to the transmission of signals from the primary side to the secondary side of the communication transformer. The signal is then transmitted through a transmission medium, such as a power line. Finally, when the signal is received, the signal is intercepted from the power line by utilizing the electromagnetic induction principle, namely, the signal returns to the primary side from the secondary side of the communication transformer; the circuit schematic of the coupling circuit is shown in fig. 4;

in fig. 4, four inductors on the left and right sides of the power line are choke inductors, and the choke inductors are formed by winding coils on an iron core with an air gap. The inductor is characterized by direct current and alternating current, so that the inductor can also be regarded as a high-frequency wave trap which plays an important role in a carrier communication system. The specific function is to allow the direct current in the power transmission line to pass through, block the path of high-frequency signals and prevent the high-frequency signals from entering places except communication nodes. The transmission rate of the information is 10Mbps, and the size of the final wave-blocking inductor is 0.lmH in view of effectively filtering out high-frequency components.

Two capacitors in the left coupling circuit and the right coupling circuit are blocking capacitors, and the two capacitors have the functions of filtering signals, reducing the influence of low-frequency direct current such as power supply ripples on communication nodes, reducing the attenuation of the signals to a certain extent and improving the communication quality. For the choice of the blocking capacitance, reference is made herein to the more sophisticated telephone lines of the prior art, which are generally selected to have a capacitance higher than luF and to withstand a voltage higher than 63V. However, the application environment of the telephone line is 48V, while the direct current environment of the carrier communication is 24V, compared with the former, the voltage of the carrier communication is higher, and the value of the final tantalum capacitor is 0.47 muf.

The FPGA model selected was EP4C6E22C8, which is manufactured by Altera. The reason for choosing such a chip is as follows: the number of phase-locked loops is 2, each PLL can divide and multiply the frequency of the clock, and five processed clocks can be output simultaneously for one clock. The specific implementation mode is that the clock management module is automatically generated by the IP core generator, relevant parameters are set according to requirements, and the use is simple and uncomplicated. The FPGA has all the advantages of the FPGA, nearly 6300 logic units and 0.27Mbits of storage space are contained in the FPGA, and all the requirements of the FPGA on the performance of a chip are met;

the configuration form of the FPGA can be divided into an active form, a passive form and a JTAG form. The AS and the PS store the relevant configuration information on the FLASH chip, and transmit the information to the FPGA after the power supply is switched on, thereby completing the configuration of the FPGA. JTAG is different from the first two more indirect ways, which is to be able to add configuration information directly to the FPGA running online. Fast under this mode, be favorable to online debugging, the utility model relates to an it is the third kind JTAG mode that the configuration interface adopted.

JTAG is a standard test protocol commonly used in the world, and is often applied to the detection of the working performance of a chip. JTAG typically has ten interfaces, two of which are not used. Except for power VCC and ground GND ports, the remaining five interfaces are TCK, TDO, TMS, TDI, and TRST in sequence, and the last one is usually floating. The special download line of FPGA is used to connect it with computer, and the software program capable of implementing correspondent function is downloaded into FPGA, then the operation and debugging can be implemented. The schematic diagram of the circuit is shown in fig. 5;

the FLASH chip adopts EPCS4 capable of realizing 4M speed, and can complete 50M read-write operation under SPI serial communication. The chip and JTAG are not connected together from a position on the board. Therefore, the connection between them requires the FPGA as a hub. Namely, configuration files are downloaded into the FPGA from the computer and then transmitted to the EPCS4, and FIG. 6 is a schematic circuit diagram of the configuration chip;

The trip coil of the circuit breaker detection system is supplied with 24V direct current by a centralized power supply system, and various chips in the circuit need 5V and 3.3V working voltage. Therefore, 5V and 3.3V voltage stabilizing chips are required in the PLC module to convert the voltage. The LM2576-5 chip is adopted in the design to provide stable 5V voltage, the size interval of the input voltage value is wider, and a specific circuit schematic diagram is shown in FIG. 7; considering the safety of the chip during operation, the Vin pin side is connected with a capacitor, and the type is usually selected from electrolytic or clamp capacitors. The SO pin side inductor is capable of storing electrical energy with a value selected to be 330 uH. Considering that the switching frequency of the chip is high, the diode on the SO pin side also meets certain requirements on switching and recovery speed, and finally the Schottky diode is adopted. The capacitor type of the output side is the same as that of the input side, and certain benefits are provided for filtering and voltage stabilization;

the AMS1117-3.3SOT-223 chip is adopted in the design to realize the conversion of 3.3V voltage, and the output precision can reach 1%. Moreover, the self-protection device can perform self-protection when the temperature is too high, and can limit the current. A specific circuit schematic diagram is shown in fig. 8; the chip can output fixed and unchangeable voltage and adjustable voltage, and the design is to output fixed 3.3V voltage. The function of the Vin pin side access capacitor is filtering, and the type is usually selected as clamp capacitor. The pin side of the Vout is also connected with a capacitor, which has certain benefit on the stability of the output voltage;

as a further aspect of the present invention, the first RS485 carrier interface circuit and the second RS485 carrier interface circuit all adopt SN65HVD 78. A level conversion is needed between the FPGA and the coupling circuit of the data processing chip, and the function of the level conversion is completed by an RS485 carrier interface circuit. The RS485 carrier interface circuit adopts SN65HVD78 produced by TI manufacturers, the functions of the chip of the type accord with the requirements of circuit design, the conversion between level signals and differential signals can be completed, and the functions of each pin are shown in Table 1;

TABLE 1 SN65HVD78 Pin introduction

The utility model discloses RS485 interface circuit accomplishes differential signal's conversion when sending, on loading the power cord with differential signal through coupling circuit after that. And when receiving, the differential signal on the coupling circuit is intercepted and converted into the original level signal for the subsequent FPGA chip to process. That is, the interface circuit is required to be capable of transmitting and receiving signals in addition to converting signals. Therefore, the receiving and transmitting control terminals of the RS485 chip cannot be all at high level or all at low level. The RE and DE pin connection method meeting the requirements comprises three types: the RE and DE pins are controlled by different pins of the FPGA, the RE and DE pins are controlled by the same pin of the FPGA, and the RE pin is grounded (i.e., always low) while the DE pin is controlled by the FPGA pin.

The utility model discloses the RS485 chip is always receiving data, does so and to make communication system have fine reliability. When transmitting data, when transmitting a bit of data to the rear coupling circuit, the R pin is used to read back the bit of data, and the two are compared. If the result is the same, it is indicated that the transmission is correct, and the next bit of data is transmitted. If the result is different, the next bit of data is not sent any more, and a signal is sent to the receiving end to enable everybody to enter a timeout state. A schematic diagram of an RS485 carrier interface circuit is shown in fig. 9.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the term "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of additional like elements in the article or device comprising the element.

The above embodiments are merely for illustrating the technical solutions of the present invention and are not to be construed as limiting, and the present invention is described in detail with reference to the preferred embodiments. It should be understood by those skilled in the art that various modifications and equivalent substitutions may be made to the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention, and all the modifications and equivalents should be covered by the scope of the claims of the present invention.

Claims

1. The utility model provides a power cord carrier communication device of circuit breaker detecting system which characterized in that: a first PLC module and a second PLC module are respectively arranged in the centralized power supply system and the circuit breaker detection system, the first PLC module comprises a first modulation and demodulation module and a first coupling circuit, and the second PLC module comprises a second modulation and demodulation module and a second coupling circuit; the first modulation and demodulation module is connected with the first coupling circuit, the first coupling circuit is connected with the direct-current 24V power supply bus, the second modulation and demodulation module is connected with the second coupling circuit, and the second coupling circuit is connected with the direct-current 24V power supply bus.

2. The power line carrier communication device of circuit breaker detection system of claim 1, wherein: the first modulation and demodulation module comprises a first FPGA data processing chip, a first RS485 carrier interface circuit and a first voltage stabilizing module; the first FPGA data processing chip is connected with the first RS485 carrier interface circuit, the first RS485 carrier interface circuit is connected with the first coupling circuit, and the first voltage stabilizing module is used for converting the 24V voltage into 5V and 3.3V voltages which enable the first FPGA data processing chip and the first RS485 carrier interface circuit to work normally;

3. The power line carrier communication device of circuit breaker detection system of claim 1, wherein: the second modulation and demodulation module in the circuit breaker detection system is used for carrying out corresponding coding processing on binary data to be sent and converting the binary data into corresponding high-frequency signals, and the second coupling circuit is used for loading the high-frequency signals onto a direct-current 24V power bus;

4. The power line carrier communication device of circuit breaker detection system of claim 1, wherein: the first coupling circuit and the second coupling circuit are inductively coupled.

5. The power line carrier communication device of the circuit breaker detection system of claim 2, wherein: the first voltage stabilizing module and the second voltage stabilizing module both adopt an LM2576-5 chip to provide stable 5V voltage and adopt an AMS1117-3.3SOT-223 chip to realize the conversion of 3.3V voltage.

6. The power line carrier communication device of the circuit breaker detection system of claim 2, wherein: and the first RS485 carrier interface circuit and the second RS485 carrier interface circuit both adopt SN65HVD 78.