CN212588311U - Configurable low-frequency high-pass filter - Google Patents

Abstract

The utility model discloses a can dispose low frequency high pass filter, include: the device comprises a coupling capacitor circuit, a first chopping switch circuit, an operational amplifier circuit, a second chopping switch circuit, a filter circuit, a first direct current feedback circuit, a second direct current feedback circuit, a first feedback capacitor array circuit and a second feedback capacitor array circuit; the utility model discloses can effectively eliminate the direct current offset voltage of electrode and not arouse target signal's distortion to can suppress motion artifact to a certain extent, have configurable high pass cut-off frequency, adjustable magnification and lower circuit noise simultaneously, and then promote whole signal acquisition system integrated level and precision.

Description

Configurable low-frequency high-pass filter

Technical Field

The utility model relates to a sensing technology and integrated circuit technical field especially relate to a can dispose low frequency high pass filter.

Background

In recent years, the rapid development of sensing technology creates favorable conditions for human attention to self physiological signals. The accurate collection of physiological signals such as electrocardio, electroencephalogram, myoelectricity, blood pressure and the like ensures that the research and diagnosis of medical science have effective information support and promotes the development of modern medical science. In addition, the acquisition and analysis of the electroencephalogram signals can realize a series of brain control systems and products, and the brain control system and the brain control products are widely applied to the fields of military affairs, astronavigation, industry, entertainment and the like.

The physiological signals such as electrocardio, electroencephalogram, myoelectricity and the like belong to weak bioelectricity signals essentially, the amplitude of the signals is generally between dozens of uV and several mV, and the range of frequencies from several thousands of Hz to several thousands of Hz is covered. Generally, the bioelectric signal is detected by connecting two electrode probes to two different contact points of a human body, and a voltage signal difference between the two electrodes is obtained for processing and analysis. However, due to the electrochemical effect of the electrodes, the electrodes themselves introduce a dc offset voltage of up to several hundred mV, which is sufficient to cover the effective signal collected. Meanwhile, as the acquisition object is in a micro-motion process, such as contraction movement of respiration or movement of the body, the signal baseline of the acquisition circuit often has larger drift due to motion artifacts generated by the human body, and the signal acquisition channel amplifying circuit is possibly saturated and distorted due to serious electrode offset voltage and motion artifacts. Therefore, in the process of amplifying the bioelectric signals, the offset voltage introduced by the electrodes needs to be eliminated through high-pass filtering, the influence caused by motion artifacts needs to be suppressed as much as possible, and meanwhile, the signal-to-noise ratio of signal sensing acquisition is improved by a certain amplification capacity. In the case of high-pass filtering processing, which is often required to achieve a very low cut-off frequency, it is required to retain the low-frequency components of the bioelectric signal.

The frequency components of interest tend to be different from bioelectric signals. The filtering frequency can be configured to meet different application requirements. In addition, the amplitude of the bioelectrical signal has a great correlation with the type of the electrode and the acquisition environment, so that the amplification factor is required to be flexibly adjusted.

SUMMERY OF THE UTILITY MODEL

The to-be-solved technical problem of the present invention is to provide a configurable low frequency high pass filter to the defects of the prior art.

The utility model provides a technical scheme that its technical problem adopted is: constructing a configurable low frequency high pass filter comprising: a coupling capacitor circuit, a first chopping switch circuit, an operational amplifier circuit, a second chopping switch circuit, a filter circuit, a first direct current feedback circuit, a second direct current feedback circuit, a first feedback capacitor array circuit and a second feedback capacitor array circuit, wherein,

the input end of the coupling capacitor circuit is respectively connected with the positive electrode VINP of the probe and the negative electrode VINN of the probe; a first output end and a second output end of the coupling capacitor circuit are respectively connected with a first input end and a second input end of the first chopping change-over switch circuit; a first output end and a second output end of the first chopping change-over switch circuit are respectively connected with a positive phase input end and a negative phase input end of the operational amplifier circuit, and the negative phase output end and the positive phase output end of the operational amplifier circuit are respectively connected with a first input end and a second input end of the second chopping change-over switch circuit; a first output end and a second output end of the second chopping change-over switch circuit are respectively connected with a first input end and a second input end of the filter circuit; a first output end of the filter circuit is used as a negative output end VOUTN of the configurable low-frequency high-pass filter, and a second output end of the filter circuit is used as a positive output end VOUTP of the configurable low-frequency high-pass filter;

after the first direct current feedback circuit and the first feedback capacitor array circuit are connected in parallel, one parallel end of the first direct current feedback circuit is connected to a connection node A of the first output end of the coupling capacitor circuit and the first input end of the first chopping change-over switch circuit, and the other parallel end of the first direct current feedback circuit is connected to a connection node C of the first output end of the second chopping change-over switch circuit and the first input end of the filter circuit;

after the second direct-current feedback circuit and the second feedback capacitor array circuit are connected in parallel, one parallel end of the second direct-current feedback circuit is connected to a connection node B of the second output end of the coupling capacitor circuit and the second input end of the first chopping change-over switch circuit, and the other parallel end of the second direct-current feedback circuit is connected to a connection node D of the second output end of the second chopping change-over switch circuit and the second input end of the filter circuit;

the coupling capacitor circuit is used for isolating the direct-current voltage input by the probe; the first chopping switching circuit and the second chopping switching circuit modulate direct-current offset voltage and component noise caused by component mismatching in the configurable low-frequency high-pass filter out of a preset frequency band by periodically switching two-phase states; the first feedback capacitor array circuit and the second feedback capacitor array circuit provide feedback paths for alternating current signals; the first direct current feedback circuit and the second direct current feedback circuit provide feedback paths for direct current signals; the filter circuit is used for filtering out the direct current offset voltage and the component noise which are modulated to be out of the preset frequency band.

Preferably, the first dc feedback circuit includes: a first PMOS transistor M1, a second PMOS transistor M2, a first bias source U1 and a second bias source U2; the second direct current feedback circuit includes: a third PMOS transistor M3, a fourth PMOS transistor M4, a third bias source U3, and a fourth bias source U4;

the source of the first PMOS transistor M1 is connected to the connection node a, the drain of the first PMOS transistor M1 is connected to the drain of the second PMOS transistor M2, the gate of the first PMOS transistor M1 is connected to the source of the second PMOS transistor M1 via the first bias source U1, the gate of the second PMOS transistor M2 is connected to the output common-mode reference voltage VCM via the second bias source U2, and the source of the second PMOS transistor M2 is connected to the connection node C;

the source of the third PMOS transistor M3 is connected to the connection node B, the drain of the third PMOS transistor M3 is connected to the drain of the fourth PMOS transistor M4, the gate of the third PMOS transistor M3 is connected to the source of the fourth PMOS transistor M3 via the third bias source U3, the gate of the fourth PMOS transistor M4 is connected to the output common-mode reference voltage VCM via the fourth bias source U4, and the source of the fourth PMOS transistor M4 is connected to the connection node D;

by adjusting the bias voltage values output by the first bias voltage source U1, the second bias voltage source U2, the third bias voltage source U3 and the fourth bias voltage source U4, the first PMOS transistor M1, the second PMOS transistor M2, the third PMOS transistor M3 and the fourth PMOS transistor M4 work in weak inversion states of different degrees to obtain different large resistance values.

Preferably, the first bias source U1, the second bias source U2, the third bias source U3 and the fourth bias source U4 are all the same bias sources, and the internal circuit of the bias sources includes: a fifth PMOS tube M5, an NMOS tube array Mx1-Mxn and an NMOS tube array driving circuit;

the NMOS tube array Mx1-Mxn is formed by connecting a plurality of NMOS tubes in parallel, the drain electrode of the fifth PMOS tube M5 is connected with the drain electrode parallel node of the NMOS tube array Mx1-Mxn, the grid electrode and the drain electrode of the fifth PMOS tube M5 are in short circuit, and the source electrode parallel node of the NMOS tube array Mx1-Mxn is grounded GND;

the NMOS tube array driving circuit comprises a plurality of sub-driving circuits, and each sub-driving circuit comprises: NMOS tube Ms1, NMOS tube Mr1, NMOS tube Mn1 and PMOS tube Mp 1; the drain of the NMOS tube Ms1 is connected to a voltage input terminal Vbias, the source of the NMOS tube Ms1 is connected to the drain of the NMOS tube Mr1, the source of the PMOS tube Mp1 is connected to VDD, the drain of the PMOS tube Mp1 is connected to the drain of the NMOS tube Mn1, the source of the NMOS tube Mn1 is grounded, the gate of the NMOS tube Mr1 is connected to the connection point of the drain of the PMOS tube Mp1 and the drain of the NMOS tube Mn1, the gates of the NMOS tube Ms1, the PMOS tube Mp1 and the NMOS tube Mn1 are connected to a selection signal input terminal Sel1, the connection point of the source of the NMOS tube Ms1 and the drain of the NMOS tube Mr1 is a driving signal output terminal Vb1 of the sub-driving circuit, and the driving signal output terminals Vb1-Vbn of the sub-driving circuit are correspondingly connected to the gates of the NMOS tube array Mx1-Mxn, respectively;

the current value flowing through the fifth PMOS transistor M5 is adjusted through the selection signal input ends of a plurality of sub driving circuits to generate different bias voltage values.

Preferably, the first chopping switch circuit comprises an NMOS transistor Mns1, an NMOS transistor Mns2, an NMOS transistor Mns3, an NMOS transistor Mns 4;

the second chopping switch circuit comprises an NMOS tube Mns5, an NMOS tube Mns6, an NMOS tube Mns7 and an NMOS tube Mns 8;

the drain of the NMOS transistor Mns1 is connected to the drain of the NMOS transistor Mns2 and then to the connection node a, the source of the NMOS transistor Mns1 is connected to the negative-phase input terminal of the operational amplifier circuit, and the source of the NMOS transistor Mns2 is connected to the positive-phase input terminal of the operational amplifier circuit; the drain of the NMOS transistor Mns3 is connected to the drain of the NMOS transistor Mns4 and then to the connection node B, the source of the NMOS transistor Mns3 is connected to the negative-phase input terminal of the operational amplifier circuit, and the source of the NMOS transistor Mns4 is connected to the positive-phase input terminal of the operational amplifier circuit;

the drain of the NMOS transistor Mns5 is connected to the drain of the NMOS transistor Mns6 and then to the connection node C, the source of the NMOS transistor Mns5 is connected to the positive phase output terminal of the operational amplifier circuit, and the source of the NMOS transistor Mns6 is connected to the negative phase output terminal of the operational amplifier circuit; the drain of the NMOS transistor Mns7 is connected to the drain of the NMOS transistor Mns8 and then to the connection node D, the source of the NMOS transistor Mns7 is connected to the positive phase output terminal of the operational amplifier circuit, and the source of the NMOS transistor Mns8 is connected to the negative phase output terminal of the operational amplifier circuit;

the on-off of the NMOS transistor Mns2, the NMOS transistor Mns3, the NMOS transistor Mns6 and the NMOS transistor Mns7 is controlled by a first driving control signal S1 applied to the gate, the on-off of the NMOS transistor Mns1, the NMOS transistor Mns4, the NMOS transistor Mns5 and the NMOS transistor Mns8 is controlled by a second driving control signal S2 applied to the gate, and the first driving control signal S1 and the second driving control signal S2 are opposite-phase signals.

Preferably, the coupling capacitance circuit comprises a first capacitance C1 and a second capacitance C2;

the first capacitor C1 is connected between the positive electrode VINP of the probe and the connection node A, the second capacitor C2 is connected between the negative electrode VINN of the probe and the connection node B, and the resistance values of the first capacitor C1 and the second capacitor C2 are equal.

Preferably, the first feedback capacitor array circuit comprises a plurality of feedback capacitor sub-circuits, each feedback capacitor sub-circuit comprises a capacitor C3 and two identical MOS switch tubes, one end of the capacitor C3 is connected to the connection node a through one of the MOS switch tubes, the other end of the capacitor C3 is connected to the connection node C through the other MOS switch tube, and the plurality of feedback capacitor sub-circuits are connected in parallel;

the second feedback capacitor array circuit comprises a plurality of feedback capacitor sub-circuits, each feedback capacitor sub-circuit comprises a capacitor C4 and two identical MOS (metal oxide semiconductor) switching tubes, one end of the capacitor C4 is connected with the connection node B through one MOS switching tube, the other end of the capacitor C3 is connected with the connection node D through the other MOS switching tube, and the feedback capacitor sub-circuits of the second feedback capacitor array circuit are connected in parallel; the total capacitance values of the first feedback capacitor array circuit and the second feedback capacitor array circuit are equal;

and the total capacitance value of the first feedback capacitor array circuit and the second feedback capacitor array circuit accessed to the configurable low-frequency high-pass filter is adjusted by controlling the on-off of an MOS (metal oxide semiconductor) switching tube of the feedback capacitor sub-circuit, so that the amplification factor of the configurable low-frequency high-pass filter is adjusted.

Preferably, the operational amplifier circuit comprises an amplifier body circuit and a common mode feedback loop; the amplifier main body circuit comprises PMOS tubes PM1, PM2, PM3, PM5, PM6, PM7, PM8 and NMOS tubes NM1, NM2, MN3 and NM 4;

the source of the PMOS transistor PM1, PM2, PM3 is connected to the power supply input terminal VDD, the gate of the PMOS transistor PM1 is connected to the first bias signal VP1, the gate of the PMOS transistor PM2 is connected to the gate of the PMOS transistor PM3 and to the first bias signal VP1, the drain of the PMOS transistor PM2 is connected to the source of the PMOS transistor PM5, the drain of the PMOS transistor PM3 is connected to the source of the PMOS transistor PM6, the gate of the PMOS transistor PM5 is connected to the gate of the PMOS transistor PM6 and to the second bias signal VP2, the source of the PMOS transistor PM7 is connected to the source of the PMOS transistor PM8 and to the drain of the PMOS transistor PM1, the gate of the PMOS transistor PM7 is the positive phase input terminal VIP of the operational amplifier circuit, and the gate VIN of the PMOS transistor PM8 is the negative phase input terminal of the operational amplifier circuit;

the drain of the NMOS transistor NM1 is connected to the drain of the PMOS transistor PM5 and serves as the negative phase output terminal VON of the operational amplifier circuit, the drain of the NMOS transistor NM2 is connected to the drain of the PMOS transistor PM6 and serves as the positive phase output terminal VOP of the operational amplifier circuit, the source of the NMOS transistor NM1 is connected to the drain of the NMOS transistor NM3 and to the drain of the PMOS transistor PM7, the source of the NMOS transistor NM2 is connected to the drain of the NMOS transistor NM4 and to the drain of the PMOS transistor PM8, the gate of the NMOS transistor NM1 is connected to the gate of the NMOS transistor NM2 and to the third bias signal VN2, the source of the NMOS transistor NM3 is connected to the source of the NMOS transistor NM4 and to GND, and the gate of the NMOS transistor NM3 is connected to the gate of the NMOS transistor NM4 and to the fourth bias signal VN 1;

the common-mode feedback loop comprises PMOS tubes PM4, PM9 and PM10, NMOS tubes NM5 and NM6 and two resistors R3 and R4 with equal resistance values;

a source of the PMOS transistor PM4 is connected to a power supply input terminal VDD, a gate of the PMOS transistor PM4 is connected to a first bias signal VP1, a source of the PMOS transistor PM9 is connected to a source of the PMOS transistor PM10 and to a drain of the PMOS transistor PM4, a gate of the PMOS transistor PM9 is connected to an input reference voltage VCM, a drain of the PMOS transistor PM9 is connected to a drain of the NMOS transistor NM5 and to a connection point of the gate of the NMOS transistor NM3 and the gate of the NMOS transistor NM4, a drain of the PMOS transistor PM10 is connected to the drain of the NMOS transistor NM6, a gate of the NMOS transistor NM5 is connected to the gate of the NMOS transistor NM6 and to the drain of the NMOS transistor NM6, and a source of the NMOS transistor NM5 is connected to the source of the NMOS transistor NM6 and to ground GND;

a first end of the resistor R3 is connected to the positive phase output terminal VOP of the operational amplifier circuit, a first end of the resistor R4 is connected to the negative phase output terminal VON of the operational amplifier circuit, and a second end of the resistor R3 is connected to a second end of the resistor R4 and to the gate of the PMOS transistor PM 10.

Further, the configurable low-frequency high-pass filter of the present invention further comprises: a first fast setup switching circuit and a second fast setup switching circuit;

one end of the first fast establishing switch circuit is connected to the connection node A, and the other end of the first fast establishing switch circuit is connected to the connection node C; one end of the second fast-establishing switch circuit is connected to the connection node B, and the other end of the second fast-establishing switch circuit is connected to the connection node D; the first fast-establishment switching circuit and the second fast-establishment switching circuit are used for improving the response speed of the configurable low-frequency high-pass filter in the process of connecting and disconnecting the probe.

Preferably, the first fast establishing switch circuit and the second fast establishing switch circuit are both MOS transistor switch circuits; the MOS tube is controlled by a control signal S0 applied to a grid electrode, when the control signal S0 is at a high level, the MOS tube switch circuit is switched on, and when the control signal S0 is at a low level, the MOS tube switch circuit is switched off.

Preferably, the filter circuit comprises a first resistor R1, a second resistor R2, a fifth capacitor C5;

a first end of the first resistor R1 is connected to the connection node C, a second end of the first resistor R1 serves as a negative output terminal VOUTN of the configurable low-frequency high-pass filter, a first end of the second resistor R2 is connected to the connection node D, a second end of the second resistor serves as a positive output terminal VOUTP of the configurable low-frequency high-pass filter, and the fifth capacitor C5 is connected between the second end of the first resistor R1 and the second end of the second resistor R2.

Implement the technical scheme of the utility model, following beneficial effect has: the signal-to-noise ratio and the anti-interference capability of weak electric signal acquisition can be effectively enhanced, and the problems of target signal distortion and failure caused by direct current maladjustment and motion artifact of the electrode are avoided. The utility model discloses the scheme has configurable high pass cut-off frequency, adjustable magnification and lower circuit noise simultaneously, and then promotes whole signal acquisition system integrated level and precision. The utility model discloses a structure is put to single fortune, and small low power dissipation does not need outside discrete passive device, can integrate and realize under standard CMOS technology.

Drawings

The invention will be further explained with reference to the drawings and examples, wherein:

fig. 1 is a schematic structural diagram of an embodiment of the configurable low-frequency high-pass filter of the present invention;

fig. 2 is a schematic structural diagram of another embodiment of the configurable low-frequency high-pass filter of the present invention;

fig. 3 is a schematic circuit diagram of an embodiment of the configurable low frequency high pass filter of the present invention;

fig. 4 is a schematic circuit diagram of the internal circuit of the bias source in the configurable low frequency high pass filter of the present invention;

fig. 5 is a timing diagram of the control signal S0, the first driving control signal S1, and the second driving control signal S2 in the configurable low-frequency high-pass filter of the present invention;

fig. 6 is a schematic circuit diagram of an operational amplifier circuit in a configurable low frequency high pass filter according to the present invention.

Detailed Description

In order to clearly understand the technical features, objects, and effects of the present invention, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of an embodiment of the configurable low-frequency high-pass filter of the present invention;

as shown in fig. 1, the configurable low-frequency high-pass filter of the present invention comprises: a coupling capacitor circuit 10, a first chopping switch circuit 20, an operational amplifier circuit 30, a second chopping switch circuit 40, a filter circuit 50, a first DC feedback circuit 60, a second DC feedback circuit 70, a first feedback capacitor array circuit 80, a second feedback capacitor array circuit 90, wherein,

the input end of the coupling capacitor circuit 10 is respectively connected with the positive electrode VINP of the probe and the negative electrode VINN of the probe; a first output end and a second output end of the coupling capacitor circuit 10 are respectively connected with a first input end and a second input end of the first chopping switch circuit 20; a first output terminal and a second output terminal of the first chopping switch circuit 20 are connected to a positive phase input terminal and a negative phase input terminal of the operational amplifier circuit 30, respectively, and a negative phase output terminal and a positive phase output terminal of the operational amplifier circuit 30 are connected to a first input terminal and a second input terminal of the second chopping switch circuit 40, respectively; a first output terminal and a second output terminal of the second chopping switch circuit 40 are respectively connected with a first input terminal and a second input terminal of the filter circuit 50; a first output end of the filter circuit 50 is used as a negative output end VOUTN of the configurable low-frequency high-pass filter, and a second output end of the filter circuit 50 is used as a positive output end VOUTP of the configurable low-frequency high-pass filter;

after the first dc feedback circuit 60 and the first feedback capacitor array circuit 80 are connected in parallel, one parallel end is connected to a connection node a between the first output end of the coupling capacitor circuit 10 and the first input end of the first chopping changeover switch circuit 20, and the other parallel end is connected to a connection node C between the first output end of the second chopping changeover switch circuit 40 and the first input end of the filter circuit 50;

after the second dc feedback circuit 70 and the second feedback capacitor array circuit 90 are connected in parallel, one parallel end of the second dc feedback circuit is connected to the connection node B between the second output end of the coupling capacitor circuit 10 and the second input end of the first chopping switch circuit 20, and the other parallel end of the second dc feedback circuit is connected to the connection node D between the second output end of the second chopping switch circuit 40 and the second input end of the filter circuit 50;

the coupling capacitor circuit 10 is used for isolating direct-current voltage input by the probe; the first chopping switching circuit 20 and the second chopping switching circuit 40 modulate the direct-current offset voltage and the component noise of the operational amplifier circuit 30 to be out of the preset frequency band by periodically switching two-phase states; the first feedback capacitor array circuit 80 and the second feedback capacitor array circuit 90 provide feedback paths for the ac signals; the first dc feedback circuit 60 and the second dc feedback circuit provide feedback paths for the dc signals; the filter circuit 50 is used for filtering out dc offset voltage and component noise modulated outside a preset frequency band.

The working principle of the configurable low-frequency high-pass filter is as follows: two positive and negative electrode probes for acquiring bioelectricity signals are respectively connected to positive and negative input ends of the circuit, positive and negative weak bioelectricity signals input from the electrodes are respectively subjected to feedback amplification through the first direct current feedback circuit 60, the first feedback capacitor array circuit 80 and the operational amplifier circuit 30, then high-pass filtering with low cut-off frequency is respectively realized through the second direct current feedback circuit 70 and the second feedback capacitor array circuit 90, meanwhile, the noise of circuit components and offset voltage caused by component mismatch are modulated out of a preset frequency band by the first chopping switch circuit 20 and the second chopping switch circuit 40, finally, the direct current offset voltage and the component noise which are modulated out of the preset frequency band are filtered out by the filter circuit 50, and finally, accurate weak bioelectricity signals are acquired.

The advantages of the technical solution of the present invention are illustrated by comparing with several existing weak bioelectric signal acquisition schemes:

the first scheme is as follows: and a low-frequency high-pass filter circuit is realized by adopting discrete components in an analog filtering mode. In some integrated bioelectric amplifiers, an external large capacitor or large resistor is generally used at the input end to meet the requirement of high-pass filtering, so as to filter the electrode offset voltage and suppress motion artifacts.

The second scheme is as follows: a MOS feedback resistor connected with a diode is adopted in a feedback loop of the operational amplifier to form large equivalent impedance, so that a low-frequency high-pass filter circuit is realized.

In the third scheme: the analog front end selects low amplification factor to prevent the electrode maladjustment from causing signal amplification and then saturation distortion, and then the ADC with ultrahigh resolution ensures the conversion precision of a large dynamic range, thereby ensuring the data precision of subsequent digital processing.

A fourth scheme: and eliminating electrode offset voltage and inhibiting motion artifact by a digital filtering mode.

The four weak bioelectric signal acquisition schemes have the following defects:

in the first solution, since the frequency components of interest of the bioelectric signal are often as low as several thousandths of Hz, it is necessary to filter the dc offset and motion artifacts of the electrodes while preserving the effective signal, which requires the cut-off frequency of the high-pass filter to be lower than several thousandths of Hz. A high-pass filter with such a low cut-off frequency requires a capacitor with a large capacitance value or a resistor with a large resistance value. This is not conducive to full integration of the solution, usually requiring external capacitors or resistors. Under the condition of multi-channel acquisition, a high-pass filter cannot be multiplexed, and one channel needs an independent high-pass filter, so that a large number of capacitors or resistors need to be externally hung, and the cost and the volume of the scheme are inconvenient to control.

In the second scheme described above, diode-connected MOS feedback resistors are used in the feedback loop, although chip integration and low cut-off frequency are easily achieved. But the biggest disadvantage is that the voltage fluctuation at two ends of the MOS feedback resistor is large, and the resistance value of the MOS feedback resistor is changed greatly, so that large signal distortion is generated.

In the third scheme, although the amplifier saturation distortion caused by the influence of the offset voltage can be relieved to a certain extent by setting the multiple of the amplifier to be smaller, the signal acquisition precision can also be influenced by the noise of the amplifier due to the smaller gain. While low amplification is generally insufficient to achieve a high signal-to-noise ratio of the signal. The need for an ultra-high resolution ADC again necessarily results in increased design difficulty and increased solution cost.

In the fourth scheme, offset voltage cancellation is performed by introducing a digital algorithm circuit, and a large circuit scale generally makes system design more complicated, so that silicon chip cost is high and additional circuit noise is introduced by integrating a digital circuit.

Therefore, the technical scheme of the utility model has following advantage: the utility model discloses the scheme does not need outside discrete device can realize the high pass and ends, can not only realize the integrated and low cut-off frequency of chip, can also effectively eliminate the direct current imbalance of electrode and do not arouse target signal's distortion to can suppress motion artifact to a certain extent, the utility model discloses a circuit design is simple and easy, change integrated, the volume is littleer, the cost is lower, the consumption is littleer.

Fig. 2 is a schematic structural diagram of another embodiment of the configurable low-frequency high-pass filter of the present invention;

as shown in fig. 2, the configurable low-frequency high-pass filter of this embodiment further includes, on the basis of the embodiment of fig. 1: a first fast setup switch circuit 100 and a second fast setup switch circuit 110;

one end of the first fast set-up switching circuit 100 is connected to the connection node a, and the other end is connected to the connection node C; one end of the second fast set-up switch circuit 110 is connected to the connection node B, and the other end is connected to the connection node D; the first fast set-up switching circuit 100 and the second fast set-up switching circuit 110 are used to increase the response speed of the configurable low frequency high pass filter during probe turn-on and turn-off.

The utility model discloses this kind of low frequency amplification filtering scheme of configurable low frequency high pass filter is in practical application, because the ultralow cut-off frequency is very low, when the input disconnection reconnects again, the response is very slow (feedback loop high impedance node leads to circuit response time slow), and it is very long time that the output is stable promptly. Therefore, the rapid establishment switching circuit is introduced to enable the amplifying circuit to be short-circuited for a short time at the initial stage of starting work, so that the voltages of the node A and the node B or the node C and the node D can be rapidly established near a working point, then the rapid establishment switching circuit is disconnected, the amplifying circuit enters a normal working state, and the response speed of the circuit in the electrode connection and disconnection processes is improved.

Fig. 3 is a schematic circuit diagram of an embodiment of the configurable low frequency high pass filter of the present invention; as shown in fig. 3, the first dc feedback circuit 60 includes: a first PMOS transistor M1, a second PMOS transistor M2, a first bias source U1 and a second bias source U2; the second dc feedback circuit 70 includes: a third PMOS transistor M3, a fourth PMOS transistor M4, a third bias source U3, and a fourth bias source U4;

the source of the first PMOS tube M1 is connected with the connection node A, the drain of the first PMOS tube M1 is connected with the drain of the second PMOS tube M2, the gate of the first PMOS tube M1 is connected with the source of the second PMOS tube through a first bias source U1, the gate of the second PMOS tube M2 is connected with the output common-mode reference voltage VCM through a second bias source U2, and the source of the second PMOS tube M2 is connected with the connection node C;

the source of the third PMOS transistor M3 is connected to the connection node B, the drain of the third PMOS transistor M3 is connected to the drain of the fourth PMOS transistor M4, the gate of the third PMOS transistor M3 is connected to the source of the fourth PMOS transistor M3 via a third bias voltage source U3, the gate of the fourth PMOS transistor M4 is connected to the output common-mode reference voltage VCM via a fourth bias voltage source U4, and the source of the fourth PMOS transistor M4 is connected to the connection node D;

by adjusting the bias voltage values output by the first bias voltage source U1, the second bias voltage source U2, the third bias voltage source U3 and the fourth bias voltage source U4, the first PMOS transistor M1, the second PMOS transistor M2, the third PMOS transistor M3 and the fourth PMOS transistor M4 work in weak inversion states of different degrees to obtain different large resistance values.

The MOS feedback resistors of the first dc feedback circuit 60 and the second dc feedback circuit 70 are implemented by two PMOS transistors respectively in a cross-coupled back-to-back manner. When the circuit works stably, the voltage of the connection node a and the connection node B is equal to the output common-mode reference voltage VCM of the operational amplifier, and the connection node a and the connection node B belong to high-impedance nodes and have no driving capability, so that the voltage of the node a and the node B can be equalized by the output common-mode reference voltage VCM of the operational amplifier when the gate bias voltage is generated, that is, the gate of the second PMOS transistor M2 can be directly connected to the connection node a through the second bias voltage source U2, and the gate of the fourth PMOS transistor M4 can be directly connected to the connection node B through the fourth bias voltage source U4.

Besides the above circuit structure, the MOS feedback resistors may also be in the form of a plurality of cascaded series connections, and are not limited to MOS transistors.

Due to different bioelectric signals, frequency components of interest are often different, and the filtering frequency can be configured to meet different application requirements. Therefore, the utility model discloses a first direct current feedback circuit 60 and second direct current feedback circuit 70 adopt the MOS pipe to act as direct current feedback resistance, through the gate bias voltage configuration feedback resistance's of adjustment MOS pipe resistance to satisfy different cut-off frequency high pass filter's requirement. The MOS feedback resistor adopts a cross-coupling structure, the linearity of the feedback resistor is improved, and the sensitivity of the resistance value of the feedback resistor along with the process change is reduced by controlling the gate bias voltage through the current.

The voltage of a bias voltage source connected to the grid of the MOS tube is adjusted, so that a certain difference value is formed between the grid voltage of the MOS tube and the output common-mode voltage of the operational amplifier, and the MOS tube works in a weak-reverse state, so that the required resistance value is obtained, and the adjustable high-pass cut-off frequency is realized.

Specifically, the utility model discloses a can dispose low frequency high pass filter's high pass cut-off frequency does:

wherein R is_fC is an equivalent resistance value of the MOS feedback resistor of the first dc feedback circuit 60 or the second dc feedback circuit 70, and C is a total capacitance value of the first feedback capacitor array circuit 80 or the second feedback capacitor array circuit 90. It is understood that the total capacitance values of the first feedback capacitor array circuit 80 or the second feedback capacitor array circuit 90 are equal, and the equivalent resistance values of the MOS feedback resistors of the first dc feedback circuit 60 or the second dc feedback circuit 70 are equal.

Further, the first biasing source U1, the second biasing source U2, the third biasing source U3, and the fourth biasing source U4 are all the same biasing source.

Fig. 4 is a schematic circuit diagram of an internal circuit of a bias source in the configurable low frequency high pass filter of the present invention.

As shown in fig. 4, the internal circuit of the bias source includes: a fifth PMOS tube M5, an NMOS tube array Mx1-Mxn and an NMOS tube array driving circuit;

the NMOS tube array Mx1-Mxn is formed by connecting a plurality of NMOS tubes in parallel, the drain electrode of a fifth PMOS tube M5 is connected with the drain electrode parallel node of the NMOS tube array Mx1-Mxn, the grid electrode and the drain electrode of the fifth PMOS tube M5 are in short circuit, and the source electrode parallel node of the NMOS tube array Mx1-Mxn is grounded GND;

the NMOS tube array driving circuit comprises a plurality of sub-driving circuits, and each sub-driving circuit comprises: NMOS tube Ms1, NMOS tube Mr1, NMOS tube Mn1 and PMOS tube Mp 1; the drain electrode of the NMOS tube Ms1 is connected with a voltage input end Vbias, the source electrode of the NMOS tube Ms1 is connected with the drain electrode of the NMOS tube Mr1, the source electrode of the PMOS tube Mp1 is connected with VDD, the drain electrode of the PMOS tube Mp1 is connected with the drain electrode of the NMOS tube Mn1, the source electrode of the NMOS tube Mn1 is grounded, the gate electrode of the NMOS tube Mr1 is connected with the connection point of the drain electrode of the PMOS tube Mp1 and the drain electrode of the NMOS tube Mn1, the gate electrodes of the NMOS tube Ms1, the PMOS tube Mp1 and the NMOS tube Mn1 are connected with a selection signal input end Sel1, the connection point of the source electrode of the NMOS tube Ms1 and the drain electrode of the NMOS tube Mr1 is a driving signal output end Vb1 of the sub-driving circuit, and driving signal output ends Vb1-Vbn of the plurality of sub-driving circuits are;

the current value flowing through the fifth PMOS pipe M5 is adjusted through the selection signal input ends of the plurality of sub driving circuits to generate different bias voltage values, so that the resistance value of the MOS feedback resistor is adjusted, and the configuration requirements of different high-pass filtering cut-off frequencies are met.

The gate bias voltage V1 of the first PMOS transistor M1 is taken as an example to describe the generation principle of the gate bias voltage. The current I flowing through the fifth PMOS transistor M5 is generated by the NMOS transistor arrays Mxn-Mx1 with gates connected to Vbn-Vb1, respectively. Vbn-Vb1 is connected to voltage input terminal Vbias or GND, respectively, as determined by selection control signal Seln-Sel 1. When the selection control signal Seln is at a high level, the corresponding switch tube Msn is turned on, the switch tube Mrn is turned off, Vbn is connected to Vbias, and the corresponding NMOS tube Mxn is equivalent to a sub-current source In; when Seln is low, the switch tube Msn is turned off, the switch tube Mrn is turned on, Vbn is connected to GND, the corresponding NMOS tube Mxn operates in the off state, and the current generated by the corresponding NMOS tube is 0. The current I flowing through the fifth PMOS transistor M5 is the sum of the currents generated by the NMOS transistor arrays Mxn-Mx1, that is, when a plurality of signals in the selection control signal Seln-Sel1 are at high level, a corresponding plurality of NMOS transistors in the NMOS transistor arrays Mx1-Mxn are turned on, and thus the current I flowing through the fifth PMOS transistor M5 is the sum of the currents generated by the corresponding turned-on NMOS transistors. For example, NMOS transistors Mxn1, Mxn2, Mxn3 in the NMOS transistor array Mx1-Mxn are turned on, and currents flowing through NMOS transistors Mxn1, Mxn2, Mxn3 are I1, I2, I3, respectively, so that the current I flowing through the fifth PMOS transistor M5 is I1+ I2+ I3. The current I flows through the gate and drain shorted M5, resulting in the bias voltage V1.

When the current I is small, M5 operates in the sub-threshold region, and when the bias voltage V1 is applied to the gate of the first PMOS transistor M1, the first PMOS transistor M1 also operates in the sub-threshold region. The current formula of the MOS tube can be obtained as follows:

where Vc is the voltage at the node C, V1 is the bias voltage V1, u applied to the MOS transistor M1_nIs the carrier mobility of the silicon wafer, C_oxIs a gate capacitance per unit area, V_thIs the threshold voltage of the MOS transistor M5,

is the width-to-length ratio of the oxide layer of the MOS transistor M5. Further, it can be deduced that:

thereby obtaining the bias voltage V1.

The channel virtual impedance of the MOS transistor M1 may be equivalent to:

wherein the content of the first and second substances,

is the width-to-length ratio of the oxide layer of the MOS transistor M1. It can be known from the formula that the impedance is independent of the threshold voltage of the MOS transistor, and thus the sensitivity to process and temperature fluctuations is reduced.

Further, the first chopping switching circuit 20 includes an NMOS transistor Mns1, an NMOS transistor Mns2, an NMOS transistor Mns3, and an NMOS transistor Mns 4;

the second chopping switch circuit 40 comprises an NMOS transistor Mns5, an NMOS transistor Mns6, an NMOS transistor Mns7 and an NMOS transistor Mns 8;

the drain of the NMOS transistor Mns1 is connected to the drain of the NMOS transistor Mns2 and then to the connection node a, the source of the NMOS transistor Mns1 is connected to the negative phase input terminal of the operational amplifier circuit 30, and the source of the NMOS transistor Mns2 is connected to the positive phase input terminal of the operational amplifier circuit 30; the drain of the NMOS transistor Mns3 is connected to the drain of the NMOS transistor Mns4 and then to the connection node B, the source of the NMOS transistor Mns3 is connected to the negative phase input terminal of the operational amplifier circuit 30, and the source of the NMOS transistor Mns4 is connected to the positive phase input terminal of the operational amplifier circuit 30;

the drain of the NMOS transistor Mns5 is connected to the drain of the NMOS transistor Mns6 and then to the connection node C, the source of the NMOS transistor Mns5 is connected to the positive phase output terminal of the operational amplifier circuit 30, and the source of the NMOS transistor Mns6 is connected to the negative phase output terminal of the operational amplifier circuit 30; the drain of the NMOS transistor Mns7 is connected to the drain of the NMOS transistor Mns8 and then to the connection node D, the source of the NMOS transistor Mns7 is connected to the positive phase output terminal of the operational amplifier circuit 30, and the source of the NMOS transistor Mns8 is connected to the negative phase output terminal of the operational amplifier circuit 30;

the on-off of the NMOS transistor Mns2, the NMOS transistor Mns3, the NMOS transistor Mns6 and the NMOS transistor Mns7 is controlled by a first driving control signal S1 applied to the gate, the on-off of the NMOS transistor Mns1, the NMOS transistor Mns4, the NMOS transistor Mns5 and the NMOS transistor Mns8 is controlled by a second driving control signal S2 applied to the gate, and the first driving control signal S1 and the second driving control signal S2 are opposite-phase signals. Specifically, the timing waveforms of the first driving control signal S1 and the second driving control signal S2 are shown in fig. 5.

The utility model discloses a can dispose low frequency high pass filter work when normal operating condition, the control signal S1 and S2 periodic upset that each other is the looks inverting this moment for two inputs and two output of operational amplifier circuit 30 chop periodically and switch, modulate the low frequency noise that the voltage imbalance of operational amplifier circuit 30 self and components and parts were introduced to the high frequency.

Further, the coupling capacitor circuit 10 includes a first capacitor C1 and a second capacitor C2;

the first capacitor C1 is connected between the positive electrode VINP of the probe and the connection node A, the second capacitor C2 is connected between the negative electrode VINN of the probe and the connection node B, and the resistance values of the first capacitor C1 and the second capacitor C2 are equal. The coupling capacitor circuit 10 is not only used to isolate the dc voltage input by the electrode probe, but also to implement a part of the amplification.

Further, the first feedback capacitor array circuit 80 includes a plurality of feedback capacitor sub-circuits, each feedback capacitor sub-circuit includes a capacitor C3 and two same MOS switch tubes, one end of the capacitor C3 is connected to the connection node a through one MOS switch tube, the other end of the capacitor C3 is connected to the connection node C through another MOS switch tube, and the plurality of feedback capacitor sub-circuits are connected in parallel;

the second feedback capacitor array circuit 90 comprises a plurality of feedback capacitor sub-circuits, each feedback capacitor sub-circuit comprises a capacitor C4 and two same MOS switch tubes, one end of the capacitor C4 is connected with the connection node B through one MOS switch tube, the other end of the capacitor C3 is connected with the connection node D through the other MOS switch tube, and the feedback capacitor sub-circuits of the second feedback capacitor array circuit 90 are connected in parallel; the total capacitance values of the first feedback capacitor array circuit 80 and the second feedback capacitor array circuit 90 are equal;

the total capacitance value of the configurable low-frequency high-pass filter accessed by the first feedback capacitor array circuit 80 and the second feedback capacitor array circuit 90 is adjusted by controlling the on-off of the MOS switch tube of the feedback capacitor sub-circuit, so that the amplification factor of the configurable low-frequency high-pass filter is adjusted.

Specifically, assuming that the first feedback capacitor array circuit 80 includes the feedback capacitor arrays C3a-C3x and the second feedback capacitor array circuit 90 includes the feedback capacitor arrays C4a-C4x, the adjustable amplification factor is realized by adjusting the ratio of the resistances of the feedback capacitor arrays C3a-C3x and C4a-C4x to the first capacitor array C1. For example, when the total capacitance value of the feedback capacitor array C3a-C3x and the total capacitance value of the feedback capacitor array C4a-C4x are both C, the AC signal amplification factor is increased

When C is present₁When being equal to C, magnification factor C_v＝1。

Further, the first fast setup switching circuit 100 and the second fast setup switching circuit 110 are both MOS transistor switching circuits; the MOS tube is controlled by a control signal S0 applied to the grid electrode, when the control signal S0 is at a high level, the MOS tube switch circuit is switched on, and when the control signal S0 is at a low level, the MOS tube switch circuit is switched off. The timing waveform of the control signal S0 is shown in fig. 5.

Further, the filter circuit 50 includes a first resistor R1, a second resistor R2, a fifth capacitor C5;

a first end of the first resistor R1 is connected to the connection node C, a second end of the first resistor R1 serves as a negative output terminal VOUTN of the configurable low-frequency high-pass filter, a first end of the second resistor R2 is connected to the connection node D, a second end of the second resistor serves as a positive output terminal VOUTP of the configurable low-frequency high-pass filter, and the fifth capacitor C5 is connected between a second end of the first resistor R1 and a second end of the second resistor R2.

The filter circuit 50 performs low-pass filtering, which removes an offset voltage and noise modulated to a high frequency by the first chopping switch circuit 20 and the second chopping switch circuit 40, and whose cutoff frequency is lower than one tenth of the chopping frequency.

Fig. 6 is a schematic circuit diagram of an operational amplifier in the configurable low frequency high pass filter of the present invention.

As shown in fig. 6, the operational amplifier circuit 30 includes an amplifier main circuit and a common mode feedback loop; the amplifier main body circuit comprises PMOS tubes PM1, PM2, PM3, PM5, PM6, PM7, PM8 and NMOS tubes NM1, NM2, MN3 and NM 4;

the source of the PMOS transistor PM1, the gate of the PMOS transistor PM2, the gate of the PMOS transistor PM3 is connected to the power supply input terminal VDD, the gate of the PMOS transistor PM1 is connected to the first bias signal VP1, the gate of the PMOS transistor PM2 is connected to the gate of the PMOS transistor PM3 and to the first bias signal VP1, the drain of the PMOS transistor PM2 is connected to the source of the PMOS transistor PM5, the drain of the PMOS transistor PM3 is connected to the source of the PMOS transistor PM6, the gate of the PMOS transistor PM5 is connected to the gate of the PMOS transistor PM6 and to the second bias signal VP2, the source of the PMOS transistor PM7 is connected to the source of the PMOS transistor PM8 and to the drain of the PMOS transistor PM1, the gate of the PMOS transistor PM7 is the positive phase input terminal VIP of the operational amplifier circuit 30, and the gate of the PMOS transistor PM 8;

the drain of the NMOS tube NM1 is connected to the drain of the PMOS tube PM5 and serves as the negative phase output terminal VON of the operational amplifier circuit 30, the drain of the NMOS tube NM2 is connected to the drain of the PMOS tube PM6 and serves as the positive phase output terminal VOP of the operational amplifier circuit 30, the source of the NMOS tube NM1 is connected to the drain of the NMOS tube NM3 and to the drain of the PMOS tube PM7, the source of the NMOS tube NM2 is connected to the drain of the NMOS tube NM4 and to the drain of the PMOS tube PM8, the gate of the NMOS tube NM1 is connected to the gate of the NMOS tube NM2 and to the third bias signal VN2, the source of the NMOS tube NM3 is connected to the source of the NMOS tube NM4 and to ground GND, and the gate of the NMOS tube NM3 is connected to the gate of the NMOS tube NM4 and to the fourth bias signal;

the common-mode feedback loop comprises PMOS tubes PM4, PM9 and PM10, NMOS tubes NM5 and NM6 and two resistors R3 and R4 with equal resistance values;

the source of the PMOS transistor PM4 is connected to the power supply input terminal VDD, the gate of the PMOS transistor PM4 is connected to the first bias signal VP1, the source of the PMOS transistor PM9 is connected to the source of the PMOS transistor PM10 and to the drain of the PMOS transistor PM4, the gate of the PMOS transistor PM9 is connected to the input reference voltage VCM, the drain of the PMOS transistor PM9 is connected to the drain of the NMOS transistor NM5 and to the connection point of the gate of the NMOS transistor NM3 and the gate of the NMOS transistor NM4, the drain of the PMOS transistor PM10 is connected to the drain of the NMOS transistor NM6, the gate of the NMOS transistor NM5 is connected to the gate of the NMOS transistor NM6 and to the drain of the NMOS transistor NM6, and the source of the NMOS transistor NM5 and the source of the NMOS transistor NM 6;

a first terminal of the resistor R3 is connected to the positive phase output terminal VOP of the operational amplifier circuit 30, a first terminal of the resistor R4 is connected to the negative phase output terminal VON of the operational amplifier circuit 30, and a second terminal of the resistor R3 is connected to the second terminal of the resistor R4 and connected to the gate of the PMOS transistor PM 10.

Two resistors R3 and R4 with equal resistance are used for collecting the output common-mode voltage VCMO of the operational amplifier circuit (30), and the common-mode voltage is consistent with the input reference voltage VCM through a common-mode feedback loop.

The structure of the above-mentioned operational amplifier circuit 30 is the fully differential foldable cascode structure, and certainly the operational amplifier circuit 30 page or leaf can be changed into other deformation forms, if adopt the NMOS pipe as the input geminate transistor, or use the differential structure of other forms, belong to the utility model provides a circuit design idea equally.

The utility model discloses can dispose low frequency high pass filter utilizes integrated MOS feedback resistance and electric capacity to realize that the low frequency high pass characteristic realizes that the imbalance is eliminated and motion artifact suppresses, switches the modulation through the chopping simultaneously and realizes circuit low noise performance, through the low frequency response speed who establishes switch circuit lift circuit fast, and the high pass is realized through adjusting MOS pipe grid bias voltage and feedback capacitor array respectively with the gain configuration of enlargiing. Therefore, the utility model discloses can dispose low frequency high pass filter and have the high pass filtering characteristic of low frequency to can solve low frequency high pass circuit response speed and signal tailing phenomenon slowly. The circuit has the characteristics of high-pass cut-off frequency and configurable amplification factor, and meanwhile, the circuit has good linear performance, low power consumption and low noise performance. And the single operational amplifier structure is easy to integrate and realize under the standard CMOS process, occupies small chip area, has low cost and is easy to embed in a signal sensing acquisition system chip.

It should be further noted that, although the present invention is based on the collection of the bioelectric signal as a design background, the present invention is not limited to the field of collection of the bioelectric signal. The design method and the circuit structure can also be applied to other sensing circuits and signal acquisition systems of weak electric signals.

It should be noted that, although the present invention needs to perform some specific control through the control signal, it does not relate to the improvement of the computer program, that is, the present invention only uses the prior art to generate the corresponding control signal to perform the corresponding control, and it does not relate to the improvement of the computer program.

The present invention has been described in terms of specific embodiments, and it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims (10)

1. A configurable low frequency high pass filter, comprising: a coupling capacitor circuit (10), a first chopping switch circuit (20), an operational amplifier circuit (30), a second chopping switch circuit (40), a filter circuit (50), a first direct current feedback circuit (60), a second direct current feedback circuit (70), a first feedback capacitor array circuit (80) and a second feedback capacitor array circuit (90), wherein,

the input end of the coupling capacitor circuit (10) is respectively connected with the positive electrode VINP of the probe and the negative electrode VINN of the probe; a first output end and a second output end of the coupling capacitor circuit (10) are respectively connected with a first input end and a second input end of the first chopping switch circuit (20); a first output end and a second output end of the first chopping switch circuit (20) are respectively connected with a positive phase input end and a negative phase input end of the operational amplifier circuit (30), and a negative phase output end and a positive phase output end of the operational amplifier circuit (30) are respectively connected with a first input end and a second input end of the second chopping switch circuit (40); a first output end and a second output end of the second chopping switching circuit (40) are respectively connected with a first input end and a second input end of the filter circuit (50); a first output end of the filter circuit (50) is used as a negative output end VOUTN of the configurable low-frequency high-pass filter, and a second output end of the filter circuit (50) is used as a positive output end VOUTP of the configurable low-frequency high-pass filter;

the first direct current feedback circuit (60) is connected with the first feedback capacitor array circuit (80) in parallel, then one parallel end of the first direct current feedback circuit is connected to a connection node A of the first output end of the coupling capacitor circuit (10) and the first input end of the first chopping change-over switch circuit (20), and the other parallel end of the first direct current feedback circuit is connected to a connection node C of the first output end of the second chopping change-over switch circuit (40) and the first input end of the filter circuit (50);

the second direct-current feedback circuit (70) and the second feedback capacitor array circuit (90) are connected in parallel, and then a parallel end of the second direct-current feedback circuit is connected to a connection node B between the second output end of the coupling capacitor circuit (10) and the second input end of the first chopping change-over switch circuit (20), and the other parallel end of the second direct-current feedback circuit is connected to a connection node D between the second output end of the second chopping change-over switch circuit (40) and the second input end of the filter circuit (50);

the coupling capacitor circuit (10) is used for isolating the direct-current voltage input by the probe; the first chopping switching circuit (20) and the second chopping switching circuit (40) modulate direct-current offset voltage and component noise caused by component mismatch in the configurable low-frequency high-pass filter to be out of a preset frequency band by periodically switching two-phase states; the first feedback capacitor array circuit (80) and the second feedback capacitor array circuit (90) provide feedback paths for alternating current signals; the first DC feedback circuit (60) and the second DC feedback circuit provide feedback paths for DC signals; the filter circuit (50) is used for filtering out the direct current offset voltage and the component noise which are modulated to be out of the preset frequency band.

2. The configurable low-frequency high-pass filter according to claim 1, characterized in that said first direct current feedback circuit (60) comprises: a first PMOS transistor M1, a second PMOS transistor M2, a first bias source U1 and a second bias source U2; the second direct current feedback circuit (70) includes: a third PMOS transistor M3, a fourth PMOS transistor M4, a third bias source U3, and a fourth bias source U4;

the source of the first PMOS transistor M1 is connected to the connection node a, the drain of the first PMOS transistor M1 is connected to the drain of the second PMOS transistor M2, the gate of the first PMOS transistor M1 is connected to the source of the second PMOS transistor M1 via the first bias source U1, the gate of the second PMOS transistor M2 is connected to the output common-mode reference voltage VCM via the second bias source U2, and the source of the second PMOS transistor M2 is connected to the connection node C;

the source of the third PMOS transistor M3 is connected to the connection node B, the drain of the third PMOS transistor M3 is connected to the drain of the fourth PMOS transistor M4, the gate of the third PMOS transistor M3 is connected to the source of the fourth PMOS transistor M3 via the third bias source U3, the gate of the fourth PMOS transistor M4 is connected to the output common-mode reference voltage VCM via the fourth bias source U4, and the source of the fourth PMOS transistor M4 is connected to the connection node D;

by adjusting the bias voltage values output by the first bias voltage source U1, the second bias voltage source U2, the third bias voltage source U3 and the fourth bias voltage source U4, the first PMOS transistor M1, the second PMOS transistor M2, the third PMOS transistor M3 and the fourth PMOS transistor M4 work in weak inversion states of different degrees to obtain different large resistance values.

3. The configurable low-frequency high-pass filter of claim 2, wherein the first bias source U1, the second bias source U2, the third bias source U3 and the fourth bias source U4 are all the same bias sources, and the internal circuit of the bias sources comprises: a fifth PMOS tube M5, an NMOS tube array Mx1-Mxn and an NMOS tube array driving circuit;

the NMOS tube array Mx1-Mxn is formed by connecting a plurality of NMOS tubes in parallel, the drain electrode of the fifth PMOS tube M5 is connected with the drain electrode parallel node of the NMOS tube array Mx1-Mxn, the grid electrode and the drain electrode of the fifth PMOS tube M5 are in short circuit, and the source electrode parallel node of the NMOS tube array Mx1-Mxn is grounded GND;

the NMOS tube array driving circuit comprises a plurality of sub-driving circuits, and each sub-driving circuit comprises: NMOS tube Ms1, NMOS tube Mr1, NMOS tube Mn1 and PMOS tube Mp 1; the drain of the NMOS tube Ms1 is connected to a voltage input terminal Vbias, the source of the NMOS tube Ms1 is connected to the drain of the NMOS tube Mr1, the source of the PMOS tube Mp1 is connected to VDD, the drain of the PMOS tube Mp1 is connected to the drain of the NMOS tube Mn1, the source of the NMOS tube Mn1 is grounded, the gate of the NMOS tube Mr1 is connected to the connection point of the drain of the PMOS tube Mp1 and the drain of the NMOS tube Mn1, the gates of the NMOS tube Ms1, the PMOS tube Mp1 and the NMOS tube Mn1 are connected to a selection signal input terminal Sel1, the connection point of the source of the NMOS tube Ms1 and the drain of the NMOS tube Mr1 is a driving signal output terminal Vb1 of the sub-driving circuit, and the driving signal output terminals Vb1-Vbn of the sub-driving circuit are correspondingly connected to the gates of the NMOS tube array Mx1-Mxn, respectively;

the current value flowing through the fifth PMOS transistor M5 is adjusted through the selection signal input ends of a plurality of sub driving circuits to generate different bias voltage values.

4. The configurable low-frequency high-pass filter of claim 1, wherein the first chopping switch circuit (20) comprises NMOS transistor Mns1, NMOS transistor Mns2, NMOS transistor Mns3, NMOS transistor Mns 4;

the second chopping switch circuit (40) comprises an NMOS tube Mns5, an NMOS tube Mns6, an NMOS tube Mns7 and an NMOS tube Mns 8;

the drain of the NMOS transistor Mns1 is connected to the drain of the NMOS transistor Mns2 and then to the connection node a, the source of the NMOS transistor Mns1 is connected to the negative input terminal of the operational amplifier circuit (30), and the source of the NMOS transistor Mns2 is connected to the positive input terminal of the operational amplifier circuit (30); the drain of the NMOS transistor Mns3 is connected to the drain of the NMOS transistor Mns4 and then to the connection node B, the source of the NMOS transistor Mns3 is connected to the negative input terminal of the operational amplifier circuit (30), and the source of the NMOS transistor Mns4 is connected to the positive input terminal of the operational amplifier circuit (30);

the drain of the NMOS transistor Mns5 is connected to the drain of the NMOS transistor Mns6 and then to the connection node C, the source of the NMOS transistor Mns5 is connected to the positive phase output terminal of the operational amplifier circuit (30), and the source of the NMOS transistor Mns6 is connected to the negative phase output terminal of the operational amplifier circuit (30); the drain of the NMOS transistor Mns7 is connected to the drain of the NMOS transistor Mns8 and then to the connection node D, the source of the NMOS transistor Mns7 is connected to the positive phase output terminal of the operational amplifier circuit (30), and the source of the NMOS transistor Mns8 is connected to the negative phase output terminal of the operational amplifier circuit (30);

the on-off of the NMOS transistor Mns2, the NMOS transistor Mns3, the NMOS transistor Mns6 and the NMOS transistor Mns7 is controlled by a first driving control signal S1 applied to the gate, the on-off of the NMOS transistor Mns1, the NMOS transistor Mns4, the NMOS transistor Mns5 and the NMOS transistor Mns8 is controlled by a second driving control signal S2 applied to the gate, and the first driving control signal S1 and the second driving control signal S2 are opposite-phase signals.

5. The configurable low-frequency high-pass filter according to claim 1, characterized in that said coupling capacitor circuit (10) comprises a first capacitor C1 and a second capacitor C2;

the first capacitor C1 is connected between the positive electrode VINP of the probe and the connection node A, the second capacitor C2 is connected between the negative electrode VINN of the probe and the connection node B, and the resistance values of the first capacitor C1 and the second capacitor C2 are equal.

6. The configurable low-frequency high-pass filter according to claim 5, wherein said first feedback capacitor array circuit (80) comprises a plurality of feedback capacitor sub-circuits, each of said feedback capacitor sub-circuits comprises a capacitor C3 and two identical MOS switch transistors, one end of said capacitor C3 is connected to said connection node A via one of said MOS switch transistors, the other end of said capacitor C3 is connected to said connection node C via another of said MOS switch transistors, and a plurality of said feedback capacitor sub-circuits are connected in parallel;

the second feedback capacitor array circuit (90) comprises a plurality of feedback capacitor sub-circuits, each feedback capacitor sub-circuit comprises a capacitor C4 and two identical MOS switching tubes, one end of the capacitor C4 is connected with the connection node B through one MOS switching tube, the other end of the capacitor C3 is connected with the connection node D through the other MOS switching tube, and the feedback capacitor sub-circuits of the second feedback capacitor array circuit (90) are connected in parallel; the total capacitance value of the first feedback capacitor array circuit (80) and the second feedback capacitor array circuit (90) is equal;

and the total capacitance value of the configurable low-frequency high-pass filter accessed by the first feedback capacitor array circuit (80) and the second feedback capacitor array circuit (90) is adjusted by controlling the on-off of an MOS (metal oxide semiconductor) switching tube of the feedback capacitor sub-circuit, so that the amplification factor of the configurable low-frequency high-pass filter is adjusted.

7. A configurable low-frequency high-pass filter according to claim 1, characterized in that said operational amplifier circuit (30) comprises an amplifier body circuit and a common-mode feedback loop; the amplifier main body circuit comprises PMOS tubes PM1, PM2, PM3, PM5, PM6, PM7, PM8 and NMOS tubes NM1, NM2, MN3 and NM 4;

the source of the PMOS transistor PM1, PM2, PM3 is connected to the power supply input terminal VDD, the gate of the PMOS transistor PM1 is connected to the first bias signal VP1, the gate of the PMOS transistor PM2 is connected to the gate of the PMOS transistor PM3 and to the first bias signal VP1, the drain of the PMOS transistor PM2 is connected to the source of the PMOS transistor PM5, the drain of the PMOS transistor PM3 is connected to the source of the PMOS transistor PM6, the gate of the PMOS transistor PM5 is connected to the gate of the PMOS transistor PM6 and to the second bias signal VP2, the source of the PMOS transistor PM7 is connected to the source of the PMOS transistor PM8 and to the drain of the PMOS transistor PM1, the gate of the PMOS transistor PM7 is the positive phase input terminal of the operational amplifier circuit (VIP 30), and the gate of the PMOS transistor PM8 is the negative phase input terminal of the operational amplifier circuit (30);

the drain of the NMOS transistor NM1 is connected to the drain of the PMOS transistor PM5 and serves as the negative phase output terminal VON of the operational amplifier circuit (30), the drain of the NMOS transistor NM2 is connected to the drain of the PMOS transistor PM6 and serves as the positive phase output terminal VOP of the operational amplifier circuit (30), the source of the NMOS transistor NM1 is connected to the drain of the NMOS transistor NM3 and to the drain of the PMOS transistor PM7, the source of the NMOS transistor NM2 is connected to the drain of the NMOS transistor NM4 and to the drain of the PMOS transistor PM8, the gate of the NMOS transistor NM1 is connected to the gate of the NMOS transistor NM2 and to the third bias signal VN2, the source of the NMOS transistor NM3 is connected to the source of the NMOS transistor NM4 and to ground, and the gate of the NMOS transistor NM3 is connected to the gate of the NMOS transistor NM4 and to the fourth bias signal VN 1;

the common-mode feedback loop comprises PMOS tubes PM4, PM9 and PM10, NMOS tubes NM5 and NM6 and two resistors R3 and R4 with equal resistance values;

a source of the PMOS transistor PM4 is connected to a power supply input terminal VDD, a gate of the PMOS transistor PM4 is connected to a first bias signal VP1, a source of the PMOS transistor PM9 is connected to a source of the PMOS transistor PM10 and to a drain of the PMOS transistor PM4, a gate of the PMOS transistor PM9 is connected to an input reference voltage VCM, a drain of the PMOS transistor PM9 is connected to a drain of the NMOS transistor NM5 and to a connection point of the gate of the NMOS transistor NM3 and the gate of the NMOS transistor NM4, a drain of the PMOS transistor PM10 is connected to the drain of the NMOS transistor NM6, a gate of the NMOS transistor NM5 is connected to the gate of the NMOS transistor NM6 and to the drain of the NMOS transistor NM6, and a source of the NMOS transistor NM5 is connected to the source of the NMOS transistor NM6 and to ground GND;

the first end of the resistor R3 is connected with the positive phase output end VOP of the operational amplifier circuit (30), the first end of the resistor R4 is connected with the negative phase output end VON of the operational amplifier circuit (30), and the second end of the resistor R3 is connected with the second end of the resistor R4 and connected with the grid electrode of the PMOS transistor PM 10.

8. The configurable low frequency high pass filter of claim 1, further comprising: a first fast setup switch circuit (100) and a second fast setup switch circuit (110);

one end of the first fast set-up switch circuit (100) is connected to the connection node A, and the other end is connected to the connection node C; -one end of the second fast set-up switching circuit (110) is connected to the connection node B and the other end is connected to the connection node D; the first fast-set-up switching circuit (100) and the second fast-set-up switching circuit (110) are used for improving the response speed of the configurable low-frequency high-pass filter in the process of connecting and disconnecting the probe.

9. The configurable low-frequency high-pass filter according to claim 8, wherein said first fast settling switching circuit (100) and said second fast settling switching circuit (110) are MOS transistor switching circuits; the MOS tube is controlled by a control signal S0 applied to a grid electrode, when the control signal S0 is at a high level, the MOS tube switch circuit is switched on, and when the control signal S0 is at a low level, the MOS tube switch circuit is switched off.

10. The configurable low-frequency high-pass filter according to claim 1, characterized in that said filtering circuit (50) comprises a first resistor R1, a second resistor R2, a fifth capacitor C5;

a first end of the first resistor R1 is connected to the connection node C, a second end of the first resistor R1 serves as a negative output terminal VOUTN of the configurable low-frequency high-pass filter, a first end of the second resistor R2 is connected to the connection node D, a second end of the second resistor serves as a positive output terminal VOUTP of the configurable low-frequency high-pass filter, and the fifth capacitor C5 is connected between the second end of the first resistor R1 and the second end of the second resistor R2.

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