CN212572589U - High-instantaneity EtherCAT hardware main station system - Google Patents

Abstract

The application discloses a high-instantaneity EtherCAT hardware master station system which is characterized by comprising a computer mainboard, wherein the computer mainboard is provided with a PCIE interface; the Ethernet Cat main station comprises an FPGA and a CH368L interface chip, the FPGA is connected to a PCIE bus through the CH368L interface chip, and the PCIE bus is connected with the PCIE interface and enters the computer mainboard; the CH368L interface chip controls the FPGA. Therefore, the real-time data can be transmitted and received, and the strong real-time performance of the data is realized and guaranteed from a hardware level.

Description

High-instantaneity EtherCAT hardware main station system

Technical Field

The application relates to the technical field of network equipment, in particular to a high-instantaneity EtherCAT hardware master station system.

Background

The information disclosed in this prior art section of this discussion is merely for enhancement of understanding of the background of the disclosure and is not to be considered as an admission or any form of suggestion that this information forms prior art that is already known to a person skilled in the art.

With the development of science and technology, the application of the communication protocol system based on the Ethernet is rapidly expanded into an automatic system, and data frames in an EtherCAT protocol transmission mode are transmitted by master station equipment. However, in the master station in the prior art, the socket original socket group package sending and receiving modes are mostly used for operation, a large amount of repeated work exists, and on the same machine, the performance is limited, so that the cpu load is high, the scheduling is frequent, the real-time performance and the stability are not high, and the master station cannot meet higher requirements

SUMMERY OF THE UTILITY MODEL

The application provides a high real-time EtherCAT hardware main website system has solved one or more among the prior art problem.

According to one aspect of the application, the high-instantaneity EtherCAT hardware master station system is characterized by comprising a computer mainboard, wherein the computer mainboard is provided with a PCIE interface; the Ethernet Cat main station comprises an FPGA and a CH368L interface chip, the FPGA is connected to a PCIE bus through the CH368L interface chip, and the PCIE bus is connected with the PCIE interface and enters the computer mainboard; the CH368L interface chip controls the FPGA.

In certain embodiments, the FPGA is model 10M08SCU169 (PD).

In some embodiments, address pins of local-bus-addr [0] - [15] on the CH368L interface chip are connected to corresponding pins of the FPGA.

In some embodiments, the local-bus-data [0] - [31] data pins on the CH368L interface chip are connected to corresponding pins of the FPGA.

In some embodiments, the mem-read and mem-write pins on the CH368L interface chip are respectively connected with corresponding pins of the FPGA, so as to realize the read-write control of the CH368L interface chip on the FPGA.

In some embodiments, the apparatus further comprises a crystal oscillator, wherein a VCC pin of the crystal oscillator is connected with a VCC-3V3 pin of the FPGA, and the crystal oscillator further provides a clock control pin of the CLKIN SYS for the FPGA.

In some embodiments, the crystal oscillator has a model number SIT1602B1-2133N 25.

Compared with the prior art, the application has the following beneficial effects:

the application realizes an Ethercat protocol by using the FPGA, and the FPGA is connected to a PCIE bus through an interface chip CH386L and then enters a computer mainboard. Because the PCIE bus has high speed and good real-time performance, the application also adopts CH386L to control the FPGA, so that the receiving and sending of real-time data can be completed, and the strong real-time performance of the data can be realized and ensured from a hardware level.

Drawings

In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic structural diagram of a high-instantaneity EtherCAT hardware master station system according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a high-instantaneity EtherCAT hardware master station system according to an embodiment of the present application;

fig. 3 is a schematic circuit structure diagram of a crystal oscillator in the high-real-time EtherCAT hardware master station system according to the embodiment of the present application;

fig. 4 is a local connection diagram of an FPGA in the high-real-time EtherCAT hardware master station system according to the embodiment of the present application;

fig. 5 is a local connection diagram of an FPGA in the high-real-time EtherCAT hardware master station system according to the embodiment of the present application;

fig. 6 is a local connection diagram of an FPGA in the high-real-time EtherCAT hardware master station system according to the embodiment of the present application;

fig. 7 is a local connection diagram of an FPGA in the high-real-time EtherCAT hardware master station system according to the embodiment of the present application;

fig. 8 is a local connection diagram between an FPGA and a CH368L in the high real-time EtherCAT hardware master station system according to the embodiment of the present application;

fig. 9 is a local connection diagram between an FPGA and CH368L in the high-real-time EtherCAT hardware master station system according to the embodiment of the present application.

Wherein, the computer mainboard 1; a PCIE interface 101; EtherCAT Master station 2; CH368L interface chip 201; an FPGA module 202; a PCIE bus 3; a power supply module 4; an ethernet physical layer transceiver 5.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are illustrative of some, but not all embodiments of the invention, and are not to be construed as limiting the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it should be noted that the terms "upper", "lower", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the elements referred to must have a specific orientation or be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and may be used for purposes of simplicity in more clearly distinguishing between different components and are not to be construed as indicating or implying relative importance.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

In addition, in the technical solutions of the present application, the technical solutions can be implemented by adopting conventional means in the art, unless otherwise specified.

As shown in fig. 1 to 9, a high real-time EtherCAT hardware master station system is provided.

As shown in fig. 1 and fig. 2, the high-instantaneity EtherCAT hardware master station system includes a computer motherboard 1, where the computer motherboard is provided with a PCIE interface; the Ethernet Cat main station comprises an FPGA and a CH368L interface chip, the FPGA is connected to a PCIE bus through the CH368L interface chip, and the PCIE bus is connected with the PCIE interface and enters the computer mainboard; the CH368L interface chip controls the FPGA, and the power module 4 supplies power to the computer mainboard 1. The application realizes an Ethercat protocol by using the FPGA, and the FPGA is connected to a PCIE bus through an interface chip CH386L and then enters a computer mainboard. Because the PCIE bus has high speed and good real-time performance, the application also adopts CH386L to control the FPGA, so that the receiving and sending of real-time data can be completed, and the strong real-time performance of the data can be realized and ensured from a hardware level.

For example, as shown in fig. 2-9, the model number of the FPGA is 10M08SCU169 (PD). And local-bus-addr [0] - [15] address pins on the CH368L interface chip are respectively connected with corresponding pins of the FPGA. Meanwhile, the data pin of local-bus-data [0] - [31] on the CH368L interface chip is connected with the corresponding pin of the FPGA. For convenience of explanation, the address pins of local-bus-addr [0] - [15] are denoted by A0-A15 in this application, respectively. The local-bus-data [0] - [31] data pins are represented by D0-D31 in the figures, and particularly, as can be seen from FIGS. 4 and 5, pins A0-A15 of the CH368L interface chip are connected with pins A0-A15 of the FPGA, and pins D0-D31 of the CH368L interface chip are connected with pins D0-D31 of the FPGA.

The application supports I/O port mapping, memory mapping, expansion ROM and interrupt by adopting a CH368L interface chip to be connected with a PCI-E bus. The CH368L interface chip can convert the high-speed PCIE bus into a simple and easy-to-use 32-bit active parallel interface similar to an ISA bus, and meanwhile, compared with other mainstream buses, the PCIE bus has the advantages of higher speed, better real-time performance and better controllability, and further can be realized from a hardware level and ensure the strong real-time performance of data.

In some embodiments, the MEM-read and MEM-write pins on the CH368L interface chip are respectively connected to corresponding pins of the FPGA, and as can be seen from fig. 4 to 9, in this embodiment, the MEM-read and MEM-write pins on the CH368L interface chip are simplified and denoted as MEM _ WR and MEM _ RD, so as to implement read-write control of the CH368L interface chip on the FPGA.

In some embodiments, the FPGA further comprises a crystal oscillator, a VCC pin of the crystal oscillator is connected to a VCC-3V3 pin of the FPGA, and the crystal oscillator further provides a clock control pin of a CLKIN SYS for the FPGA, that is, a clock input of 25 MHz. The model of the crystal oscillator is SIT1602BI-2133N 25.

The crystal oscillator can provide signals with highly stable frequency for the system, and further ensures the high stability of the signals.

The above embodiments of the present application are only used for illustrating the technical solutions of the present application, and not for limiting the same, it should be understood that, for those skilled in the art, modifications or substitutions can be made on the basis of the above description without departing from the inventive concept of the present application, and all such modifications and substitutions shall fall within the protection scope of the appended claims of the present application. In this case all the details may be replaced with equivalent elements, and the materials, shapes and dimensions may be any.

Claims (7)

1. High real-time EtherCAT hardware main station system, which is characterized by comprising

The computer comprises a computer mainboard, wherein the computer mainboard is provided with a PCIE interface;

the Ethernet Cat main station comprises an FPGA and a CH368L interface chip, the FPGA is connected to a PCIE bus through the CH368L interface chip, and the PCIE bus is connected with the PCIE interface and enters the computer mainboard; the CH368L interface chip controls the FPGA.

2. The EtherCAT hardware master station system with high real-time performance according to claim 1, wherein the model of the FPGA is 10M08SCU169 (PD).

3. The EtherCAT hardware master station system with high real-time performance according to claim 2, characterized in that the address pins of local-bus-addr [0] - [15] on the CH368L interface chip are respectively connected with the corresponding pins of the FPGA.

4. The system of claim 3, wherein the local-bus-data [0] - [31] data pins on the CH368L interface chip are connected to corresponding pins of the FPGA.

5. The high-instantaneity EtherCAT hardware master station system according to claim 3, characterized in that the mem-read and mem-write pins on the CH368L interface chip are respectively connected with corresponding pins of the FPGA, so as to realize the read-write control of the CH368L interface chip on the FPGA.

6. The high-instantaneity EtherCAT hardware master station system according to claim 3, further comprising a crystal oscillator, wherein a VCC pin of the crystal oscillator is connected to a VCC-3V3 pin of the FPGA, and the crystal oscillator further provides a clock control pin of CLKIN SYS for the FPGA.

7. The system of claim 6, wherein the crystal oscillator is SIT1602B1-2133N 25.

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