CN212137851U

CN212137851U - Video output device supporting HEVC decoding

Info

Publication number: CN212137851U
Application number: CN202020312880.7U
Authority: CN
Inventors: 汤志敏; 李伟; 杨雪松
Original assignee: WELLAV TECHNOLOGIES Ltd
Current assignee: WELLAV TECHNOLOGIES Ltd
Priority date: 2020-03-13
Filing date: 2020-03-13
Publication date: 2020-12-11
Anticipated expiration: 2030-03-13

Abstract

The application discloses video output equipment supporting HEVC decoding, which is characterized by comprising a TS stream input interface, a TS stream output interface and a video output interface, wherein the TS stream input interface is used for being connected with a TS stream data transmission line; the HEVC decoding module is connected with the TS stream input interface and is used for HEVC decoding of the TS stream to obtain YUV data; and the video output module comprises an SDI output component and an IP output component, and is used for outputting the video data through the SDI output component or the IP output component after the YUV data is processed. After YUV data is processed by a video output module provided with an SDI output assembly and an IP output assembly, two common transmission format files can be output so as to be convenient for playing different devices; and the decoded YUV data can be packaged by self according to the customer requirements so as to meet the playing requirements of more devices.

Description

Video output device supporting HEVC decoding

Technical Field

The application relates to the field of electronic detection, in particular to video output equipment supporting HEVC decoding.

Background

Hevc (high Efficiency Video coding) is an efficient Video compression standard. The HEVC standard retains some original technologies on the basis of the video coding standard h.264, improves some related technologies, and uses advanced technologies to improve the relationship between the code stream, the coding quality, the delay, and the algorithm complexity, thereby achieving the optimal setting. Compared with h.264, HEVC provides a data compression ratio that is doubled at the same level of video quality, or improves video quality at the same bit rate by a large amount, which means that the quality of video content will increase by a lot and a large amount of network bandwidth can be saved.

The existing video output equipment generally receives a video format of the HEVC standard, adopts hardware to decode and then directly outputs the video format, and a client can play a file of the video format only through specific playing equipment. However, since the playing devices on the market are all five-door, the output video format is fixed, so that the video output device cannot meet the playing requirements of each playing device, the compatibility is poor, and different requirements of customers cannot be met at the same time.

SUMMERY OF THE UTILITY MODEL

The application provides a video output device supporting HEVC decoding, which can improve the compatibility of output videos.

The video output apparatus includes:

the TS flow input interface is used for connecting with a TS flow data transmission line;

the HEVC decoding module is connected with the TS stream input interface and is used for HEVC decoding of the TS stream to obtain YUV data; and

and the video output module comprises an SDI output component and an IP output component, and is used for outputting video data through the SDI output component or the IP output component after the YUV data is processed.

Optionally, the HEVC decoding module includes:

the HEVC decoder is used for carrying out protocol decoding and decapsulation on the TS data and calling an HEVC encoding and decoding library stored in the memory to decode the data into YUV data; and

and the memory is electrically connected with the HEVC decoder and stores the HEVC coding and decoding library.

Optionally, the SDI output component includes a decklik SDI processing module and an SDI output interface;

and the output end of the decklik SDI processing module is connected with the SDI output interface and used for outputting video data through the SDI output interface after the YUV data are packaged into the video data conforming to the SDI protocol.

Optionally, the IP output component includes a Matrox IP processing module and an IP output interface;

and the output end of the Matrox IP processing module is connected with the IP output interface and is used for outputting video data through the IP output interface after the YUV data is packaged into the video data conforming to the IP protocol.

Optionally, the video data conforming to the IP protocol is data in the SMPTE2110 format.

As can be seen from the above, in the video output device supporting HEVC decoding in the present application, YUV data is obtained by decoding TS stream data input from a TS stream input interface by using an HEVC decoding module, and after the YUV data is processed by using a video output module provided with an SDI output component and an IP output component, two common transmission format files can be output, so as to facilitate playing of different devices; and the decoded YUV data can be packaged by self according to the customer requirements so as to meet the playing requirements of more devices.

Drawings

Fig. 1 is a schematic structural diagram of a video output device supporting HEVC decoding according to an embodiment of the present disclosure.

Fig. 2 is a schematic structural diagram of an HEVC decoding module provided in an embodiment of the present application.

Fig. 3 is a schematic structural diagram of a video output module according to an embodiment of the present application.

Detailed Description

The following detailed description of the preferred embodiments of the present application, taken in conjunction with the accompanying drawings, will make the advantages and features of the present application more readily appreciated by those skilled in the art, and thus will more clearly define the scope of the invention.

Referring to fig. 1, a structure of a video output device supporting HEVC decoding according to an embodiment of the present application is shown.

As shown in fig. 1, the video output device supporting HEVC decoding includes a TS stream input interface 1, an HEVC decoding module 2, and a video output module 3.

The TS stream input interface 1 is used for connecting with a TS stream data transmission line, which may be a common television signal transmission line for transmitting TS stream data. The TS stream input interface 1 may be an SDI, ASI or IP interface, or other TS stream transmission interfaces commonly used in the art.

HEVC decoding module 2 may employ a general-purpose processor, such as a CPU (Central Processing Unit), or employ other forms of decoding chipsets. By the HEVC decoding module 2, the input HEVC format video based on TS streaming can be decoded into corresponding YUV data.

In one embodiment, the HEVC decoding module 2 performs the deprotocolation and decapsulation operations and then performs the video decoding, wherein the HEVC decoding module 2 mainly decodes the video NALU data into the original YUV data by calling the audio/video codec library FFMPEG API of the third party.

The HEVC decoding module 2 may perform decoding operation by hardware decoding or other software decoding after performing protocol interfacing and decapsulation on HEVC-formatted video transmitted by TS stream.

The video output module 3 includes an SDI output module 31 and an IP output module 32, so as to output the video data after the YUV data is processed by the SDI output module 31 or the IP output module 32.

Wherein, before output through the SDI output component 31 and/or the IP output component 32, video format adjustment can be performed on the YUV data through the SDI output component 31 and/or the IP output component 32, wherein the video format is determined according to parameters set by a user.

For example, if the IP output component 32 is adopted to output video data, the IP output component 32 encapsulates the decoded YUV data to cooperate with the IP transport protocol to obtain a playing device suitable for the IP input signal source after being re-encapsulated, so that the video output device is compatible with the playing device suitable for the IP input signal source.

If the parameters of the video format, such as the resolution and the code rate of the video, need to be adjusted, the IP output component 32 may perform encapsulation to obtain video data meeting the parameters based on the setting of the parameters. Because the HEVC decoding module 2 outputs YUV data, it is also convenient for the IP output component 32 to adjust the video data, and further convenient for compatibility with different playing devices.

As can be seen from the above, in the video output device supporting HEVC decoding in the present application, data of a TS stream input from a TS stream input interface 1 is decoded by an HEVC decoding module 2 to obtain YUV data, and after the YUV data is processed by a video output module 3 provided with an SDI output component 31 and an IP output component 32, two common transmission format files can be output, so as to facilitate playing of different devices; and the decoded YUV data can be packaged by self according to the customer requirements so as to meet the playing requirements of more devices.

Referring to fig. 2, a structure of an HEVC decoding module 2 provided by an embodiment of the present application is shown.

The HEVC decoding module 2 may include an HEVC decoder 21 and a memory 22 connected to the HEVC.

Specifically, the HEVC decoder 21 is configured to deproplex and decapsulate the TS data, and call the HEVC codec library stored in the memory 22 to decode the data into YUV data. The memory 22 stores an HEVC codec library.

In an embodiment, the memory 22 may store the audio/video codec library FFMPEG API, and in addition, other audio/video codec libraries may be provided to the HEVC decoder 21, so as to implement a software decoding operation on HEVC by the HEVC decoder 21, and obtain original YUV data.

In an embodiment, the HEVC decoder 21 may use a CPU processor of a general-purpose computer as the HEVC decoder 21, for example, a general-purpose processor of intel or AMD, and a specific peripheral circuit structure thereof may be implemented by a scheme commonly used in the art. It is understood that the specific model of the HEVC decoder 21 may also adopt other models that are commonly available in the art and can perform HEVC data decoding, and the difference between the models does not affect the implementation of the embodiments of this application.

The YUV data output by the software decoding mode can be output after the video format is adjusted by the video output module 3, so that the video output device is convenient to adapt to playing devices with different playing specifications, and the compatibility of the video output device is improved.

Referring to fig. 3, a structure of a video output module 3 according to an embodiment of the present disclosure is shown.

The video output module 3 includes an SDI output component 31 and an IP output component 32.

In one embodiment, the SDI output component 31 includes a decklik SDI processing module 311 and an SDI output interface 312. An output end of the decklik SDI processing module 311 is connected to the SDI output interface 312, and is configured to package the YUV data into video data conforming to the SDI protocol, and output the video data through the SDI output interface 312.

Specifically, the decklik SDI processing module 311 may output video data through the SDI output interface 312 after repackaging and format adjusting the YUV data based on the setting information, so as to facilitate connection of a playing device having an SDI protocol interface with the video output device, and obtain corresponding video data.

The IP output module 32 includes a Matrox IP processing module 321 and an IP output interface 322. The output end of the Matrox IP processing module 321 is connected to the IP output interface 322, and is configured to package the YUV data into video data conforming to the IP protocol, and output the video data through the IP output interface 322.

Specifically, the Matrox IP processing module 321 may encapsulate and format-adjust the YUV data based on the setting information, and then output the video data through the IP output interface 322, so as to facilitate connection between the playing device having the IP protocol interface and the video output device, and obtain the corresponding video data.

It should be noted that the above embodiments are all examples in the present application, the hardware models specifically adopted by the SDI output component 31 and the IP output component 32 may be hardware models common in the art, and the differences between the models do not affect the implementation of the embodiments in the present application.

The video output module 3 adopts a combined output mode of the SDI output component 31 and the IP output component 32, can perform format adjustment and processing on the original YUV data according to the needs of the client, and then outputs the video data to the playing device through the corresponding SDI output interface 312 and/or the IP output interface 322. This can further improve the compatibility of the video output device.

The embodiments of the present application have been described in detail with reference to the drawings, but the present application is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present application within the knowledge of those skilled in the art.

Claims

1. A video output device supporting HEVC decoding, the video output device comprising:

2. The video output device supporting HEVC decoding according to claim 1, wherein said HEVC decoding module comprises:

3. A video output device supporting HEVC decoding according to claim 1 wherein:

the SDI output assembly comprises a decklik SDI processing module and an SDI output interface;

4. A video output device supporting HEVC decoding according to claim 1 wherein:

the IP output component comprises a Matrox IP processing module and an IP output interface;

5. The video output device capable of HEVC decoding according to claim 4, wherein the video data compliant with the IP protocol is SMPTE2110 formatted data.