CN211879369U - Chip packaging structure and electronic equipment - Google Patents
Chip packaging structure and electronic equipment Download PDFInfo
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- CN211879369U CN211879369U CN202020890865.0U CN202020890865U CN211879369U CN 211879369 U CN211879369 U CN 211879369U CN 202020890865 U CN202020890865 U CN 202020890865U CN 211879369 U CN211879369 U CN 211879369U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- Condensed Matter Physics & Semiconductors (AREA)
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model discloses a chip package structure and electronic equipment belongs to semiconductor chip encapsulation test technical field. The chip packaging structure comprises: a package substrate having a first surface and a second surface disposed opposite to each other; the chip is arranged inside the packaging substrate and provided with a third surface and a fourth surface which are oppositely arranged, and a chip pin is arranged on the third surface; and the heat dissipation structure is arranged in the packaging substrate, is positioned on the fourth surface of the chip, exposes the surface of one side of the heat dissipation structure, which is far away from the chip, on the second surface of the packaging substrate, and is used for providing a heat dissipation channel for the chip. The technical scheme of the utility model, it can increase chip package's heat dissipation channel, effectively improves chip package's heat-sinking capability, reduces chip package's thermal resistance to improve chip package's consumption.
Description
Technical Field
The embodiment of the disclosure relates to the technical field of semiconductor chip packaging test, in particular to a chip packaging structure and electronic equipment.
Background
Today, the rapid development of semiconductor packaging technology, miniaturization, and high integration of devices have become mainstream of development. The continuous evolution of System On Chip (SOC), package level System (SIP), and more functions are integrated in a single package, so that the power consumption of the single package is continuously increased; on the other hand, due to the constraints of cost and system volume, the size of a single package is required to be continuously reduced, so that the volume power consumption density of the package structure is higher and higher, the internal structure of the package structure is more and more complex, multiple materials are mutually stacked, the heat conduction path of a chip is complicated, and great challenges are brought to package heat dissipation.
In recent years, embedded Chip packages ecp (embedded Chip package) have been developed, in which a Chip, a resistor, and a capacitor are embedded in a substrate, and Chip pins are interconnected with the resistor, the capacitor, and the substrate by a redistribution layer (RDL) method. The packaging method has the advantages that the integration level can be further increased, the packaging thickness can be reduced, and the packaging method is suitable for systems (such as handheld devices like mobile phones) with high requirements on the thickness.
However, in the Embedded Chip Package (ECP) structure, heat generated by the chip located inside the substrate during use cannot be dissipated well, which results in a decrease in heat dissipation capability of the chip package and limits improvement of chip power consumption.
SUMMERY OF THE UTILITY MODEL
The disclosed embodiments provide a chip package structure and an electronic device, which are capable of effectively increasing a heat dissipation channel of a chip package, effectively improving a heat dissipation capability of the chip package, and reducing a thermal resistance of the chip package.
In order to achieve the above object, an embodiment of the present disclosure provides a chip package structure, where the chip package structure includes: a package substrate having a first surface and a second surface disposed opposite to each other; the chip is arranged inside the packaging substrate and provided with a third surface and a fourth surface which are oppositely arranged, and a chip pin is arranged on the third surface; and the heat dissipation structure is arranged in the packaging substrate, is positioned on the fourth surface of the chip, exposes the surface of one side of the heat dissipation structure, which is far away from the chip, on the second surface of the packaging substrate, and is used for providing a heat dissipation channel for the chip.
In order to achieve the above object, an embodiment of the present disclosure provides an electronic device, where the electronic device includes a circuit board and the chip package structure, and the circuit board is electrically connected to the chip in the chip package structure.
The chip packaging structure and the electronic device provided by the embodiment of the disclosure adopt an Embedded Chip Package (ECP) mode, and the surface of one side of the chip is provided with the heat dissipation structure, so that a heat dissipation channel is provided for the chip, heat generated by the chip can be well dissipated, and in practical application, the heat dissipation structure can conduct the heat generated by the chip to an external circuit board. The embodiment can effectively increase the heat dissipation channel of the chip package, improve the heat dissipation capacity of the chip package, and reduce the thermal resistance of the chip package, thereby effectively improving the power consumption of the chip, and improving the performance and the service life of the chip.
Drawings
Fig. 1 is a schematic structural diagram of a chip package structure according to an embodiment of the disclosure;
fig. 2 is a schematic structural diagram of a chip package structure according to a second embodiment of the disclosure.
Detailed Description
In order to make those skilled in the art better understand the technical solutions of the embodiments of the present disclosure, the following describes in detail a chip package structure and an electronic device provided in the embodiments of the present disclosure with reference to the drawings.
The accompanying drawings, which are included to provide a further understanding of the embodiments of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure and not to limit the disclosure.
Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, but which may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Embodiments of the present disclosure and features of embodiments may be combined with each other without conflict.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, "first," "second," and similar words do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Similarly, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
Embodiments described herein may be described with reference to plan and/or cross-sectional views in light of idealized schematic illustrations of the disclosure. Accordingly, the example illustrations can be modified in accordance with manufacturing techniques and/or tolerances. Accordingly, the embodiments are not limited to the embodiments shown in the drawings, but include modifications of configurations formed based on a manufacturing process. Thus, the regions illustrated in the figures have schematic properties, and the shapes of the regions shown in the figures illustrate specific shapes of regions of elements, but are not intended to be limiting.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Example one
As shown in fig. 1, the present embodiment provides a chip package structure, which includes: a package substrate 101, the package substrate 101 having a first surface S1 and a second surface S2 oppositely disposed; at least one Chip (Chip)102, the Chip 102 being disposed inside the package substrate 101, the Chip 102 having a third surface S3 and a fourth surface S4 opposite to each other, the third surface (active surface) S3 having Chip pins 103 thereon; the heat dissipation structure 104 is disposed inside the package substrate 101, located on the fourth surface (inactive surface) S4 of the chip 102, and exposed at the second surface S2 of the package substrate 101 on a side surface thereof away from the chip 102, and is used for providing a heat dissipation channel for the chip 102.
The chip packaging structure provided by the embodiment adopts an Embedded Chip Package (ECP) mode, and the heat dissipation structure is arranged on the surface of one side of the chip, so that a heat dissipation channel is provided for the chip, heat generated by the chip can be well dissipated, and in practical application, the heat dissipation structure can conduct the heat generated by the chip to an external circuit board. The embodiment can effectively increase the heat dissipation channel of the chip package and reduce the thermal resistance of the chip package, thereby effectively improving the power consumption of the chip, and improving the performance and the service life of the chip.
In this embodiment, the package substrate 101 may be a substrate made of an organic material, or may be a substrate made of another composite material.
In this embodiment, the chip 103 is an integrated circuit chip, which may be a chip in any implementation form, and this embodiment is not limited thereto.
In this embodiment, the heat dissipation structures 104 may be disposed in one-to-one correspondence with the chips 102, and the number of the heat dissipation structures 104 may also be less than that of the chips 102, which is not limited in this embodiment. The heat dissipation structure 104 may cover the fourth surface S4 of the corresponding chip 102, or may cover a part of the surface of the fourth surface S4 of the corresponding chip 102. The shape of the heat dissipation structure 104 may be a sheet, the heat dissipation structure 104 may be a metal copper sheet, and the heat dissipation structure 104 may also be a structure made of other heat dissipation materials, which is not limited in this embodiment.
In the present embodiment, as shown in fig. 1, a surface of the heat dissipation structure 104 away from the chip 102 may be flush with the second surface S2 of the package substrate 101.
In this embodiment, as shown in fig. 1, a first metal Trace (Trace)105 is disposed on the first surface S1 of the package substrate 101, the first metal Trace 105 is correspondingly connected to a chip pin 103 on the chip 102, the chip 102 is electrically connected to the first metal Trace 105 through the chip pin 103, the chip pin 103 is used for providing an external signal path for the chip 102, and the chip can transmit a signal to an external device, an apparatus, and the like through the chip pin 102 and the first metal Trace 105. The number of the chip pins 103 of the chip 102 may be multiple, and correspondingly, the number of the first metal traces 105 may be multiple. In this embodiment, the first metal trace 105 can also provide a heat dissipation channel for the chip 102 to conduct heat generated by the chip 102. The first metal trace 105 may be made of a copper material, or may be made of other suitable metal materials.
In the present embodiment, as shown in fig. 1, the first solder resist layer 106 is disposed on the first surface S1 of the package substrate 101, and the first solder resist layer 106 may be disposed to cover the first surface S1. For some components, such as inductors or other components, of which the chips 102 need to be connected, have a large volume, and are not conveniently embedded in the package substrate 101, a connection interface corresponding to the chips 102 needs to be reserved on the package substrate 101, therefore, in this embodiment, for a portion of the first metal trace 105, which needs to be connected to an external component, a first window 107a is disposed on the first solder mask layer 106 at a position corresponding to the portion of the first metal trace 105, so as to expose a portion of the first metal trace 105 corresponding to the first window 107a, a first metal Pad (Pad)107 connected to the corresponding first metal trace 105 is disposed in the first window 107a, and the first metal Pad 107 is used for connecting an external component, such as an inductor or other components. The connection end of the external component is soldered to the first metal pad 107, so that the external component can be electrically connected to the chip 102, and signal interconnection between the external component and the chip 102 is realized. The material of the first metal pad 107 may be a silver-tin alloy material, and may also be other suitable metal materials.
In this embodiment, in order to realize the electrical connection between the chip 102 inside the package substrate 101 and the external circuit board, as shown in fig. 1, a second metal Trace (Trace)108 is disposed on the second surface S2 of the package substrate 101, the second metal Trace 108 is disposed corresponding to a portion of the first metal Trace 105, a through hole H is disposed between the first surface S1 and the second surface S2, the second metal Trace 108 is connected to the corresponding first metal Trace 105 through the through hole H, and the second metal Trace 108 is used for connecting an external circuit board (not shown), such as a Printed Circuit Board (PCB), so as to realize the electrical connection between the chip 102 and the external circuit board. The material of the second metal trace 108 is the same as that of the first metal trace 105, and the through hole H is filled with the material of the first metal trace 105, so that the second metal trace 108 is connected to the corresponding first metal trace 105. In this embodiment, the second metal traces 108 can also provide a heat dissipation channel for the chip 102, so as to conduct heat generated by the chip 102 to the external circuit board for heat dissipation.
In this embodiment, the number of the vias H between the second metal trace 108 and the corresponding first metal trace 105 may be one or more, and fig. 1 only exemplarily shows that the number of the vias H between the second metal trace 108 and the corresponding first metal trace 105 is two, which includes but is not limited to this, for example, the number of the vias H between the second metal trace 108 and the corresponding first metal trace 105 may also be one.
In the present embodiment, as shown in fig. 1, the second solder resist layer 109 is disposed on the second surface S2 of the package substrate 101, and the second solder resist layer 109 may be disposed to cover the second surface S2. In order to realize the connection between the second metal trace 108 and the external circuit board, a second window 110a is disposed on the second solder mask layer 109 at a position corresponding to the second metal trace 108, so that a portion of the second metal trace 108 corresponding to the second window 110a is exposed, a second metal pad 110 connected to the corresponding second metal trace 108 is disposed in the second window 110a, and the second metal pad 110 is used for connecting the external circuit board. The second metal pad 110 is welded on the external circuit board and electrically connected with the external circuit board, so that the external circuit board is electrically connected with the second metal wire 108, the chip 102 is electrically connected with the external circuit board, and the signal interconnection between the external circuit board and the chip 102 is realized. Wherein the material of the second metal pad 110 is the same as the material of the first metal pad 107.
In this embodiment, as shown in fig. 1, at least one third opening window 111a is disposed on the second solder mask 109 at a position corresponding to the heat dissipation structure 104, so that a portion of the heat dissipation structure 104 corresponding to the third opening window 111a is exposed, a third metal pad 111 connected to the corresponding heat dissipation structure 104 is disposed in the third opening window 111a, and the third metal pad 111 is used for connecting an external circuit board (not shown in the figure). The third metal pad 111 is soldered on the external circuit board and thermally connected to the external circuit board, so that heat generated by the operation of the chip 102 is conducted to the external circuit board for heat dissipation. The material of the third metal pad 111 is the same as the material of the first metal pad 107 and the second metal pad 110. It should be noted that fig. 1 exemplarily shows a case where one third opening window 111a is disposed on the second solder resist layer 109, but the embodiment includes but is not limited thereto, and the number of the third opening windows 111a may also be multiple.
In this embodiment, as shown in fig. 1, the chip package structure further includes one or more first passive elements 112, the one or more first passive elements 112 may include passive elements required for a capacitor element, a resistor element, and the like, and since the volume of the passive elements is small and is convenient to embed in the package substrate 101, the first passive element 112 may be disposed in the package substrate 101, and the first passive element 112 is electrically connected to the chip 102 through the first metal trace 105. In order to realize the functions of signal storage, buffering, etc. in the signal transmission process, the chip 102 needs to be connected with some passive components having these functions, and in order to improve the integration level of the chip package, in this embodiment, one or more first passive components 112 are integrated inside the package substrate 101 and electrically connected with the chip 102 inside the package substrate 101. It should be noted that fig. 1 only exemplarily shows a case where two first passive elements 112 are included, the present embodiment includes but is not limited to this, and the chip package structure may further include 1 or more first passive elements 112.
In this embodiment, as shown in fig. 1, the chip package structure further includes one or more second passive elements 113, the one or more second passive elements 113 may include an inductive element or other required elements, and the second passive elements 113 are not easily embedded in the package substrate 101 due to their large size or other factors, and thus the second passive elements 113 need to be disposed outside the package substrate 101. Specifically, the second passive component 113 is disposed on the first solder mask layer 106, and the second passive component 113 is connected to the first metal pad 107. By soldering the second passive element 113 to the first metal pad 107, the second passive element 113 disposed outside the package substrate 101 can be electrically connected to the chip 102 inside the package substrate. It should be noted that fig. 1 only exemplarily shows a case where one second passive element 113 is included, the present embodiment includes but is not limited to this, and the chip package structure may further include more second passive elements 1123.
In this embodiment, the first passive element 112, the chip 102, and the heat dissipation structure 104 providing a heat dissipation channel are integrated into the package substrate 101, so as to effectively reduce the package volume and weight, reduce the package complexity, improve the integration of chip package, and facilitate mass production. Meanwhile, for components which are not conveniently buried inside the package substrate 101, by providing the first metal pads 107 connected to the first metal traces 105 on the first surface S1 of the package substrate 101, the first metal pads 107 can be used to connect components outside the package substrate 101, such as inductors or other required components, and by providing the second metal pads 108 connected to the second metal traces 108 and the third metal pads 111 connected to the heat dissipation structure 104 on the second surface S2 opposite to the first surface S1, the second metal pads 108 and the third metal pads 111 can be used to connect external circuit boards, such as PCB boards, further improving the integration level of chip packaging and effectively reducing the size of the external circuit boards.
Example two
As shown in fig. 2, the present embodiment provides another chip package structure, which is different from the chip package structure provided in the first embodiment, in that the chip package structure of the present embodiment further includes a heat conducting connection structure 114, the heat conducting connection structure 114 is located between the heat dissipation structure 104 and the fourth surface S4 of the chip 102, and the heat dissipation structure 104 is soldered to the fourth surface S4 of the chip 102 through the heat conducting connection structure 114. Wherein heat generated by the operation of the chip 102 can be conducted to the heat dissipation structure 104 through the thermally conductive connection structure 114.
One side surface of the heat dissipation structure 104 close to the fourth surface S4, the heat conductive connection structure 114, and the fourth surface S4 of the chip 102 may be soldered by reflow soldering. The reflow soldering method among the chip, the heat conductive connection structure and the heat dissipation structure is a technique that is easy to be thought by the skilled person, and is not described herein again.
The heat conducting connection structure 114 may be an indium metal sheet, and the heat conducting connection structure 114 may also be made of other metal materials, which is not limited in this embodiment.
This embodiment is through setting up heat conduction connection structure between the fourth surface at heat radiation structure and chip, can make heat radiation structure easily weld on the chip to guarantee heat radiation structure's heat-sinking capability.
In addition, for other relevant descriptions of the chip package structure provided by the present embodiment, reference may be made to the description of the first embodiment, and further description is omitted here.
EXAMPLE III
The embodiment provides an electronic device, which comprises a circuit board and a chip packaging structure, wherein the circuit board is electrically connected with a chip in the chip packaging structure. The chip package structure provided in any of the foregoing embodiments is adopted, and for specific description of the chip package structure, reference may be made to the description of any of the foregoing embodiments, and details are not repeated here. The circuit board may be a Printed Circuit Board (PCB).
Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted in a generic and descriptive sense only and not for purposes of limitation. In some instances, features, characteristics and/or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics and/or elements described in connection with other embodiments, unless expressly stated otherwise, as would be apparent to one skilled in the art. Accordingly, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the disclosure as set forth in the appended claims.
Claims (12)
1. A chip package structure, comprising:
a package substrate having a first surface and a second surface disposed opposite to each other;
the chip is arranged inside the packaging substrate and provided with a third surface and a fourth surface which are oppositely arranged, and a chip pin is arranged on the third surface;
and the heat dissipation structure is arranged in the packaging substrate, is positioned on the fourth surface of the chip, exposes the surface of one side of the heat dissipation structure, which is far away from the chip, on the second surface of the packaging substrate, and is used for providing a heat dissipation channel for the chip.
2. The chip package structure according to claim 1, further comprising a thermally conductive connection structure between the heat dissipation structure and the fourth surface, wherein the heat dissipation structure is soldered to the fourth surface of the chip through the thermally conductive connection structure.
3. The chip package structure according to claim 1, wherein the first surface is provided with a first metal trace correspondingly connected to the chip pin.
4. The chip packaging structure according to claim 3, further comprising a first solder mask covering the first surface, wherein a first window is disposed on the first solder mask at a position corresponding to a portion of the first metal trace, a first metal pad connected to the corresponding first metal trace is disposed in the first window, and the first metal pad is used for connecting an external device.
5. The chip package structure according to claim 3, wherein a second metal trace is disposed on the second surface and corresponds to a portion of the first metal trace, a through hole is disposed between the first surface and the second surface, and the second metal trace is connected to the corresponding first metal trace through the through hole.
6. The chip packaging structure according to claim 5, further comprising a second solder mask covering the second surface, wherein a second window is disposed on the second solder mask at a position corresponding to the second metal trace, a second metal pad connected to the corresponding second metal trace is disposed in the second window, and the second metal pad is used for connecting an external circuit board.
7. The chip packaging structure according to claim 6, wherein at least one third opening window is disposed on the second solder mask layer at a position corresponding to the heat dissipation structure, a third metal pad connected to the corresponding heat dissipation structure is disposed in the third opening window, and the third metal pad is used for connecting an external circuit board.
8. The chip package structure according to claim 3, further comprising one or more first passive elements, wherein the first passive elements are disposed inside the package substrate, and the first passive elements are electrically connected to the chip through the first metal traces.
9. The chip package structure according to claim 4, further comprising one or more second passive components disposed on the first solder mask layer, the second passive components being connected to the first metal pads.
10. The chip package structure according to claim 1, wherein the heat dissipation structure is a metal copper sheet.
11. The chip package structure according to claim 2, wherein the thermally conductive connecting structure is a metal indium plate.
12. An electronic device comprising a circuit board and the chip package structure of any one of claims 1-11, wherein the circuit board is electrically connected to the chip in the chip package structure.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020890865.0U CN211879369U (en) | 2020-05-25 | 2020-05-25 | Chip packaging structure and electronic equipment |
| PCT/CN2021/090553 WO2021238559A1 (en) | 2020-05-25 | 2021-04-28 | Chip package structure and electronic device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202020890865.0U CN211879369U (en) | 2020-05-25 | 2020-05-25 | Chip packaging structure and electronic equipment |
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| CN211879369U true CN211879369U (en) | 2020-11-06 |
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| WO (1) | WO2021238559A1 (en) |
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| CN112490845A (en) * | 2020-12-04 | 2021-03-12 | 华引芯（武汉）科技有限公司 | High heat dissipation laser device |
| CN112531456A (en) * | 2020-12-04 | 2021-03-19 | 华引芯（武汉）科技有限公司 | Manufacturing method of high-heat-dissipation laser device |
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| CN113035794A (en) * | 2021-02-01 | 2021-06-25 | 珠海越亚半导体股份有限公司 | Chip packaging structure manufacturing method and chip packaging structure |
| CN113130454A (en) * | 2021-04-12 | 2021-07-16 | 长沙新雷半导体科技有限公司 | Chip packaging device, electronic module and electronic equipment |
| WO2021238559A1 (en) * | 2020-05-25 | 2021-12-02 | 中兴通讯股份有限公司 | Chip package structure and electronic device |
| CN114334676A (en) * | 2021-12-22 | 2022-04-12 | 深圳市沃芯半导体技术有限公司 | Packaging method of power supply chip and corresponding packaging structure |
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| CN101221944A (en) * | 2007-01-09 | 2008-07-16 | 矽品精密工业股份有限公司 | Cooling type semiconductor packaging member |
| US8018037B2 (en) * | 2009-04-16 | 2011-09-13 | Mediatek Inc. | Semiconductor chip package |
| TW201218468A (en) * | 2010-10-26 | 2012-05-01 | Bridge Semiconductor Corp | Semiconductor chip assembly with bump/base heat spreader and cavity in bump |
| CN211879369U (en) * | 2020-05-25 | 2020-11-06 | 深圳市中兴微电子技术有限公司 | Chip packaging structure and electronic equipment |
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2020
- 2020-05-25 CN CN202020890865.0U patent/CN211879369U/en active Active
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2021
- 2021-04-28 WO PCT/CN2021/090553 patent/WO2021238559A1/en active Application Filing
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| CN112490845A (en) * | 2020-12-04 | 2021-03-12 | 华引芯（武汉）科技有限公司 | High heat dissipation laser device |
| CN112531456A (en) * | 2020-12-04 | 2021-03-19 | 华引芯（武汉）科技有限公司 | Manufacturing method of high-heat-dissipation laser device |
| CN112490845B (en) * | 2020-12-04 | 2021-10-22 | 华引芯（武汉）科技有限公司 | High heat dissipation laser device |
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| CN113035794A (en) * | 2021-02-01 | 2021-06-25 | 珠海越亚半导体股份有限公司 | Chip packaging structure manufacturing method and chip packaging structure |
| CN113035794B (en) * | 2021-02-01 | 2023-04-07 | 珠海越亚半导体股份有限公司 | Chip packaging structure manufacturing method and chip packaging structure |
| CN113130454A (en) * | 2021-04-12 | 2021-07-16 | 长沙新雷半导体科技有限公司 | Chip packaging device, electronic module and electronic equipment |
| US11942396B2 (en) | 2021-11-30 | 2024-03-26 | Industrial Technology Research Institute | Heterogeneous integration semiconductor package structure |
| CN114334676A (en) * | 2021-12-22 | 2022-04-12 | 深圳市沃芯半导体技术有限公司 | Packaging method of power supply chip and corresponding packaging structure |
| CN114334676B (en) * | 2021-12-22 | 2023-11-21 | 深圳市沃芯半导体技术有限公司 | Packaging method of power chip and corresponding packaging structure |
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