CN211669288U

CN211669288U - Power battery protection board test system

Info

Publication number: CN211669288U
Application number: CN201921854200.8U
Authority: CN
Inventors: 程忠光; 张猛
Original assignee: Shenzhen Hanchi Technology Co ltd
Current assignee: Shenzhen Hanchi Technology Co ltd
Priority date: 2019-10-30
Filing date: 2019-10-30
Publication date: 2020-10-13
Anticipated expiration: 2029-10-30

Abstract

The utility model relates to a power battery protection shield test system, including the main control board, the battery protection shield, electronic battery module to and sensor module. The main control panel comprises a main control chip, a main control chip peripheral circuit, an interface circuit, a signal processing circuit and a functional module circuit. The interface circuit comprises a CAN bus interface circuit with isolation, an SIP interface circuit with isolation, a USB interface circuit with isolation and a wireless WI-FI module. The main control board and the battery protection board communicate and transmit signals through the SPI and the I/O with isolation, and a configured battery management system is formed. Because the interface circuit can be interconnected with external equipment, the heterogeneous network has the characteristics. Meanwhile, due to the power circuit, the power detection circuit, the interface circuit, the signal processing circuit and the functional module circuit in the main control panel, the main control panel can be ensured to operate safely and stably, and the detection of a safe and stable operation state and the safety protection of a battery are achieved.

Description

Power battery protection board test system

[ technical field ] A method for producing a semiconductor device

The utility model relates to a power battery protection shield test system for battery field.

[ background of the invention ]

The three key technologies of the existing electric automobile are a battery, a motor and an electronic control system. Batteries are the key to the development of electric vehicles. However, the existing battery has many technical problems in the use of the electric vehicle, such as: when the battery is in use, the using amount state of the battery cannot be timely and accurately predicted and monitored, the technical problems of overcharge, overdischarge and overheating of the battery often occur, and the charging and discharging characteristics of the battery are easily influenced by environmental conditions. Therefore, how to make the battery play the most role becomes the core problem of the development of the electric vehicle. The key to solve the core problem of the development of the electric automobile is a battery management system. The battery management system is an important component of an electric vehicle, and the main functions of the battery management system are to monitor and estimate the state of a battery, protect the battery, manage the energy of the battery, and the like. The scientific and reasonable battery management system can not only ensure the safe and reliable operation of the battery, but also optimize and manage the energy of the battery and prolong the service life of the battery. The conventional battery management system is composed of a main control board and a battery protection board. Most of the existing battery management systems use batteries as core parts of electric vehicles, and manage and apply the operation of the electric vehicles. In this process, although the battery can be used safely, the battery parameters are measured and estimated. However, the battery cannot detect the operation state of the battery in the actual use process, and the battery is protected safely.

[ Utility model ] content

In view of this, the utility model aims to solve the technical problem that a power battery protection shield test system that has the characteristics of heterogeneous network, safety and stability running state's detection and battery safety protection is provided.

Therefore, the technical solution of the present invention is to provide a power battery protection board testing system, which includes a main control board, a battery protection board connected to the main control board, an electric battery module connected to the battery protection board, and a sensor module connected between the electric battery module and the main control board; the battery protection board is formed by cascading a plurality of battery management special chips; the main control panel comprises a main control chip, a main control chip peripheral circuit, an interface circuit, a signal processing circuit and a functional module circuit, wherein the main control chip peripheral circuit, the interface circuit, the signal processing circuit and the functional module circuit are respectively connected with the main control chip; the main control chip is composed of an F28M35x series multi-core single chip microcomputer MCU with the model number of F28M35H 22C; the peripheral circuit of the main control chip comprises a power supply circuit, a reset circuit, a crystal oscillator clock circuit and a simulation interface circuit; the power supply circuit comprises a voltage reduction circuit and a power supply detection circuit; the interface circuit comprises a CAN bus interface circuit with isolation, an SIP interface circuit with isolation, a USB interface circuit with isolation and a wireless WI-FI module; the signal processing circuit comprises a circuit signal acquisition circuit; the functional module circuit comprises a switching value signal processing circuit and an IC storage module circuit; the main control board and the battery protection board communicate and transmit signals through the SPI and the I/O with isolation, and a configured battery management system is formed.

Further limiting, the main control chip comprises a single chip microcomputer MCU, a UART interface, an SPI interface, a CAN interface, a USB interface, an IC interface, a GPIO interface, a first A/D interface and a first A/D interface which are respectively arranged in the single chip microcomputer MCU; the WI-FI module and the GPS module are respectively connected with the UART interface; the input/output interface is connected with the GPIO interface, the signal input conditioning module is connected with the first A/D interface, the voltage conversion and detection module is connected with the second A/D interface, and the voltage modules with different voltages are connected with the voltage conversion and detection module; the SPI isolation interface is connected with the SPI interface; the device comprises a CAN isolation interface connected with the CAN interface, a USB isolation interface connected with the USB interface, and an IC storage circuit connected with the IC interface.

Further, the reset circuit comprises a resistor R1, a reset control pin XRS and a reset control pin ARS which are connected to two ends of the resistor R1, a resistor R2 and a resistor R3 which are connected to one side of two ends of the resistor R1 in series, a capacitor C1 and a capacitor C2 which are connected to the other side of two ends of the resistor R1 in series, the resistor R2 is connected with a resistor R3 in parallel, the capacitor C1 is connected with a capacitor C2 in parallel, a resistor end and a voltage end are connected with each other, and a capacitor end is grounded; the reset control pin XRS controls the subsystem to reset, and the reset control pin ARS simulates the subsystem to reset.

Further, the crystal oscillator clock circuit comprises a crystal oscillator A1, a capacitor C3 connected in series with one side of two ends of a crystal oscillator A1, a capacitor C4, a pin X1 connected in series with the other side of two ends of a crystal oscillator A1, and a pin X2; the pin X1 and the pin X2 are respectively used for controlling and simulating the reset of the two subsystems, and the circuit with the model of F28M35H22C is realized through the pin X1, the pin X2 and an SSOSOC end; the operating frequency of up to 100MHz can be realized by the PLL configuration, and the chip can be provided with signals of 10MHz and 32KHz for the internal use of the chip.

Further, the simulation interface circuit is formed by a JTAG interface circuit of F28M35H22C, which includes a JTAG interface chip, a resistor R4, a resistor R5, a resistor R6, and a resistor R7, respectively connected to the JTAG interface chip.

Further, the voltage reduction circuit comprises a chip P15, a capacitor C5 connected between a pin 1 and a pin 8 of a chip P15, a capacitor C6 connected to a pin 2 of the chip P15, a capacitor C7, a resistor R8, a resistor R9 connected to a pin 4 of the chip P15, a resistor R10 connected between a pin 3 of the chip P15 and the resistor R9, a diode D1 connected between the pin 8 and a pin 7 of the chip P15, an inductor L1 connected to an output end of the diode D1, a capacitor C6 connected between the other end of the inductor L1 and an input end of the diode D1, a capacitor C7 connected to a pin 5 of the chip P15, a capacitor C8, a resistor R11, a resistor R11 connected in series with the capacitor C7, and a capacitor C8 connected between two ends of the resistor R11 and the capacitor C7; a resistor R12 and a resistor R13 connected to pin 5 of the chip P15, and a capacitor C9 connected to one end of the resistor R13.

Further, the power detection circuit comprises a voltage signal acquisition circuit and a voltage signal monitoring circuit; the voltage signal acquisition circuit comprises an operational amplifier U18, a resistor R14 connected to the output end of the operational amplifier U18, a resistor R15, a resistor R14 and a resistor R15 which are connected in series; the resistor R16, the resistor R17 and the capacitor C10 are connected to the positive input end of the operational amplifier U18, the resistor R16 is connected with the resistor R17 in series, and the capacitor C10 is connected with the positive input end of the operational amplifier U18 in parallel; a resistor R18, a resistor R19, a resistor R19 and a resistor R18 which are connected with the resistor R17 in series, and a capacitor C11 connected between the positive input terminal and the output terminal of the operational amplifier U18.

The utility model has the advantages of: the battery protection board is formed by cascading a plurality of battery management special chips; the main control panel comprises a main control chip, a main control chip peripheral circuit, an interface circuit, a signal processing circuit and a functional module circuit, wherein the main control chip peripheral circuit, the interface circuit, the signal processing circuit and the functional module circuit are respectively connected with the main control chip; the main control chip is composed of an F28M35x series multi-core single chip microcomputer MCU with the model number of F28M35H 22C; the peripheral circuit of the main control chip comprises a power supply circuit, a reset circuit, a crystal oscillator clock circuit and a simulation interface circuit; the power supply circuit comprises a voltage reduction circuit and a power supply detection circuit; the interface circuit comprises a CAN bus interface circuit with isolation, an SIP interface circuit with isolation, a USB interface circuit with isolation and a wireless WI-FI module; the signal processing circuit comprises a circuit signal acquisition circuit; the functional module circuit comprises a switching value signal processing circuit and an IC storage module circuit; the main control board and the battery protection board communicate and transmit signals through the SPI and the I/O with isolation, and a configured battery management system is formed. Because of interface circuit can with external equipment interconnect for the main control board can not only communicate with the battery protection shield, but also can realize with the communication between the various abundant equipment in the external world, has heterogeneous network's characteristics. Meanwhile, due to the power circuit, the power detection circuit, the interface circuit, the signal processing circuit and the functional module circuit inside the main control panel, the main control panel can be ensured to operate safely and stably, so that the main control panel can operate stably, and the system also has richer control functions, and achieves the purposes of safe and stable operation state detection and battery safety protection.

The technical solution of the present invention will be described in further detail with reference to the accompanying drawings and embodiments.

[ description of the drawings ]

Fig. 1 is a schematic block diagram of a test system for a power battery protection board according to the present invention;

FIG. 2 is a circuit diagram of the main control board of the present invention;

fig. 3 is a circuit diagram of the reset circuit of the present invention;

FIG. 4 is a circuit diagram of a crystal oscillator clock circuit according to the present invention;

fig. 5 is a circuit diagram of the middle emulation interface circuit of the present invention;

fig. 6 is a circuit diagram of the voltage step-down circuit of the present invention;

fig. 7 is a circuit diagram of the medium voltage signal acquisition circuit of the present invention;

[ detailed description ] embodiments

In order to make the technical problem, technical solution and advantageous effects to be solved by the present invention clearer and more obvious, the following description of the present invention with reference to the accompanying drawings and embodiments is provided for further details. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention.

Referring to fig. 1 to 7, a power battery protection board testing system including a main control board, a battery protection board connected to the main control board, an electric battery module connected to the battery protection board, and a sensor module connected between the electric battery module and the main control board is described below with reference to an embodiment.

The main control board is used for realizing a complex control algorithm and a multifunctional heterogeneous communication network, and the main control board and the battery protection board are communicated through the SPI and the I/O with isolation to realize the purposes of detecting and protecting the battery management system. The main control board and the battery protection board communicate and transmit signals through the SPI and the I/O with isolation, and a configured battery management system is formed.

The battery protection board is formed by cascading a plurality of battery management special chips. The main function of the battery protection board is to realize the monitoring and protection of multiple batteries. The model number of the battery management special chip is bq76PL 536A-Q1. The plurality of battery management dedicated chips are realized in a cascade form. The battery management chip is connected with the battery management chip through the SPI and the I/O, and the whole protection board is connected with the main control board through the isolated SPI and the I/O. The main control board can also communicate with battery management chips of all levels through SPI and I/O. The battery information, as measured by the battery management dedicated chip, may be communicated to the main control board through the strip isolation SPI. Each battery management chip can monitor and protect 6 batteries simultaneously, and each chip has the functions of balance control, voltage measurement, temperature measurement, battery protection and the like.

The main control panel comprises a main control chip, a main control chip peripheral circuit, an interface circuit, a signal processing circuit and a functional module circuit, wherein the main control chip peripheral circuit, the interface circuit, the signal processing circuit and the functional module circuit are respectively connected with the main control chip.

The main control chip is composed of an F28M35x series multi-core single chip microcomputer MCU with the model number of F28M35H 22C. The main control chip comprises a single chip microcomputer MCU, a UART interface, an SPI interface, a CAN interface, a USB interface, an IC interface, a GPIO interface, a first A/D interface and a first A/D interface which are respectively arranged in the single chip microcomputer MCU; the WI-FI module and the GPS module are respectively connected with the UART interface; the input/output interface is connected with the GPIO interface, the signal input conditioning module is connected with the first A/D interface, the voltage conversion and detection module is connected with the second A/D interface, and the voltage modules with different voltages are connected with the voltage conversion and detection module; the SPI isolation interface is connected with the SPI interface; the device comprises a CAN isolation interface connected with the CAN interface, a USB isolation interface connected with the USB interface, and an IC storage circuit connected with the IC interface. The MCU has three subsystems, namely a main control subsystem

A control subsystem TMS320C28x and a simulation subsystem. The main control subsystem has real-time and efficient data processing and control functions; the control subsystem integrates various types of communication peripherals; the analog subsystem has high-precision analog-digital processing performance. The three subsystems provide a hardware basis for the realization of a battery management system development platform.

The peripheral circuit of the main control chip comprises a power supply circuit, a reset circuit, a crystal oscillator clock circuit and a simulation interface circuit. The reset circuit comprises a resistor R1, a reset control pin XRS and a reset control pin ARS which are connected to two ends of a resistor R1, a resistor R2 and a resistor R3 which are connected to one side of two ends of a resistor R1 in series, a capacitor C1 and a capacitor C2 which are connected to the other side of two ends of a resistor R1 in series, the resistor R2 and a resistor R3 are connected in parallel, the capacitor C1 and a capacitor C2 are connected in parallel, a resistor end and a voltage end are connected in series, and a capacitor end is grounded; the reset control pin XRS controls the subsystem to reset, and the reset control pin ARS simulates the subsystem to reset. The reset control pin XRS and the reset control pin ARS are often connected together by an external circuit in a design.

The crystal oscillator clock circuit comprises a crystal oscillator A1, a capacitor C3 and a capacitor C4 which are connected in series with one side of two ends of a crystal oscillator A1, a pin X1 and a pin X2 which are connected in series with the other side of two ends of a crystal oscillator A1; the pin X1 and the pin X2 are respectively used for controlling and simulating the reset of the two subsystems, and the circuit with the model of F28M35H22C is realized through the pin X1, the pin X2 and an SSOSOC end; the operating frequency of up to 100MHz can be realized by the PLL configuration, and the chip can be provided with signals of 10MHz and 32KHz for the internal use of the chip.

The simulation interface circuit is composed of a JTAG interface circuit of F28M35H22C, and the JTAG interface circuit comprises a JTAG interface chip, a resistor R4, a resistor R5, a resistor R6 and a resistor R7 which are respectively connected with the JTAG interface chip. And a user downloads and debugs the program by using the JTAG interface chip.

The power supply circuit comprises a voltage reduction circuit and a power supply detection circuit. The voltage reduction circuit comprises a chip P15, a capacitor C5 connected between a pin 1 and a pin 8 of a chip P15, a capacitor C6 connected to a pin 2 of the chip P15, a capacitor C7, a resistor R8, a resistor R9 connected to a pin 4 of a chip P15, a resistor R10 connected between a pin 3 and a resistor R9 of a chip P15, a diode D1 connected between a pin 8 and a pin 7 of the chip P15, an inductor L1 connected to an output end of the diode D1, a capacitor C1 connected between the other end of the inductor L1 and an input end of the diode D1, a capacitor C1 connected to a pin 5 of the chip P1, a capacitor C1, a resistor R1, the resistor R1 and the capacitor C1 are connected in series, and the capacitor C1 is connected between two ends of the resistor R1 and the capacitor C; a resistor R12 and a resistor R13 connected to pin 5 of the chip P15, and a capacitor C9 connected to one end of the resistor R13.

Since the power supply of the whole vehicle usually fluctuates and the range of the fluctuation is usually 12 to 32V, or even larger, a power supply capable of adapting to voltage fluctuation and ensuring voltage-stabilized output is required. The chip P15 is a voltage reduction and stabilization chip, the input power supply ccV can adapt to voltage change in the range of 4.5V to 60V, the maximum output current can reach 5A, the chip has an integrated high-side MOSFET, and the output voltage is adjustable. The main control board already has a stable 8V voltage. In order to meet the power supply requirements of different parts of the main control board, 8V is respectively reduced to 3.3V and 5V. Meanwhile, the 3.3V and 5V voltages are divided into analog and digital parts by the isolation inductor L1, and stable power supplies are provided for different parts of the main control board.

The power supply detection circuit comprises a voltage signal acquisition circuit and a voltage signal monitoring circuit; the voltage signal acquisition circuit comprises an operational amplifier U18, a resistor R14 connected to the output end of the operational amplifier U18, a resistor R15, a resistor R14 and a resistor R15 which are connected in series; the resistor R16, the resistor R17 and the capacitor C10 are connected to the positive input end of the operational amplifier U18, the resistor R16 is connected with the resistor R17 in series, and the capacitor C10 is connected with the positive input end of the operational amplifier U18 in parallel; a resistor R18, a resistor R19, a resistor R19 and a resistor R18 which are connected with the resistor R17 in series, and a capacitor C11 connected between the positive input terminal and the output terminal of the operational amplifier U18.

In order to ensure that the power supply can stably supply power, when the voltage of the connected power supply drops too fast, the MCU of the singlechip needs to store related data in time. When the power supply voltage rises too fast, the circuit board needs to be protected in time. The power supply detection circuit mainly collects voltage in real time and compares and monitors the upper limit and the lower limit of the voltage. Firstly, the operational amplifiers LM2902-Q1 are used for conditioning signals of input voltage, and then the signals are used for analog sampling of the MCU. Next, the upper and lower limits of the input voltage are compared and monitored by the operational amplifiers LM2903 to Q1.

The voltage-controlled voltage source second-order low-pass filter circuit is composed of operational amplifiers LM 2902-Q1. The operational amplifiers LM2902 to Q1 are independent operational amplifiers with high gain frequency compensation, and can be powered by a single power supply or double power supplies. The power is supplied by the 5V analog power supply of the main control board. When the voltage is stable, the input power ccV and the output AD BATU end select proper resistance, and then the output signal can be directly sent to the A/D sampling module of the MCU analog subsystem of the singlechip for sampling. Therefore, the power supply detection device not only can provide proper power supply for each part of the main control board, but also has the power supply detection function.

The interface circuit comprises a CAN bus interface circuit with isolation, an SIP interface circuit with isolation, a USB interface circuit with isolation and a wireless WI-FI module.

The isolated CAN bus interface circuit is composed of a CAN main control chip with the model number of F28M35H22C, the CAN main control chip is provided with two paths of CAN bus interfaces, and two pins are respectively used as a sending end and a receiving end of a CAN bus. But rather is designed as a CAN bus interface circuit. The CAN bus interface circuit is communicated with a CAN network of the whole vehicle. Here, the CAN bus communication interface with isolation is fully compatible with the CAN2.0b standard interface. Under the twisted-pair drive mode, the CAN bus interface is dominant, and the voltages to ground of the CANH end and the CANL end are 3.5V and 1.5V respectively. When hidden, the voltages to the ground of the CANH terminal and the CANL terminal are both 2.5V. Therefore, it is not possible to directly communicate with the CAN bus in the twisted pair mode, and a high-speed transceiver of the CAN bus needs to be designed. In order to enhance the anti-interference capability of the CAN bus nodes and avoid mutual disturbance between the non-common ground circuits, a CAN bus interface with isolation needs to be designed. The CAN isolation transceiver chip ISO1050 is mainly realized by a CAN isolation transceiver chip ISO1050, and the chip ISO1050 has functions of serial line, overvoltage and ground loss protection and overheating shutoff, and meets the requirements of ISO11898-2 standard. Used with an isolated power supply, this transceiver also prevents noise currents on the data bus or other circuitry from entering the local ground and interfering with and damaging sensitive circuitry. Wherein RXD and TXD are connected with the receiving and transmitting pins; CANH and CANL are connected to a CAN bus. CANH and CANL connect the termination resistors of 120 to achieve impedance matching to reduce electrical signal reflections. The CAN bus interface not only has high-speed transceiving function, but also has isolation effect.

The isolation SPI interface is a high-speed synchronous serial input/output interface and is commonly used for communication between the MCU and peripheral equipment thereof or between the MCU and other MCUs. The SPI interface is mainly used for an SD card storage interface and communication between a main control board and a battery protection board. When the USB interface is connected to an upper computer, the power supply can be turned off, and the USB interface with the isolation is powered by the upper computer; when the USB interface with the isolation is connected to other equipment needing power supply, such as a USB flash disk, the chip can be enabled to provide power for the USB interface with the isolation. The USB interface with the isolation is suitable for being applied to power control of the multifunctional USB interface.

The signal processing circuit comprises a circuit signal acquisition circuit. The signal processing circuit is a voltage-controlled voltage source second-order low-pass filter circuit formed by operational amplifiers LM2902-Q1, isolation signals can directly enter an A/D channel of the MCU for collection, and therefore the MCU can obtain the actual working current value of the battery. The functional module circuit comprises a switching value signal processing circuit and an IC storage module circuit.

In summary, the battery protection board is formed by cascading a plurality of battery management special chips; the main control panel comprises a main control chip, a main control chip peripheral circuit, an interface circuit, a signal processing circuit and a functional module circuit, wherein the main control chip peripheral circuit, the interface circuit, the signal processing circuit and the functional module circuit are respectively connected with the main control chip; the main control chip is composed of an F28M35x series multi-core single chip microcomputer MCU with the model number of F28M35H 22C; the peripheral circuit of the main control chip comprises a power supply circuit, a reset circuit, a crystal oscillator clock circuit and a simulation interface circuit; the power supply circuit comprises a voltage reduction circuit and a power supply detection circuit; the interface circuit comprises a CAN bus interface circuit with isolation, an SIP interface circuit with isolation, a USB interface circuit with isolation and a wireless WI-FI module; the signal processing circuit comprises a circuit signal acquisition circuit; the functional module circuit comprises a switching value signal processing circuit and an IC storage module circuit; the main control board and the battery protection board communicate and transmit signals through the SPI and the I/O with isolation, and a configured battery management system is formed. Because of interface circuit can with external equipment interconnect for the main control board can not only communicate with the battery protection shield, but also can realize with the communication between the various abundant equipment in the external world, has heterogeneous network's characteristics. Meanwhile, due to the power circuit, the power detection circuit, the interface circuit, the signal processing circuit and the functional module circuit inside the main control panel, the main control panel can be ensured to operate safely and stably, so that the main control panel can operate stably, and the system also has richer control functions, and achieves the purposes of safe and stable operation state detection and battery safety protection.

The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, without thereby limiting the scope of the invention. Any modification, equivalent replacement and improvement made by those skilled in the art without departing from the scope and spirit of the present invention should be within the scope of the claims of the present invention.

Claims

1. A power battery protection board test system comprises a main control board, a battery protection board, an electric battery module and a sensor module, wherein the battery protection board is connected with the main control board; the method is characterized in that: the battery protection board is formed by cascading a plurality of battery management special chips; the main control panel comprises a main control chip, a main control chip peripheral circuit, an interface circuit, a signal processing circuit and a functional module circuit, wherein the main control chip peripheral circuit, the interface circuit, the signal processing circuit and the functional module circuit are respectively connected with the main control chip; the main control chip is composed of an F28M35x series multi-core single chip microcomputer MCU with the model number of F28M35H 22C; the peripheral circuit of the main control chip comprises a power supply circuit, a reset circuit, a crystal oscillator clock circuit and a simulation interface circuit; the power supply circuit comprises a voltage reduction circuit and a power supply detection circuit; the interface circuit comprises a CAN bus interface circuit with isolation, an SIP interface circuit with isolation, a USB interface circuit with isolation and a wireless WI-FI module; the signal processing circuit comprises a circuit signal acquisition circuit; the functional module circuit comprises a switching value signal processing circuit and an IC storage module circuit; the main control board and the battery protection board communicate and transmit signals through the SPI and the I/O with isolation, and a configured battery management system is formed.

2. The power battery protection panel testing system of claim 1, wherein: the main control chip comprises a single chip microcomputer MCU, a UART interface, an SPI interface, a CAN interface, a USB interface, an IC interface, a GPIO interface, a first A/D interface and a first A/D interface which are respectively arranged in the single chip microcomputer MCU; the WI-FI module and the GPS module are respectively connected with the UART interface; the input/output interface is connected with the GPIO interface, the signal input conditioning module is connected with the first A/D interface, the voltage conversion and detection module is connected with the second A/D interface, and the voltage modules with different voltages are connected with the voltage conversion and detection module; the SPI isolation interface is connected with the SPI interface; the device comprises a CAN isolation interface connected with the CAN interface, a USB isolation interface connected with the USB interface, and an IC storage circuit connected with the IC interface.

3. The power battery protection panel testing system of claim 1, wherein: the reset circuit comprises a resistor R1, a reset control pin XRS and a reset control pin ARS which are connected to two ends of a resistor R1, a resistor R2 and a resistor R3 which are connected to one side of two ends of a resistor R1 in series, a capacitor C1 and a capacitor C2 which are connected to the other side of two ends of a resistor R1 in series, the resistor R2 and a resistor R3 are connected in parallel, the capacitor C1 and a capacitor C2 are connected in parallel, a resistor end and a voltage end are connected in series, and a capacitor end is grounded; the reset control pin XRS controls the subsystem to reset, and the reset control pin ARS simulates the subsystem to reset.

4. The power battery protection panel testing system of claim 1, wherein: the crystal oscillator clock circuit comprises a crystal oscillator A1, a capacitor C3 and a capacitor C4 which are connected in series with one side of two ends of a crystal oscillator A1, a pin X1 and a pin X2 which are connected in series with the other side of two ends of a crystal oscillator A1; the pin X1 and the pin X2 are respectively used for controlling and simulating the reset of the two subsystems, and the circuit with the model of F28M35H22C is realized through the pin X1, the pin X2 and an SSOSOC end; the operating frequency of up to 100MHz can be realized by the PLL configuration, and the chip can be provided with signals of 10MHz and 32KHz for the internal use of the chip.

5. The power battery protection panel testing system of claim 1, wherein: the simulation interface circuit is composed of a JTAG interface circuit of F28M35H22C, and the JTAG interface circuit comprises a JTAG interface chip, a resistor R4, a resistor R5, a resistor R6 and a resistor R7 which are respectively connected with the JTAG interface chip.

6. The power battery protection panel testing system of claim 1, wherein: the voltage reduction circuit comprises a chip P15, a capacitor C5 connected between a pin 1 and a pin 8 of a chip P15, a capacitor C6 connected to a pin 2 of the chip P15, a capacitor C7, a resistor R8, a resistor R9 connected to a pin 4 of a chip P15, a resistor R10 connected between a pin 3 and a resistor R9 of a chip P15, a diode D1 connected between a pin 8 and a pin 7 of the chip P15, an inductor L1 connected to an output end of the diode D1, a capacitor C1 connected between the other end of the inductor L1 and an input end of the diode D1, a capacitor C1 connected to a pin 5 of the chip P1, a capacitor C1, a resistor R1, the resistor R1 and the capacitor C1 are connected in series, and the capacitor C1 is connected between two ends of the resistor R1 and the capacitor C; a resistor R12 and a resistor R13 connected to pin 5 of the chip P15, and a capacitor C9 connected to one end of the resistor R13.

7. The power battery protection panel testing system of claim 1, wherein: the power supply detection circuit comprises a voltage signal acquisition circuit and a voltage signal monitoring circuit; the voltage signal acquisition circuit comprises an operational amplifier U18, a resistor R14 connected to the output end of the operational amplifier U18, a resistor R15, a resistor R14 and a resistor R15 which are connected in series; the resistor R16, the resistor R17 and the capacitor C10 are connected to the positive input end of the operational amplifier U18, the resistor R16 is connected with the resistor R17 in series, and the capacitor C10 is connected with the positive input end of the operational amplifier U18 in parallel; a resistor R18, a resistor R19, a resistor R19 and a resistor R18 which are connected with the resistor R17 in series, and a capacitor C11 connected between the positive input terminal and the output terminal of the operational amplifier U18.