CN211508898U

CN211508898U - Switch unit arrangement

Info

Publication number: CN211508898U
Application number: CN201921305853.0U
Authority: CN
Inventors: S·施罗特
Original assignee: Ebien Peter Mulfingen GmbH
Current assignee: Ebien Peter Mulfingen GmbH; Ebm Papst Mulfingen GmbH and Co KG
Priority date: 2019-04-29
Filing date: 2019-08-13
Publication date: 2020-09-15
Anticipated expiration: 2029-08-13
Also published as: CN113330675A; EP3874589A1; WO2020221712A1; DE102019110988A1

Abstract

The utility model relates to a switch unit configuration (1) for reducing the radio interference voltage spectrum of electronic switching device, switch unit configuration (1) has and is used for the dynamic change to come from n switch unit return circuits, respectively have an alternating current i of a looks₁To i_nIs provided with N ∈ N and N ≧ 2, where N denotes a positive integer, is provided byThis can reduce the radio interference voltage with lower circuit complexity.

Description

Switch unit arrangement

Technical Field

The utility model relates to a switch unit (Schaltzelle) for reducing the radio interference voltage of electronic commutation device.

Background

The switching power supply and the commutation device generate radio interference due to high frequency switching (hochfrequente Taktung). Radio interference propagates in free space by means of electromagnetic fields and, in wired conditions, in the form of high-frequency voltages and high-frequency currents through the power supply connection. The high-frequency switching device emits radio interference radiation. The radio interference radiation is measured as a radio interference field strength (in μ V/m). The intensity of the radio interference radiation depends, for example, on the edge steepness of the currents and voltages operated and mainly on the circuit configuration. To this end, the prior art provides devices and solutions that attempt to reduce the interference voltage.

In the field of switching power supplies, for example, in order to reduce the distortion of the current drawn from the power supply, i.e. to reduce the harmonics of the supply frequency in the current drawn from the power supply, it is known to connect the switching power supply directly to a bridge rectifier fed by the power supply, without a filter capacitor connected between the two. By correspondingly controlling the on and off times of a switch in a switching power supply operating in a high-frequency switching mode, a current with a sinusoidal supply frequency can be drawn from the power supply which is at least substantially free of harmonics. However, such a circuit has a disadvantage in that the power it consumes contains a component fluctuating with the frequency of the dual power supply in addition to a constant component, which is undesirable.

A circuit arrangement for generating a dc voltage from a sinusoidal input voltage is known from EP 0223315B 1, which circuit arrangement reduces the interference voltage at low frequencies. To this end, this known circuit configuration comprises a switching power supply comprising a diode, a coil, a capacitor and a transistor, to which a substantially sinusoidal input voltage is applied via a rectifier, and whose elements are arranged such that: in the on state of the transistor, the diode blocks, and the coil current flows at least through the transistor, and in the off state, the diode and the load and the capacitor connected in parallel flow. In the pulse generator, switching pulses for the transistor are generated from the input voltage, the frequency of which varies constantly in time between a minimum frequency at which the rectified input voltage reaches a maximum value and a maximum frequency at which the input voltage reaches a minimum value. That is, this circuit configuration connects other switching power supplies between the rectifier and the capacitor that are not electrically isolated, which means a high circuit complexity.

DE 3537536A discloses a suppression element capable of lossy suppression of the anti-ringing pulses (rcuckschwingpulses) on high-frequency switches. Such circuits limit the rise speed of the reverse voltage on the high frequency switch and can thus be used in particular to reduce high frequency interference. That is, the faster the voltage on the high-frequency switch rises when switching to the blocking state, the larger the capacitive interference current flowing in parasitic capacitance (e.g., a joint of the high-frequency switch connected to the heat sink and the ground) that is always present in the environment of the high-frequency switch becomes. Without initially canceling such interference, it may be necessary to use complex power filters to suppress the interference. However, the above-described suppression element also increases circuit complexity. The circuit becomes particularly complex when the above-mentioned known low-frequency interference and high-frequency interference suppression measures have to be jointly employed in the supply circuit.

SUMMERY OF THE UTILITY MODEL

The object of the present invention is to provide a circuit arrangement which enables radio interference voltages, in particular harmonics of the switching frequency, to be reduced with a low circuit complexity.

The basic idea of the present invention is to dynamically change the phase offset of the circuit, in particular by: when at least two power electronic switching units operating in switched mode are operating in parallel, the power electronic switching units are operated by targeted dynamic phase shifting of a carrier signal modulating the power electronic switching units, thereby targeted reduction of radio interference voltages.

By using the interleaving technique (i.e. controlling at least two commutation cells in time), a single harmonic in the frequency spectrum is reduced according to the phase shift of the control signal, based on the present invention a dynamic phase shift, which implies a dynamic influence on the harmonic, which dynamic influence can again result in a measurement of a lower level on the detector stage (detektorstefe) of the measuring instrument due to the limited pulse bandwidth of the measuring instrument.

In particular, for this purpose, the carriers of the modulation scheme (modulation scheme) of at least one of the switching units of the switching unit arrangement are phase-shifted. In another technical scheme, the following settings are carried out: by varying the phase offset and the frequency jitter of the modulation scheme of at least one switching cell configured by the switching cells.

To this end, the invention proposes a switch unit arrangement with the following characteristics:

dynamically varying an alternating current i, each having a phase, from n switching cell circuits₁To i_nIs offset to reduce the radio interference voltage spectrum (FSS), where N ∈ N and N ≧ 2, where N represents a positive integer.

Wherein the phase offset may be varied according to a predetermined function.

Wherein the circuit is designed such that the phase shift proceeds rapidly, thereby reducing the radio interference voltage spectrum (FSS) based on the finite pulse width of the meter.

According to the invention, the switching unit is configured for this purpose with:

a. a first wire loop comprising at least two first and second parallel-arranged conductive paths, a first common conductive node of the first and second conductive paths and a first terminal for feeding an input alternating voltage U_{Input device}Is connected to a second common conductive node of the first and second conductive paths and is arranged to provide an output ac voltage U_{Output of}Is connected to the first common output side connection, and

b. a second wire loop comprising at least two third and fourth parallel-arranged conduction paths, a third common conduction node of said third and fourth conduction paths and a third common conduction node for feeding said input alternating voltage U_{Input device}Is connected to a fourth common conductive node of said third and fourth conductive paths and is arranged to provide said output ac voltage U_{Output of}Is connected to the second common output side connection of,

c. a fifth conductive path and a sixth conductive path each having at least one switch are provided between the first wire loop and the second wire loop,

d. a control circuit formed to sequentially open and close the switches in a staggered time such that phases of current through the first and second conductive paths and phases of current through the third and fourth conductive paths are relatively offset so as to be included in the electricityStream i₁To i_nAt the total current i, one or several current peaks or harmonics in_{General assembly}＝i₁+i₂+…+i_nThrough the current i₁To i_nIs reduced or eliminated.

In a particularly advantageous embodiment of the invention, the following is provided: the control circuit is formed to exclude the current i₁…i_nPhase shift of

Frequency jitter is superimposed to change the frequency of the phase shift achieved.

The following are also particularly advantageous: the switch is arranged for this purpose in a fifth conductive path between the first conductive path of the first wire loop and the third conductive path of the second wire loop.

Advantageously, the switch is arranged for this purpose in a sixth conductive path between the second conductive path of the first wire loop and the fourth conductive path of the second wire loop.

The following technical solution is further advantageous: a first diode is arranged in a third conductive path of the second wire loop and further a second diode is arranged in a fourth conductive path of the second wire loop.

In a further advantageous embodiment of the invention, the following are provided: the switch is an electronic switch.

In a further advantageous embodiment of the invention, the following are provided: the switches are power semiconductor switches.

Another aspect of the invention (in addition to the above description of the device) relates to the use of said arrangement for reducing the radio interference voltage of an electronically commutated device by means of a switch unit arrangement as described above, at least in the following steps. The control circuit operates the two switches in sequence in time-staggered (in a fast switching manner) such that the current i through the first and second conduction paths₁And through the third and fourth conduction pathsCurrent i of the path₂Is relatively phase shifted so as to be included in the current i₁And i₂At the total current i, one or several current peaks or harmonics in_{General assembly}＝i₁+i₂In the passing current i₁And i₂Is reduced or eliminated.

The core idea of the utility model relates to following aspect: dynamically changing phase shift

The realization mode is as follows: phase shifting by means of a control circuit

Frequency jitter for rapidly changing the frequency is superimposed. Wherein the phase shift change used for this purpose becomes particularly effective if the change takes place in the 13kHz range.

In a further advantageous embodiment of the invention, the following are provided: the phase is changed from 180 ° to 90 ° or from 90 ° to 45 ° by means of phase dithering (phasejittering).

With regard to the features of further advantageous developments of the invention, reference is made to the above description, which is to be read in conjunction with the preferred embodiments of the invention, with reference to the attached drawings.

Drawings

Wherein:

FIG. 1 is an exemplary switch cell configuration;

FIG. 2 shows the sum current i_{General assembly}A schematic diagram of (a);

FIG. 3 is a view (180 degrees staggered) of a first measurement curve;

FIG. 4 is a view (staggered by 90) of a second measurement curve;

FIG. 5 is a view (staggered 45) of a third measurement curve;

fig. 6 is a view of a fourth measurement curve (staggered jitter).

Detailed Description

The invention is explained in more detail below with reference to fig. 1 to 6, wherein like reference numerals refer to like structural and/or functional features.

Fig. 1 shows an exemplary switching cell arrangement 1. This switching cell configuration 1 is composed of a first line loop LS1 comprising two parallel-arranged

conductive paths

12, 13, one of the common conductive nodes 10 of which is connected to a common conductor for feeding an input ac voltage U_{Input device}Common input side first connector U_e1And (4) connecting.

Second common conductive node 11 for providing an output AC voltage U_{Output of}First common output side terminal U_a1And (4) connecting.

In the present embodiment, the input voltage is smaller than the output voltage, and the configuration is used similarly to the boost converter.

The second line circuit LS2 has two parallel-arranged

conductor paths

22, 23, of which one common conductor node 20 is connected to a common conductor node for feeding an input ac voltage U_{Input device}Common input side second terminal U_e2And (4) connecting.

As shown in fig. 1, a second common conductive node 21 of the conductive paths is connected to supply the output ac voltage U_{Output of}Second common output side terminal U_a2And (4) connecting.

Between the two line loops LS1, LS2, there are provided

conductive paths

30, 31 each having a switch S1, S2.

Furthermore, a first diode D1 is arranged in first conductive path 22 of second wire loop LS2 after the branch node of conductive path 30, and likewise a second diode D2 is arranged in second conductive path 23 of second wire loop LS2 after branch node 25 of conductive path 31. In first conductive path 22 of second wire loop LS2, a winding L1 is further provided upstream of the branch node of conductive path 30, and in second conductive path 22 of second wire loop LS2, a winding L2 is further provided upstream of the branch node of conductive path 31.

By turning on the switch S1, the current i1 in the coil L1 rises. If the switch S1 is then opened again in the boost converter mode described above, the current i1 continues to flow through the coil L1 and the diode D1 and drops again in the process. By turning on the switch S2, the current i2 in the coil L2 rises. If the switch S2 is then opened again in the boost converter mode described above, the current i2 continues to flow through the coil L2 and the diode D2 and drops again in the process.

If more identical commutation cells (Kommutierungszelle) are now used, the input current will be split between the stages.

If the control signals of the switches S1 and S2 are shifted by one phase relative to each other

As shown in fig. 2, the high frequency current ripples partially cancel each other out.

These measures have the following effect on electromagnetic compatibility. Frequencies, in particular from 150kHz, are of particular interest for the spectrum of radio interference voltages. Thus, the switching frequency f at 130kHz_PWMNext, frequencies from the second harmonic are of particular interest.

If sum of the currents i_{General assembly}Split into spectral components, the results show that specific harmonics associated with a particular phase and multiples thereof cancel each other out in the spectrum. These harmonics are the 1 st, 3 rd, 5 th, … harmonics at 180 ° phase shift. At a 90 phase shift, the 2 nd, 5 th, 7 th, … harmonics cancel each other out. Every time a commutation unit is added, one more harmonic and its multiples can be eliminated according to the phase offset.

For this purpose, in each case one further first and second line circuit can be provided, which together with the respectively adjacent line circuit form two parallel-arranged line circuits, of which one common line node is connected to the common input-side connection for supplying the input ac voltage and the second common line node is connected to the common output-side connection, and in each case one further line circuit with a further switch is provided between the line circuits, so that a cascaded parallel connection of the switching units is formed.

For operating the switches S1, S2, a control circuit is provided, which controlsThe circuit is formed for sequentially opening and closing the two switches S1, S2 in time-staggered manner, so that the phase of the current i1 through one of the conduction paths 22 and the phase of the current i2 through the second conduction path 23 are relatively offset, so that the current i is contained in₁And i₂At the total current i, one or several current peaks or harmonics in_{General assembly}Passing current i in i1+ i1₁And i₂Is reduced or eliminated.

However, it is not meaningful to completely eliminate a single harmonic, since the corresponding higher order harmonic or lower frequency harmonic is then decisive for the limit value compliance.

If one observes the radio jammer used for measuring the radio interference voltage according to CISPR16, it is found that the radio jammer has a defined pulse bandwidth which is divided into different ranges depending on the measuring frequency and has a bandwidth of 9kHz in the range of 150kHz to 30 MHz. If the frequency of the pulses generated by the circuit is greater than 9kHz, the pulses will be only partially sensed by the meter due to the missing pulse bandwidth.

The solution is therefore as follows: the commutation cells (which are each composed of one conducting path in the upper and lower conductor loop, the corresponding coil and diode in the upper path, and the switch with the connecting path) are rapidly phase-shifted relative to one another, so that the harmonics resulting from the phase-shifted switching (phaseverses Takten) are always shifted. Wherein the phase is changed rapidly so that the change is at half the pulse bandwidth of the meter, thereby reducing the measured interference. The quotient of the switching frequency and the phase change frequency is preferably equal to an integer multiple, which has a favorable effect on the control behavior.

For example, the phase is changed from 180 ° to 90 ° (or from 90 ° to 45 ° as measured) and back again at a switching frequency of 130kHz and a phase change frequency of 13 kHz. The harmonics thus generated and affected by the respective interleaving are thus reduced and the filters required for electromagnetic compatibility can be reduced.

The utility model discloses a scheme can exert the influence to a plurality of harmonics and amplitude distribution thereof simultaneously. The subsequent views in fig. 3 to 6 exemplarily show the frequency spectrum of the normalized zero-mean current output by the signal generator to the input of the measuring instrument. There is no second harmonic in fig. 3 with an interleaving value of 180 deg. because only 130kHz and multiples thereof are eliminated. In fig. 4 where the interleaving value is 90 °, there is no third harmonic at 260 kHz. There is no fourth harmonic in fig. 5 with an interleaving value of 45 °. The advantage of dynamic phase variation is clearly reflected in the minimum amplitude in fig. 6, which shows the "staggered jitter from 45 ° to 90 ° with a 13kHz phase variation frequency" pattern.

This scheme can also be operated in conjunction with frequency variation to further flatten (Verschleifen) the spectrum. The above-described solution is also applicable to parallel operation of, for example, two or several inverters for motor commutation. The phase change can be controlled by means of a mathematical function, wherein several phases with different transitions (jumps, transitions, etc.) and one continuously changing phase can be used. The time spans with different lengths can be selected for each phase. The utility model discloses a scheme is not only influential to input current, also influential to the interference that the switch unit causes jointly.

Claims

1. A switching cell arrangement (1) for reducing the radio interference voltage spectrum of an electronic commutation device, characterized in that the switching cell arrangement (1) has means for dynamically changing alternating currents i, each having one phase, from n switching cell loops₁To i_nIs provided, wherein N ∈ N and N ≧ 2, where N represents a positive integer, to reduce the radio interference voltage spectrum.

2. The switching cell configuration (1) according to claim 1, characterized in that the phase offset is varied according to a fixed function.

3. The switching cell configuration (1) according to claim 1 or 2, characterized in that the temporal variation of the phase offset is performed rapidly, thereby reducing the radio interference voltage spectrum based on the finite pulse width of the meter.

4. The switching cell arrangement (1) according to claim 1 or 2, characterized by having:

a. at least one first line loop (LS1) comprising at least two first and second parallel-arranged conducting paths (12, 13), the first common conducting node (10) of which is connected to a first common conducting node for feeding an input AC voltage U_{Input device}Common input side first terminal (U)_e1) A second common conductive node (11) of the first and second conductive paths and means for providing an output alternating voltage U_{Output of}First common output side terminal (U) of_a1) Is connected, and

b. at least one second line loop (LS2) comprising at least two third and fourth parallel-arranged conduction paths (22, 23), a third common conduction node (20) of which is connected to a first common conduction node for feeding the input AC voltage U_{Input device}Common input side second terminal (U)_e2) A fourth common conductive node (21) of the third and fourth conductive paths connected to provide the output AC voltage U_{Output of}Second common output side terminal (U) of_a2) The connection is carried out by connecting the two parts,

c. a fifth and a sixth conductive path (30, 31) each having at least one switch (S1, S2) are provided between the first and second conductor loops (LS1, LS2),

d. a control circuit formed to sequentially open and close the switches in a staggered time such that phases of currents through the first and second conductive paths and phases of currents through the third and fourth conductive paths are relatively offset so as to be included in the current i₁To i_nAt the total current i, one or several current peaks or harmonics in_{General assembly}＝i₁+i₂+…+i_nThrough the current i₁To i_nIs reduced or eliminated.

5. The switch cell configuration (1) according to claim 4, characterized in that the control circuit is formed for excluding the current i₁…i_nPhase shift of

Frequency jitter is also superimposed to change the frequency of the phase shift.

6. The switch cell configuration (1) according to claim 4, characterized in that the switch is arranged in a fifth conductive path (30) between the first conductive path (12) of the first wire loop (LS1) and the third conductive path (22) of the second wire loop (LS 2).

7. The switching cell configuration (1) according to claim 4, characterized in that the switch is arranged in a sixth conductive path (31) between the second conductive path (13) of the first wire loop (LS1) and the fourth conductive path (23) of the second wire loop (LS 2).

8. The switching cell configuration (1) according to claim 4, characterized in that a first diode (D1) is arranged in the third conductive path (22) of the second wire loop (LS 2).

9. The switch cell configuration (1) according to claim 4, characterized in that a second diode (D2) is arranged in a fourth conductive path (23) of the second wire loop (LS 2).

10. The switch cell configuration (1) according to claim 4, characterized in that the switches (S1, S2) are electronic switches.

11. The switch cell configuration (1) according to claim 10, characterized in that the switches (S1, S2) are power semiconductor switches.