CN211505789U

CN211505789U - PCIE board card testing arrangement

Info

Publication number: CN211505789U
Application number: CN201922210522.5U
Authority: CN
Inventors: 王安; 孔祥涛
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2019-12-11
Filing date: 2019-12-11
Publication date: 2020-09-15
Anticipated expiration: 2029-12-11

Abstract

The utility model discloses a PCIE board card testing device, wherein PCIE SWITCH, BMC and a fan module are arranged on a mainboard of the device; the PCIE SWITCH is connected with the BMC through a UART; the fan of the fan module is inserted into the fan connector, and the fan connector is in control connection with the BMC; the PCIE board to be tested is plugged on a Riser board connected with the main board, and the Riser board is connected with PCIE SWITCH of the main board through a cable. The utility model provides an operate inconvenient, support equipment small in quantity, with high costs, the problem of inefficiency among the current PCIE integrated circuit board test technique, can be high-efficient, quick, convenient carry out the integrated circuit board and verify. The operation is simple and convenient, and the board card test can be completed without an external operating system. In addition, the automatic distribution of the board card bandwidth can be realized through BMC by identifying different addresses Pin of the external board card, so that different test board cards are adapted, and manual operation is reduced.

Description

PCIE board card testing arrangement

Technical Field

The utility model relates to a server test field, concretely relates to PCIE integrated circuit board testing arrangement.

Background

In a server product, as the scale of a system becomes larger and the complexity increases, the number of PCIE boards also becomes more and more, and the workload for management and verification of the PCIE boards becomes more and more. In the laboratory, the material management personnel often will carry out quality verification judgement to the integrated circuit board that uses daily, and hardware engineer will carry out preliminary integrated circuit board function verification to the integrated circuit board of new development, all use the server system to go to verify at present, through looking for suitable complete machine server equipment, insert corresponding PCIE integrated circuit board on the PCIE slot that server equipment corresponds under the power-off state, the start gets into the system, look over the connection status of corresponding integrated circuit board under the system, including the bandwidth of connecting, rate information, judge whether the integrated circuit board is normal according to actual integrated circuit board configuration information.

Because the native PCIE resource of the CPU of the server equipment is limited, servers designed aiming at a large amount of PCIE card-inserting equipment are not many, the number of PCIE slots of the whole server specially used for testing the board card is small, the checking of the actual connection state of the board card also needs to enter the system for checking, and the entering of the system takes time, so that the verification of the PCIE board card at present cannot be realized rapidly in batch, an operating system needs to be relied on, the efficiency is low, the cost is high, and the system is not convenient and simple.

Disclosure of Invention

In order to solve the technical problem, the utility model provides a PCIE integrated circuit board testing arrangement can carry out the PCIE integrated circuit board high-efficiently, fast, conveniently and verify.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

a PCIE board card testing device is characterized in that PCIE SWITCH, BMC and a fan module are arranged on a mainboard of the device; the PCIE SWITCH is connected with the BMC through a UART; the fan of the fan module is inserted into the fan connector, and the fan connector is in control connection with the BMC;

the PCIE board card to be tested is plugged on an Ri ser board connected with the main board, and the Ri ser board is connected with PCIESWITCH of the main board through a cable.

Further, the fan connector sends a PRESENT _ N signal to the BMC, the BMC sends a PWM signal to the fan connector, and the fan connector feeds back a TACH signal to the BMC.

Furthermore, the mainboard is provided with a DB9 connector, the DB9 connector is connected with PCIE SWITCH through UART, and is connected with a computer through a USB-to-serial port adapter cable to transmit PCIE board card state information.

Furthermore, the mainboard is provided with an RJ45 interface, the RJ45 interface is connected with a BMC inside the mainboard, and is connected with a computer outside the mainboard through a network cable to transmit PCIE board card state information.

Further, the fan module comprises a 6056 specification fan for dissipating heat of the device.

Further, the Ri ser plate comprises X16S lot Riser, X8 Slot Riser and X4 Slot Riser.

Further, the PCIE board includes three types, X16, X8, and X4.

The utility model has the advantages that:

the utility model discloses a PCIE integrated circuit board testing arrangement has solved the inconvenient, support equipment problem few, with high costs, the inefficiency of operation among the current PCIE integrated circuit board testing technique, can be high-efficient, quick, convenient carry out the integrated circuit board and verify.

PCIE slot expansion is carried out through PCIE SWITCH, so that the number of board cards tested by the system at a time is increased, and the cost of the test system is reduced. The state of testing the PCIE board card is obtained through PCIE SWITCH self-contained UART external computer or an onboard BMC chip, the operation of the whole process is simple and convenient, and the board card test can be completed without an external operating system. In addition, the automatic distribution of the board card bandwidth can be realized through the BMC by identifying different addresses P in of the external board cards, so that different test board cards are adapted, and manual operation is reduced.

Drawings

Fig. 1 is a schematic diagram of a connection structure of an embodiment of a PCIE board test apparatus of the present invention;

fig. 2 is a schematic diagram of the fan connector signal connection of the PCIE board test apparatus of the present invention;

fig. 3 is a schematic diagram of a second connection structure of the PCIE board test apparatus of the present invention.

Detailed Description

In order to clearly illustrate the technical features of the present invention, the present invention is explained in detail by the following embodiments in combination with the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. In order to simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and processes are omitted so as to not unnecessarily limit the invention.

As shown in fig. 1, a first embodiment of the present invention provides a PCIE board test device, where PCIE SWITCH, BMC and a fan module are disposed on a motherboard of the device; the PCIE SWITCH is connected with the BMC through a UART; the fan of the fan module is inserted into the fan connector, and the fan connector is in control connection with the BMC;

Specifically, as shown in fig. 2, after the fan is inserted into the fan connector, the fan connector sends a PRESENT _ N signal to the BMC, the BMC receives the on-site information of the fan, sends a PWM signal to the fan connector, controls the fan speed, and the fan connector feeds back a TACH signal to the BMC, so that the control and monitoring of the fan speed are realized.

On the basis of the first embodiment, the second embodiment of the present invention takes PCIE SWITCH of 96Lane as an example, and describes the connection structure of the testing device in detail.

PCIE SWITCH can be externally connected with PCIE board cards of X16, X8 and X4, and respectively accessed through X16 Slot Riser, X8S lot Riser and X4S lot Riser which are connected with PCIE SWITCH cables. In the second embodiment, PCIE SWITCH of 96Lane is selected, and 6 PCIE boards with X16 bandwidth, 12 PCIE boards with X8 bandwidth, or 24 PCIE boards with X4 bandwidth may be supported, and different Ri ser boards may be selected according to different test requirements, as shown in fig. 3, 12X 8 Slot Ri ser are adopted in the second embodiment.

The fan module of the second embodiment is composed of 6 fans of 6056 specification, the fans are fixedly installed on the mainboard, and 6 fan connectors of the fan module are respectively connected with the BMC in a control mode and used for heat dissipation of the device.

The state detection of the PCIE board card to be detected is acquired through the UART (universal asynchronous receiver/transmitter) of PCIE SWITCH, and is specifically realized through two operation modes. Firstly, the computer is connected with the mainboard through a standard DB9 connector arranged on the mainboard. The DB9 connector is connected with PCIESWITCH through a UART (universal asynchronous receiver/transmitter), and is connected with a computer through a USB-to-serial port patch cord, a computer end can read the connection state of PCIESWITCH and the PCIE board card connected with PCIE SWITCH through a command by using a serial port tool, an ARM microprocessor integrated in PCIE SWITCH can acquire the bandwidth and speed information of the whole PCIE SWITCH and each PCIE board card, and the acquired text information can be directly read and analyzed at the computer end. And secondly, checking and managing through the BMC. The device mainboard is provided with an RJ45 interface, the device mainboard can be connected with a computer through a network cable, and the BMC is connected with an RJ45 interface through a PHY. The IP address of the PCIE SWITCH mainboard is input through the browser, the BMC logs in to the BMC, the BMC has a Web operation interface, the detailed information of the PCIE board card which needs to be detected at present can be listed only by clicking the acquisition button after the starting, and the operation in the whole process is simple and convenient. In addition, the system detects the board address signal on the PCIE board when the PCIE SWITCH and the PCIE board are connected, and bandwidth allocation of PCIE SWITCH can be automatically configured through the BMC when the whole detection system is turned on, so that different PCIE boards are adapted.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the scope of the present invention is not limited thereto. Various modifications and alterations will occur to those skilled in the art based on the foregoing description. And are neither required nor exhaustive of all embodiments. On the basis of the technical scheme of the utility model, various modifications or deformations that technical personnel in the field need not pay out creative work and can make still are within the protection scope of the utility model.

Claims

1. A PCIE board card testing device is characterized in that PCIE SWITCH, BMC and a fan module are arranged on a mainboard of the device; the PCIE SWITCH is connected with the BMC through a UART; the fan of the fan module is inserted into the fan connector, and the fan connector is in control connection with the BMC;

the PCIE board to be tested is plugged on a Riser board connected with the main board, and the Riser board is connected with PCIE SWITCH of the main board through a cable.

2. The PCIE board test device of claim 1, wherein the fan connector sends a PRESENT _ N signal to the BMC, the BMC sends a PWM signal to the fan connector, and the fan connector feeds back a TACH signal to the BMC.

3. The PCIE board test device according to claim 1, wherein the motherboard is provided with a DB9 connector, the DB9 connector is connected to PCIE SWITCH through UART, and is connected to a computer through a USB-to-serial port patch cord to transmit PCIE board status information.

4. The PCIE board test device according to claim 1, wherein the motherboard is provided with an RJ45 interface, the RJ45 interface is connected to the BMC inside the motherboard, and is connected to a computer outside the motherboard through a network cable to transmit PCIE board status information.

5. The PCIE board test apparatus of claim 1, wherein the fan module comprises a 6056 specification fan for device heat dissipation.

6. The PCIE board card testing device of claim 1, wherein the Riser board includes X16 Slot Riser, X8 Slot Riser and X4 Slot Riser.

7. The PCIE board test device of claim 6, wherein the PCIE board includes three of X16, X8 and X4.