CN211479114U - PCIE optical fiber communication adapter card - Google Patents

Abstract

The utility model provides a PCIE optical fiber communication switching card, include: the system comprises a connector, a DCDC power supply, an FPGA module and at least one QSFP interface cage; the connector is used for taking electricity and connecting the FPGA module into the computer system through PCIE X8; the FPGA module comprises an FPGA chip and a firmware, the FPGA chip is connected with at least one QSFP interface cage and the firmware, and the FPGA module is used for carrying out PCIE protocol analysis on the acquired PCIE data stream issued by the computer system and converting the PCIE data stream into optical port data and transmitting the optical port data to a corresponding transmitting optical port; the DC-DC power supply is connected with the connector and the FPGA module and used for supplying power. The utility model discloses realize PCIE to the switching card of fiber communication based on FPGA field programmable gate array, encrypt through field programmable logic, both possessed the characteristic of hard encryption, possessed the easy characteristics of upgrading of soft encryption again, communication rate is controllable, and the bottom agreement is steerable, can encrypt, has improved PCIE switching card security and flexibility, can be applicable to different application scenes.

Description

PCIE optical fiber communication adapter card

Technical Field

The utility model relates to the field of communication technology, concretely relates to PCIE optical fiber communication switching card.

Background

The optical fiber communication is widely applied to the fields of electric power communication, photoelectric media, intelligent transportation, industrial automation, national defense informatization construction and the like, and becomes a key technology influencing the life of everyone. In an electric power system, optical fibers are laid along with high-voltage wires to realize high-speed information transmission, so that an intelligent power supply network is provided for people. In the photoelectric media industry, the output of sound images is mainly used, and in order to ensure the quality of sound images and ensure the stability and bandwidth of transmission, complete equipment based on an optical fiber communication technology is built in some media units; in the military field, optical fiber communication can not only transmit a large amount of information, but also has strong anti-interference performance, and occupies irreplaceable positions in the aspects of ground communication, air communication, strategic communication and the like. And the optical fiber card is a basic component unit for optical fiber communication.

The existing optical fiber communication cards are basically supplied by international great numbers such as INTELBRODCOM, Cisco Huashi and the like, domestic supply also adopts the chips as OEMs basically, interfaces and protocols tend to be standard, controllability is poor, a bottom layer protocol cannot be adjusted basically, safety is low, standardization brings the advantage of compatibility, and lawless persons have the opportunity to steal information from the interface and the protocol.

SUMMERY OF THE UTILITY MODEL

To the defect among the prior art, the utility model provides a PCIE fiber communication switching card.

The utility model provides a PCIE optical fiber communication switching card, include:

the system comprises a connector, a DCDC power supply, an FPGA module and at least one QSFP interface cage;

the connector is used for taking electricity and connecting the FPGA module into a computer system through PCIE X8;

the FPGA module comprises an FPGA chip and a firmware, the FPGA chip is connected with the at least one QSFP interface cage and the firmware, an FPGA program is stored in the firmware, and the FPGA module is used for carrying out PCIE protocol analysis on the acquired PCIE data stream issued by the computer system, determining data to be processed and determining a forwarding optical port of each data to be processed through route judgment; converting data to be processed into optical interface data according to an optical interface protocol, and forwarding the optical interface data to a corresponding forwarding optical interface;

the DC-DC power supply is connected with the connector and the FPGA module and used for supplying power.

As above PCIE optical fiber communication adapter card, optionally, the FPGA module includes:

and the PCIE interface control sub-module is connected with the connector and is used for realizing the communication control of the PCIE interface and the computer system.

As above PCIE optical fiber communication adapter card, optionally, the FPGA module further includes:

and the downlink buffer queue is connected with the PCIE interface control submodule and is set to be in an FIFO mode.

As above PCIE optical fiber communication adapter card, optionally, the FPGA module further includes:

and the uplink buffer queue is connected with the PCIE interface control submodule and is set to be in an FIFO mode.

As above PCIE optical fiber communication adapter card, optionally, the FPGA module further includes:

and the FIFO state monitoring management submodule is connected with the uplink buffer queue and the downlink buffer queue and is used for configuring and detecting the FIFO state.

As above PCIE optical fiber communication adapter card, optionally, the FPGA module further includes:

and the encryption submodule is connected with the downlink buffer queue and used for encrypting the data to be processed.

As above PCIE optical fiber communication adapter card, optionally, the FPGA module further includes:

and the decryption submodule is connected with the uplink buffer queue and used for decrypting the received optical port data.

As above PCIE optical fiber communication adapter card, optionally, the FPGA module further includes:

and the GTH interface serial-parallel conversion sub-module is connected with each optical port and used for converting parallel data into serial data when transmitting data and converting serial data into parallel data when receiving data.

As for the PCIE optical fiber communication adapter card, optionally, the model of the FPGA chip is V7XC 690T.

The utility model provides a PCIE optical fiber communication switching card, realize PCIE to the switching card of optical fiber communication based on FPGA field programmable logic gate array, encrypt through field programmable logic, both possessed the characteristic of hard encryption, possessed the characteristics that soft encryption easily upgraded again, communication rate is controllable, the bottom agreement is steerable, can encrypt, PCIE switching card security and flexibility have been improved, adapt to different application scenes, be particularly useful for the sensitive trade of data security.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a PCIE optical fiber communication adapter card provided in an embodiment of the present invention;

fig. 2 is a schematic diagram of an FPGA module in a PCIE optical fiber communication adapter card provided in an embodiment of the present invention;

fig. 3 is a schematic flow chart of a method for implementing a PCIE optical fiber communication adapter card according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a DES encryption process according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of one iteration in the DES encryption process provided by the embodiment of the present invention

Fig. 6 is a schematic diagram of a DES encryption process in an FPGA module according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Fig. 1 is the embodiment of the utility model provides a structural schematic diagram of PCIE fiber communication switching card, as shown in fig. 1, PCIE fiber communication switching card includes: the device comprises a connector, a DCDC power supply, an FPGA module and at least one QSFP interface cage;

the connector is used for taking electricity and connecting the FPGA module into a computer system through PCIE X83.0; the connector is responsible for getting the electricity,

the FPGA module comprises an FPGA chip and firmware, the FPGA chip is connected with at least one QSFP interface cage and the firmware, the FPGA program is stored in the firmware, the FPGA automatically loads the program after being powered on so as to complete PCIE interface and protocol control and optical interface and protocol control, and the data sent to a corresponding optical interface by the computer system through the PCIE are subjected to routing judgment and then protocol conversion, and then are transmitted to the corresponding optical interface. And the DC-DC power supply is connected with the connector and the FPGA module and used for supplying power. The model of the FPGA chip can be V7XC 690T.

Fig. 2 is the embodiment of the utility model provides an FPGA module sketch among PCIE fiber communication adapter card, as shown in fig. 2, the fpAG module includes: a PCIE interface control sub-module, an FIFO status monitoring management sub-module, an uplink buffer queue, a downlink buffer queue, an encryption sub-module, a decryption sub-module and a GTH interface serial-parallel conversion sub-module (GTHsedes).

The PCIE interface control submodule is connected with the connector, communication control of the PCIE interface and the computer system is completed, a PCIE protocol is realized, received data are analyzed and sent into an uplink buffer queue, the uplink buffer queue can be configured into an FIFO mode, when the data are sent, the data are sent into a downlink buffer queue, the downlink buffer queue can also be configured into the FIFO mode, and then the data are sent to each optical port after being taken out from the queue and processed by a sending module; when receiving data, the data coming from the optical port enters the uplink buffer queue after a series of processing, and when the alignment is not empty, the PCIE interface control sub-module sends an interrupt signal to the computer through the PCIE interface to inform the computer that the received data is to be processed.

Aiming at the problem of large data volume and frequent interruption, optimization is needed. When the data packet on the optical interface is small, when the data packet is frequent, the system can generate a lot of interrupts, the system can spend too much time to process the interrupts, the processing efficiency is low, therefore, the interrupts can be made configurable, the interrupts can be configured to be generated when the FIFO is nearly full, the system can check whether data needs to be read or not in an inquiry mode in normal time, the CPU utilization rate is greatly improved, the CPU does not need to continuously process the interrupts, but checks whether the received data of the optical fiber card is to be processed or not at intervals, if so, the DMA is processed to the memory, and if not, the DMA directly exits. The FIFO status monitoring management submodule configures and detects the FIFO, the interrupt can be configured into 10 levels aiming at different application scenes, for example, some optical interfaces may apply some relatively small data volume, and have certain requirements on real time, while other optical interfaces require large data volume, but have less strict requirements on delay, and then a reasonable processing level can be achieved by configuring different interrupt levels respectively. On the other hand, the size of the FIFO can be configured, and the FIFO can be adjusted according to the actual scene during application, so that the flexibility and the adaptability to the blind scene are greatly increased. For data encryption, an independent encryption sub-module and an independent decryption sub-module are arranged in an FPGA module to encrypt and decrypt data, the FPGA module is customizable and replaceable, and has the flexibility and the safety of programmable logic.

The following processing procedure of the FPGA module is specifically explained, fig. 3 is a schematic flow diagram of an implementation method of a PCIE optical fiber communication adapter card provided in an embodiment of the present invention, as shown in fig. 3, the method includes:

step S31, acquiring a PCIE data stream issued by the computer system;

specifically, a PCIE data stream issued by the computer system is acquired through the connector and the PCIE interface control sub-module, and after the PCIE data stream issued by the computer system is acquired, the PCIE data stream is sent to a downlink buffer queue, where the downlink buffer queue may be set to an FIFO mode, and the specific size of the FIFO and the trigger condition for taking out data are determined according to the data characteristics of each optical interface.

Step S32, performing PCIE protocol analysis on the PCIE data stream, determining to-be-processed data, and determining a forwarding optical port of each to-be-processed data through routing judgment;

specifically, according to a preset period, for example, processing is performed once at intervals of a period of time, PCIE data is taken out from the downlink buffer queue, optical interface protocol conversion is performed on the PCIE data, and data to be processed is determined.

Step S33, encrypting the data to be processed;

in particular, a simple encryption algorithm may be used, for example, a set of random codes is selected to perform an exclusive or operation on the data to be processed, and a CRC is generated. The data to be processed may also be encrypted using DES encryption. The DES encryption algorithm is to change a 64-bit plaintext input block into a 64-bit ciphertext output block, the key of which is 64 bits, 8 of which are parity bits.

Fig. 4 is a schematic diagram of a DES encryption process according to an embodiment of the present invention; fig. 5 is a schematic diagram of one iteration in the DES encryption process provided by the embodiment of the present invention, as shown in fig. 4 to 5, the DES encryption process includes:

for the data m to be processed, rearranging all bits in m through a fixed initial permutation IP, and constructing a 64-bit string m 0;

splitting the 64-bit string m0 into m0 ═ IP (m0) ═ L0R0, wherein L0 consists of the last 32 bits of m 0;

calculating 16 iterative transformations, wherein each iteration has the same structure, the ith iterative operation takes the result of the (i-1) th iteration and a sub-key Ki as input, each iterative operation only carries out transformation on the right half part Ri-1 of the data, and LiRi obtained according to a round function f is taken as the input of the next iteration to represent the XOR (addition according to a bit modulo 2) of 2 bit strings;

the subkey Ki of each round of operation is obtained by dividing a 56-bit user key into 2 parts, and each part is obtained by shifting according to a cyclic shift number table and replacing according to a replacement selection table;

the processing procedure of the round function f comprises the following steps: firstly, E replacement is carried out on Ri-1, then exclusive OR is carried out on the Ri-1 and the sub-secret key Ki of the current round, and finally S box replacement and P replacement are carried out;

and (4) processing the result of 16 times of iterative transformation by using the inverse permutation IP-1 of the IP permutation, and taking the finally obtained output as the encrypted data to be processed.

Fig. 6 is the DES encryption process schematic diagram in the FPGA module provided in the embodiment of the present invention, as shown in fig. 6, the DES encryption algorithm generates a secret message based on a multi-round key transformation round function and a key plus data operation round function, that is, 16 hardware copies of the round function can be passed, so as to achieve the pipeline processing of deep refinement, and achieve performance optimization. The iterative characteristic of the DES algorithm makes the DES algorithm suitable for adopting the structural design of the assembly line, can realize 16 data blocks are encrypted at the same time, thus raise and encrypt the efficiency.

Step S34, according to the optical interface protocol, convert the encrypted data to be processed into optical interface data, and forward the optical interface data to the corresponding forwarding optical interface.

Further, the method further comprises: and sending the optical port data sent by each receiving optical port to an uplink buffer data queue, and sending an interrupt signal to the computer system when the uplink buffer data queue is not empty, so as to inform the computer system that the received data is ready to be processed.

Specifically, the uplink buffer data queue is set to be in an FIFO mode, and when the optical port data in the uplink buffer data queue meets a preset condition, an interrupt signal is sent to the computer system. The FIFO size and the corresponding preset condition corresponding to each receiving optical port are determined according to the data characteristics of each receiving optical port.

Further, the sending the optical port data sent by each receiving optical port to the uplink buffer data queue includes: and decrypting the optical port data sent by each receiving optical port according to a preset decryption method, and sending the optical port data into an uplink buffer data queue.

The embodiment of the utility model provides a PCIE optical fiber communication switching card, realize PCIE to the switching card of optical fiber communication based on FPGA field programmable logic gate array, encrypt through field programmable logic, both possessed the characteristic of hard encryption, possessed the easy characteristics of upgrading of soft encryption again, communication rate is controllable, the bottom agreement is steerable, can encrypt, PCIE switching card security and flexibility have been improved, can adapt to different application scenes, be particularly useful for the sensitive trade of data security.

The above-described embodiments of the apparatuses and the like are merely illustrative, wherein the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, and not to limit the same; although embodiments of the present invention have been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its various embodiments.

Claims (9)

1. A PCIE fiber communication adapter card is characterized by comprising:

the system comprises a connector, a DCDC power supply, an FPGA module and at least one QSFP interface cage;

the connector is used for taking electricity and connecting the FPGA module into a computer system through PCIE X8;

the FPGA module comprises an FPGA chip and a firmware, the FPGA chip is connected with the at least one QSFP interface cage and the firmware, an FPGA program is stored in the firmware, and the FPGA module is used for carrying out PCIE protocol analysis on the acquired PCIE data stream issued by the computer system, determining data to be processed and determining a forwarding optical port of each data to be processed through route judgment; converting data to be processed into optical interface data according to an optical interface protocol, and forwarding the optical interface data to a corresponding forwarding optical interface;

the DC-DC power supply is connected with the connector and the FPGA module and used for supplying power.

2. The PCIE fiber optic communications adapter card of claim 1, wherein the FPGA module comprises:

and the PCIE interface control sub-module is connected with the connector and is used for realizing the communication control of the PCIE interface and the computer system.

3. The PCIE fiber optic communications adapter card of claim 2, wherein the FPGA module further comprises:

and the downlink buffer queue is connected with the PCIE interface control submodule and is set to be in an FIFO mode.

4. The PCIE fiber optic communications adapter card of claim 3, wherein the FPGA module further comprises:

and the uplink buffer queue is connected with the PCIE interface control submodule and is set to be in an FIFO mode.

5. The PCIE fiber optic communications adapter card of claim 4, wherein the FPGA module further comprises:

and the FIFO state monitoring management submodule is connected with the uplink buffer queue and the downlink buffer queue and is used for configuring and detecting the FIFO state.

6. The PCIE fiber optic communications adapter card of claim 5, wherein the FPGA module further comprises:

and the encryption submodule is connected with the downlink buffer queue and used for encrypting the data to be processed.

7. The PCIE fiber optic communications adapter card of claim 5, wherein the FPGA module further comprises:

and the decryption submodule is connected with the uplink buffer queue and used for decrypting the received optical port data.

8. The PCIE fiber optic communications adapter card of claim 7, wherein the FPGA module further comprises:

and the GTH interface serial-parallel conversion sub-module is connected with each optical port and used for converting parallel data into serial data when transmitting data and converting serial data into parallel data when receiving data.

9. The PCIE fiber optic communications adapter card of any one of claims 1 to 8, wherein the FPGA chip model is V7XC 690T.

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