CN211426703U - Chip detection device - Google Patents
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- CN211426703U CN211426703U CN201922353851.5U CN201922353851U CN211426703U CN 211426703 U CN211426703 U CN 211426703U CN 201922353851 U CN201922353851 U CN 201922353851U CN 211426703 U CN211426703 U CN 211426703U
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Abstract
The utility model provides a chip detection device, include: the detection head comprises a plurality of probes and a communication interface, wherein the probes are used for contacting with terminals of a chip to be detected so as to enable the probes to be in communication connection with the chip to be detected; the communication interface is connected with the probe and is used for realizing the communication between the detection head and the detection host; the detection host comprises a plurality of function detection circuits and a selection circuit, wherein the selection circuit is used for selecting the required function detection circuit to communicate with the detection head, so that the detection host can perform corresponding performance detection on the chip through the detection head. The utility model discloses chip detection device adopts a plurality of function detection circuit and selection circuit matched with mode, and the selection circuit selects corresponding function detection circuit according to the detection demand to realize detecting the different functions of chip.
Description
Technical Field
The utility model relates to a chip detection device especially relates to a chip detection device in printer consumptive material.
Background
Recording apparatuses, such as printers, copiers, and facsimile machines, are used to record information to be recorded on a recording medium, such as paper, through consumables (e.g., ink, toner, etc.). The recording apparatus generally includes a recording apparatus main body and a consumable cartridge. The consumable cartridge is generally detachably mounted on the recording apparatus, and is provided with a consumable chip for marking data information such as consumption or remaining amount of the consumable in the consumable cartridge. Consumable chips are typically removably mounted on a consumable cartridge, and a storage element is provided in the chip to store rewritable data such as consumption or balance of the consumable, as well as other read-only data associated with the consumable cartridge. When the consumable box is installed on the recording device, the chip on the consumable box can be electrically connected with the recording device and exchange data with the recording device.
In the current market, not only original consumable chips produced by original manufacturers but also compatible consumable chips sold by compatible manufacturers are sold, or the performance of the chips may be changed due to the influence of factors such as environmental factors and transportation processes during the period from the chip production to the chip sale; various factors lead to good and uneven performance of consumable chips mounted on the consumable box, and product quality and user benefits cannot be guaranteed. The consumable chip detection equipment in the prior art can only detect whether the written data in the consumable chip is complete or not, cannot detect other performances of the consumable chip, and evaluates the quality of the chip.
SUMMERY OF THE UTILITY MODEL
In view of the above problem, the utility model provides a chip detection device, it can carry out comprehensive detection to the chip performance.
The utility model provides a chip detection device, include: at least one detection head and a detection host,
the detection head comprises a plurality of probes and a communication interface, wherein the probes are used for contacting with terminals of a chip to be detected so as to enable the probes to be in communication connection with the chip to be detected; the communication interface is connected with the probe and is used for realizing the communication between the detection head and the detection host;
the detection host comprises a plurality of function detection circuits and a selection circuit, wherein the selection circuit is used for selecting the required function detection circuit to communicate with the detection head, so that the detection host can perform corresponding performance detection on the chip through the detection head.
Optionally, the detection host further has an information storage unit, and the information storage unit is used for prestoring information of a plurality of different chips.
Optionally, the detection head further includes a configuration storage unit, the configuration storage unit is in communication connection with the communication interface, and the configuration storage unit is used for storing a plurality of communication protocols and/or a plurality of electrically defined arrangement modes of the terminals.
Optionally, the configuration storage unit is further configured to temporarily store the detection result of the detected chip.
Optionally, the plurality of function detection circuits include any two or more combinations of a terminal electrical definition detection circuit, a communication protocol detection circuit, a read/write function detection circuit, a data acquisition circuit, a power consumption detection circuit, a frequency detection circuit, a chip maximum/low operating voltage detection circuit, or a protection capability detection circuit.
Optionally, the detection host is configured to comprehensively score the performance of the detected chip according to the performance detection results of the plurality of function detection circuits.
Optionally, the detection host further includes an input interface and an output interface;
the input interface is used for receiving the performance of a chip which needs to be detected by a user, so that the selection circuit selects the corresponding function detection circuit and executes detection operation through the detection head;
the output interface is used for receiving the detection result of the detection head and displaying the detection result on the detection host.
Optionally, the input interface is connected with a key unit on the detection host, and a user selects a detection requirement through the key unit; the output interface is connected with a display screen on the detection host, and the display screen is used for displaying the detection result;
or the input interface and the output interface are connected with a touch display screen on the detection host, and the touch display screen can be used for a user to select a detection requirement and can display a detection result.
Optionally, the detection head and the detection host establish a communication connection through wired communication or wireless communication.
The utility model discloses chip detection device adopts a plurality of function detection circuit and selection circuit matched with mode, and the selection circuit selects corresponding function detection circuit according to the detection demand to realize detecting the different functions of chip. Therefore, the utility model discloses can carry out comprehensive detection and evaluation to the performance of chip, be favorable to improving the quality of product comprehensively.
Drawings
Fig. 1 is a diagram illustrating a detection circuit according to an embodiment of the chip detection apparatus of the present invention;
fig. 2 is an internal circuit module structure of an embodiment of the chip detection apparatus of the present invention;
FIG. 3 is an external structure of an embodiment of the chip detection apparatus of the present invention;
fig. 4 is a circuit for electrically defining and detecting terminals according to an embodiment of the chip detection device of the present invention;
fig. 5 shows an internal circuit structure of a voltage detection circuit according to an embodiment of the chip detection apparatus of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
As shown in fig. 1, an embodiment of the present invention provides a chip detection apparatus, including: at least one inspection head 1 and an inspection master 2,
the detection head 1 comprises a plurality of probes 11 and a communication interface, wherein the probes 11 are used for contacting with terminals of a chip to be detected so as to enable the probes 11 to be in communication connection with the chip to be detected; the communication interface is connected with the probe 11 and is used for realizing the communication between the detection head 1 and the detection host machine 2;
the detection host 2 comprises a plurality of function detection circuits 26 and a selection circuit 24, and the selection circuit 24 is used for selecting the required function detection circuit 26 to communicate with the detection head 1, so that the detection host 2 performs performance detection on the chip through the detection head 4.
As an optional implementation manner of this embodiment, the plurality of function detection circuits 26 include a terminal electrical definition detection circuit 261, a communication protocol detection circuit 262, a read-write function detection circuit 263, a data acquisition circuit 264, a power consumption detection circuit 265, a frequency detection circuit 266, a chip maximum/low voltage detection circuit 267, and a protection capability detection circuit 268. Of course, the present embodiment does not limit the scope of the present invention, and in other embodiments, any two or more functional modules among the above-described function detection modules may be selected.
In this embodiment, the selection circuit 24 is adopted to select the function detection circuit, so that the chip detection apparatus of this embodiment adopts a mode that a plurality of function detection circuits are matched with the selection circuit 24, and the selection circuit 24 selects the corresponding function detection circuit according to the detection requirement, thereby detecting different functions of the chip. Therefore, the performance of the chip can be comprehensively detected and evaluated, and the quality of the product can be comprehensively improved.
The detection host needs to establish communication connection with the chip to be detected, for example, as shown in fig. 3, the chip detection apparatus further includes a detection head 1, where the detection head 1 includes a plurality of probes 11 and a communication interface in communication connection with the probes 11;
the probes 11 are used for contacting with the detection terminals of the tested chip and establishing communication connection.
The detection head 1 and the detection host machine 2 are in communication connection in a wired communication or wireless communication mode, wherein the wired communication is that the detection head and the detection host machine are in communication connection through a signal line, and the wireless communication is that the detection head and the detection host machine are in communication connection through Bluetooth, RFID and the like.
The detection head 1 establishes communication connection with the detected chip by adopting a mode of contacting with the probe 11, and has the advantage that the connection can be realized conveniently and quickly by adopting the connection mode. However, this connection method is not limited to the present invention, and any other method capable of realizing communication connection may be adopted.
Specifically, as shown in fig. 2, the internal circuit module structure of the chip detection device is provided, in which the detection head 1 includes: a stylus unit 11 and a communication interface 12, the communication interface 12 being provided in an internal circuit configuration of the detection head 1; the communication interface 12 is connected with the plurality of contact pins 11 and the internal circuit of the host 2, the plurality of contact pins 11 can be in one-to-one contact with the terminals of the chip, and after the communication interface 12 receives a detection instruction sent from the host 2, the communication is realized with the chip through the plurality of contact pins 11, the detection is completed, and the detection result is fed back to the host 2. As an optional implementation manner of this embodiment, the internal circuit of the detection head 1 further includes a configuration storage unit 13, the configuration storage unit 13 may be used to store information such as a plurality of different communication protocols and a plurality of electrical defined arrangement manners of the terminals, the communication interface 12 is connected to the plurality of contact pins 11, the configuration storage unit 13 and the internal circuit of the host 2, respectively, after receiving the detection instruction sent from the host 2 side, the communication interface 12 calls the required data or program from the configuration storage unit 13 to communicate with the chip via the plurality of contact pins 11, complete the detection and feed back the detection result to the host 2.
As an optional implementation manner of this embodiment, the host 2 further includes a display screen 21 and a key unit 22 provided outside, and an input interface 23, a selection circuit 24, an information storage unit 25, a detection circuit 26, and an output interface 27 provided in an internal circuit module. The key unit 22 is connected with the input interface 23, and when a user presses a corresponding key of the chip performance to be detected, the input interface 23 converts the key into an electric signal and sends the electric signal to the selection circuit 24 connected with the input interface; the selection circuit 24 is respectively connected with the information storage unit 25 and the detection circuit 26, wherein the information storage unit is pre-stored with information of a user model corresponding to the chip model, a corresponding manufacturer and the like, the detection circuit 26 comprises a plurality of circuits for detecting different chip performances, the selection circuit 24 selects the corresponding detection circuit 26 according to the electric signals to detect the chip through the detection head 1, the detection head 1 feeds back the detection result to the output interface 27, and the output interface 27 is connected with the display screen 21, so that the detection result is displayed on the display screen. Further, the host computer may also perform comprehensive scoring according to the detected performance results and display the comprehensive scoring on the display screen 21. In the present embodiment, the display screen 21 is disposed outside the detection host as a display module, but this method is not exclusive, and other methods may also be adopted, for example, an external display device may also be adopted to perform display, or projection display, and the like. The key unit 22 is used as the input module of the present embodiment, and similarly, this manner is not unique, and other modules capable of completing information input, such as a keyboard or a touch screen, may also be used as the input module.
Through the chip detection device in this embodiment, can detect the multiple different performance of chip to can carry out comprehensive score according to the different performance results of chip, be convenient for assess the quality of chip, detach the chip that the quality is not good, leave the better chip of quality, with the benefit of guaranteeing the user.
The detection process of each function detection circuit described above is specifically described as follows:
the terminal electrically defines the detection circuit: as shown in fig. 4, for convenience of description, in the present embodiment, the chip has five terminals, namely VCC (power supply terminal), GND (ground terminal), RST (reset terminal), CLK (clock terminal), and SDK (data terminal), the communication interface 12 includes an MCU and analog printer-side corresponding terminals to input VCC, GND, RST, CLK, and SDK modules with corresponding timings, each of the illustrated modules is connected to each probe 11, that is, the VCC, GND, RST, CLK, and SDK modules in the communication interface 12 input signals to the VCC, GND, RST, CLK, and SDK terminals of the chip through the probes 11.
The probes 11 of the plurality of detection heads 1 can be in one-to-one corresponding contact with the terminals of the chip to be detected, but the electrical definition arrangement sequence of the probes 11 of each detection head 1 is different. The selection circuit 24 receives the terminal electrical definition detection circuit 261 in the command conduction detection circuit 26, when the communication interface 12 receives the command of detecting the electrical definition of the terminal, it sends a command to the chip to determine whether the chip can work normally, if so, it indicates that the electrical definition arrangement sequence of the probe of the detection head 1 used is consistent with the electrical definition arrangement sequence of the chip terminal, and sends the electrical definition arrangement sequence of the detection head 1 to the output interface 21 of the host computer, and displays it on the display screen 27; if the host 2 displays information indicating communication abnormality or the like, the other detection heads are replaced until the host 2 indicates communication normality and returns to the terminal definition arrangement order.
Alternatively, as shown in fig. 4, another implementation of the electrically defined detection circuit is shown. When the user selects the electrical definition of the detection terminal through the detection host 2, the selection circuit 24 receives the command to turn on the terminal electrical definition detection circuit 261 in the detection circuit 26, when the communication interface 12 receives the command of the electrical definition of the detection terminal, the prestored multiple terminal electrical definition arrangement sequences are read from the configuration storage unit 13, the MCU correspondingly turns on the corresponding probes 11 according to each electrical definition arrangement sequence, and inputs corresponding signals to the chip, and when the electrical definition arrangement sequences are consistent with the actual terminal electrical definition arrangement sequences of the chip, that is, the detection is passed, the MCU sends the corresponding electrical definition arrangement sequences to the output interface 21 of the host and displays the corresponding electrical definition arrangement sequences on the display screen 27. This implementation may reduce the number of detection heads that need to be configured.
Since the electrical definitions of the chip terminals are required to be known in advance for the other circuit performance detection circuits, when detecting the performance of the same chip, the detected electrical definition sequence of the chip terminals is temporarily stored in the configuration storage unit 13, and each subsequent chip performance detection circuit detects the chip based on the temporarily stored electrical definition sequence of the terminals. The detection head is judged to be the same chip in the time period from the contact of the detection head to the separation of the detection head from the chip, if the detection head detects no chip contact, the electrical definition sequence of the chip terminals temporarily stored in the configuration storage unit 13 is deleted, so that the detection speed of the host can be improved, and the electrical definition sequence of the terminals does not need to be determined in each performance detection.
Communication protocol detection circuitry: the configuration storage unit 13 stores therein various communication protocol programs, such as IIC, SPI, parallel interface (I/O), DMA, and other communication protocols. When the user selects the communication protocol of the detection chip through the detection host 2, the selection circuit 24 receives the instruction to turn on the communication protocol detection circuit 262 in the detection circuit 26, and when the communication interface 12 receives the instruction to detect the communication protocol of the chip, the communication protocol program and the determined terminal electrical definition sequence are read from the configuration storage unit 13, different communication protocols are sent to the chip through the data communication terminal, and when the chip can normally work under a certain communication protocol, the protocol is sent to the output interface 21 of the host and displayed on the display screen 27.
Since the following circuit performance detection circuits all need to know the communication protocol of the chip in advance, when detecting the performance of the same chip, the detected communication protocol is temporarily stored in the configuration storage unit 13, and each subsequent chip performance detection circuit operates the chip according to the temporarily stored communication protocol. The detection head is judged to be the same chip in the time period from the contact with a certain chip to the separation from the chip, if the detection head detects no chip contact, the communication protocol temporarily stored in the configuration storage unit 13 is deleted, so that the detection speed of the host can be improved, and the communication protocol of the chip is not required to be determined in advance during each performance detection.
Read-write function detection circuitry: when a user selects the read-write function of the detection chip through the detection host 2, the selection circuit 24 receives the instruction to turn on the read-write function detection circuit 263 in the detection circuit 26, the read-write function detection circuit 263 sends a read instruction to the communication interface 12, the communication interface 12 reads the determined terminal electrical definition sequence and the communication protocol program from the configuration storage unit 13, the read instruction is sent to the chip through the data communication terminal, whether the chip responds or not is judged, the judgment result is fed back to the output interface 27, and if the read function is normally displayed on the display screen, the read function is displayed on the display screen, otherwise, the read function is displayed abnormally; when the write function is detected, the time from the time when the chip receives the write command to the time when the response of the write command is completed is judged, whether the response time is within a preset time range or not is judged, the judgment result is fed back to the output interface 27, if the response time is within the preset time range, the 'write function normal' is displayed on the display screen, and the 'write function abnormal' is displayed in an irregular mode;
a data acquisition circuit: when the user selects to obtain the data inside the chip through the detection host 2, the selection circuit 24 receives the instruction to turn on the data obtaining circuit 264 in the detection circuit 26, the data obtaining circuit 264 sends a read instruction to the communication interface 12, the communication interface 12 reads the determined terminal electrical definition sequence and the communication protocol program from the configuration storage unit 13, the read instruction is sent to the chip through the data communication terminal, the chip returns the basic information of the chip to the communication interface 12 through the data communication terminal, the basic information of the chip comprises the model number, the production date, the serial number and the like of the chip, and the communication interface returns the basic information obtained from the chip to the data obtaining circuit 264. The information storage unit 25 is pre-stored with information such as printer model and corresponding manufacturer corresponding to each chip model, and the data acquisition circuit 264 acquires corresponding signals from the information storage unit 25 according to the chip model, and then sends the signals to the output interface 27 and displays the signals on the display screen 21.
The power consumption detection circuit: the power consumption detection circuit 265 is divided into a static power consumption detection circuit and a dynamic power consumption detection circuit.
When the static power consumption of the chip is detected, the static power consumption detection circuit sends an instruction for detecting the static power consumption of the chip to the communication interface 12, after the communication interface receives the instruction, the MCU in the communication interface 12 conducts the VCC module and the probe corresponding to the VCC terminal of the chip, the probes corresponding to the other terminals of the chip are all conducted with the GND module, the voltage and the current at the VCC end of the chip are detected at the moment, and the static power consumption is calculated, wherein the smaller the static power consumption, the better the performance of the chip is.
When the dynamic power consumption of the chip is detected, the dynamic power consumption detection circuit sends a chip dynamic power consumption detection instruction to the communication interface 12, the communication interface 12 reads the determined terminal electrical definition sequence and the communication protocol program from the configuration storage unit 13, the MCU in the communication interface 12 conducts the probes of the modules and the corresponding terminals of the chip, sends the instruction to the chip, detects the voltage and the current of the VCC end of the chip in a normal working state, and calculates the dynamic power consumption, wherein the smaller the dynamic power consumption, the better the performance of the chip.
A frequency detection circuit: when the user selects the operating frequency of the detection chip through the detection host 2, the selection circuit 24 receives the instruction to turn on the frequency detection circuit 266 in the detection circuit 26, the frequency detection circuit 266 uses different frequencies to send the instruction to the chip through the communication interface 12, judges whether the chip can normally operate, determines the frequency range in which the chip can normally operate, and the larger the frequency range in which the chip normally operates, the better the performance, and divides the frequency range into "excellent", "good" and "normal" according to the operating frequency range in which the chip can adapt, and displays the frequency range on the display screen 21.
A voltage detection circuit: when the user selects the operating voltage of the detection chip through the detection host 2, the selection circuit 24 receives the instruction to turn on the voltage detection circuit 267 in the detection circuit 26, as shown in fig. 5, which is a schematic circuit diagram of the voltage detection circuit 267, and only 4 levels of resistors are listed in the diagram, and the resistors can be increased or decreased in the actual application process, and the value of the resistor R connected in the circuit is changed by controlling the switch S, and the voltage detection circuit 267 provides different voltages to the VCC terminal of the chip through the communication interface 12, and sends a command to the chip under different voltages, and determines the highest voltage and the lowest voltage at which the chip can normally operate, and the larger the voltage range at which the chip normally operates is, the better the performance is, and the operating voltage range at which the chip can adapt is divided into "excellent", "good" and "normal", and displayed on the display screen 21.
Protection capability detection circuit: the protection capability detection circuit 268 may include various circuits such as an over-current protection circuit, an over-voltage protection circuit, a temperature protection circuit, an electrostatic protection circuit, etc., and the embodiment takes over the detection of the over-voltage protection capability as an example.
The protection capability detection circuit 268 firstly obtains the highest working voltage of the chip through the voltage detection circuit 267, applies a voltage larger than the highest working voltage to the VCC terminal of the chip through the communication interface 12, then recovers to the normal working voltage, sends an instruction to the chip at this time, and judges whether the chip can normally work, if so, the overvoltage protection capability of the chip is good.
The chip detection device of the embodiment adopts a mode that a plurality of function detection circuits are matched with the selection circuit, and the selection circuit selects the corresponding function detection circuit according to the detection requirement, so that the detection of different functions of the chip is realized. The host may simultaneously execute the detection functions of the plurality of function detection circuits. Therefore, the performance of the chip can be comprehensively detected and evaluated, and the quality of the product can be comprehensively improved.
The above description is only for the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A chip detection apparatus, comprising: at least one detection head and a detection host,
the detection head comprises a plurality of probes and a communication interface, wherein the probes are used for contacting with terminals of a chip to be detected so as to enable the probes to be in communication connection with the chip to be detected; the communication interface is connected with the probe and is used for realizing the communication between the detection head and the detection host;
the detection host comprises a plurality of function detection circuits and a selection circuit, wherein the selection circuit is used for selecting the required function detection circuit to communicate with the detection head, so that the detection host can perform corresponding performance detection on the chip through the detection head.
2. The chip detection apparatus according to claim 1, wherein: the detection host is also provided with an information storage unit, and the information storage unit is used for prestoring information of various different chips.
3. The chip detection apparatus according to claim 1, wherein: the detection head also comprises a configuration storage unit, the configuration storage unit is in communication connection with the communication interface, and the configuration storage unit is used for storing a plurality of communication protocols and/or a plurality of electrical definition arrangement modes of terminals.
4. The chip detection apparatus according to claim 3, wherein: the configuration storage unit is also used for temporarily storing the detection result of the detected chip.
5. The chip detection device according to any one of claims 1 to 3, wherein: the plurality of function detection circuits include any two or more combinations of a terminal electrical definition detection circuit, a communication protocol detection circuit, a read-write function detection circuit, a data acquisition circuit, a power consumption detection circuit, a frequency detection circuit, a chip maximum/low working voltage detection circuit, or a protection capability detection circuit.
6. The chip detection apparatus according to claim 5, wherein: the detection host is used for comprehensively scoring the performance of the detected chip according to the performance detection results of the plurality of function detection circuits.
7. The chip detection apparatus according to claim 5, wherein: the detection host further comprises an input interface and an output interface;
the input interface is used for receiving the performance of a chip which needs to be detected by a user, so that the selection circuit selects the corresponding function detection circuit and executes detection operation through the detection head;
the output interface is used for receiving the detection result of the detection head and displaying the detection result on the detection host.
8. The chip detection apparatus according to claim 7, wherein: the input interface is connected with a key unit on the detection host, and a user selects a detection requirement through the key unit; the output interface is connected with a display screen on the detection host, and the display screen is used for displaying the detection result;
or the input interface and the output interface are connected with a touch display screen on the detection host, and the touch display screen can be used for a user to select a detection requirement and can display a detection result.
9. The chip detection apparatus according to claim 1, wherein: and the detection head and the detection host machine are in communication connection in a wired communication or wireless communication mode.
10. The chip detection apparatus according to claim 1, wherein: the detected chip is a printing consumable chip and is used for storing relevant information of consumables.
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| CN201922353851.5U CN211426703U (en) | 2019-12-23 | 2019-12-23 | Chip detection device |
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| CN201922353851.5U CN211426703U (en) | 2019-12-23 | 2019-12-23 | Chip detection device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113419160A (en) * | 2021-06-18 | 2021-09-21 | 珠海美佳音科技有限公司 | Chip detection interface circuit |
| CN113625155A (en) * | 2021-08-11 | 2021-11-09 | 湖南省计量检测研究院 | Multifunctional communication chip detection system based on big data |
-
2019
- 2019-12-23 CN CN201922353851.5U patent/CN211426703U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113419160A (en) * | 2021-06-18 | 2021-09-21 | 珠海美佳音科技有限公司 | Chip detection interface circuit |
| CN113419160B (en) * | 2021-06-18 | 2023-09-29 | 珠海美佳音科技有限公司 | Chip detection interface circuit |
| CN113625155A (en) * | 2021-08-11 | 2021-11-09 | 湖南省计量检测研究院 | Multifunctional communication chip detection system based on big data |
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Address after: 519060 building 01, 83 Guangwan street, Xiangzhou District, Zhuhai City, Guangdong Province Patentee after: Jihai Microelectronics Co.,Ltd. Address before: 519060 building 01, 83 Guangwan street, Xiangzhou District, Zhuhai City, Guangdong Province Patentee before: APEX MICROELECTRONICS Co.,Ltd. |