CN211236252U - Anti-broadband interference Beidou vehicle-mounted all-in-one machine - Google Patents

Anti-broadband interference Beidou vehicle-mounted all-in-one machine Download PDF

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CN211236252U
CN211236252U CN201920338695.2U CN201920338695U CN211236252U CN 211236252 U CN211236252 U CN 211236252U CN 201920338695 U CN201920338695 U CN 201920338695U CN 211236252 U CN211236252 U CN 211236252U
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interference
signals
processing
radio frequency
power supply
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王秀军
黄芳
陈恺
戚龙星
李涛
佘波
赵娟
武秋娜
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Jiangsu Radio Factory Co ltd
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Jiangsu Radio Factory Co ltd
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Abstract

The utility model provides an anti-broadband interference Beidou vehicle-mounted all-in-one machine, which comprises a host and a cable, wherein the host comprises an anti-interference antenna array element, a receiving channel module, a power amplifier/combiner, an anti-interference module, a transmitting filter, a baseband signal processing board, a power information board, a power filter and the like; the utility model discloses a core is anti-interference module, and this anti-interference module adopts frequency domain narrowband interference suppression and the cascaded mode of time self-adaptation trapped wave processing, carries out frequency domain narrowband interference suppression to intermediate frequency signal respectively promptly earlier, carries out time self-adaptation processing again with the trapped wave result again, suppresses the broadband interference. The method balances factors in multiple aspects such as anti-interference performance, system complexity, reliability, power consumption and the like, has the capability of simultaneously resisting narrow-band interference and multiple broadband interference, up-converts signals after interference cancellation into radio frequency signals, and then can process the navigation signals according to a conventional method.

Description

Anti-broadband interference Beidou vehicle-mounted all-in-one machine
Technical Field
The utility model belongs to the technical field of satellite communication, specific be applied to an anti broadband interference big dipper on-vehicle all-in-one that says so.
Background
The BeiDou Navigation Satellite System (BeiDou Navigation Satellite System) is a global Navigation Satellite System which is implemented, independently researched and developed and completely independently operated in China, and obtains more and more attention at home and abroad by virtue of the advantages of wide service range, accurate positioning, good Navigation real-time performance and the like. The Beidou second generation satellite navigation and positioning system is a dual-band ranging system, breaks through the monopoly of the United states and Russia on global navigation and positioning, and can play a vital role in the fields of national defense safety, economic construction and the like of China along with the continuous improvement of the system.
The existing large-scale Beidou vehicle-mounted all-in-one machine in the current market does not have an anti-interference function, and can realize functions of RNSS positioning, time service, communication and the like. However, due to the very weak characteristic of the Beidou signal, the Beidou receiver is easily interfered by external narrow-band signals and broadband signals or intentionally by enemies, so that the Beidou receiver fails; the core of the problem is that the Beidou vehicle-mounted integrated machine does not have an anti-interference function, can not identify correct Beidou information under the condition of interference, and identifies and rejects noise and interference signals.
SUMMERY OF THE UTILITY MODEL
To foretell problem, the utility model discloses the on-vehicle all-in-one of anti-interference big dipper can realize anti broadband interference function, can anti B3 frequency point and each 3 broadband interferences of S frequency point, and the interference covers B3 and S frequency point 100% bandwidth, and B3 frequency point interference-to-signal ratio is not less than 70dB, and S frequency point interference-to-signal ratio is not less than 60 dB.
In order to realize the purpose, the utility model discloses a technical scheme is: the Beidou satellite vehicle-mounted all-in-one machine with the function of resisting broadband interference comprises an anti-interference antenna array element, a receiving channel module, a power amplifier/combiner, an anti-interference module, a transmitting filter, a baseband signal processing board, a power supply information board and a power supply filter; wherein the content of the first and second substances,
the anti-interference antenna array element receives satellite navigation positioning radio frequency signals;
the anti-interference module adopts a processing mode of cascade connection of frequency domain narrow-band interference suppression and space-time adaptive notch processing to up-convert the signal after interference cancellation into a radio frequency signal, and then processes the radio frequency signal according to a conventional method;
the power amplifier/combiner module has a power amplification function for RDSS-L transmitting signals, a transmitting aluminum foil device is arranged in the power amplifier/combiner module, and RDSS-L transmitting radio frequency signals are sent to an anti-interference antenna to finish power amplification and transmission;
the baseband signal processing board performs centralized processing on the positioning radio frequency signal, extracts various observed quantities after down-conversion, digitization and baseband signal processing of a radio frequency front end, completes tasks of capturing, tracking, navigation message demodulation and time difference measurement of a received signal and further completes PVT resolving;
a power supply on the power supply information board is directly fed into the power amplifier through the power supply module, and a transmitting channel is opened while transmitting is realized through transmitting enabling;
and the power supply module converts an external power supply into a power supply on the power supply information board.
Furthermore, the satellite navigation positioning radio frequency signals received by the anti-interference antenna array element are satellite navigation positioning radio frequency signals of RNSS-B1, RNSS-B3 and RDSS-S frequency points, and the two navigation radio frequency signals of RDSS-S and RNSS-B3 are received by a four-array element receiving array antenna respectively.
The utility model provides an anti-interference method of above-mentioned on-vehicle all-in-one machine, 4 way intermediate frequency analog signal of every frequency point of S and B3 frequency point that antenna array element was received is digital intermediate frequency signal through AD conversion, get into anti-interference processing unit, restrain narrowband interference earlier, then carry out space-time joint adaptive filtering with 4 passageway digital intermediate frequency signals after the narrowband restraines, restrain broadband interference, then handle through digital AGC, form the invariable digital baseband signal of range, through DA conversion intermediate frequency analog signal, then carry out the up-conversion, and export for the baseband signal processing board. The antenna directional diagram is controlled by adjusting the weight of each unit of the antenna array, and the anti-interference antenna simultaneously generates null in a plurality of interference directions, so that the effective suppression of interference is realized.
Further, the suppression of the wideband interference suppression by performing space-time joint adaptive filtering on the 4-channel digital intermediate-frequency signal after the narrowband suppression is divided into two cases: the method comprises the steps of a constrained space-time self-adaptive processing algorithm and an unconstrained space-time self-adaptive processing algorithm, wherein the unconstrained space-time self-adaptive algorithm does not need any priori knowledge, so that a gain zero point points to an interference incoming direction, and when the outside has no interference, a nearly uniform hemispherical gain directional diagram is established; the constrained space-time adaptive algorithm needs the position information of a known satellite, the position information of a satellite receiver and the attitude information of a receiving antenna, so that an antenna array generates a plurality of narrow beams which respectively point to and track each target satellite, and meanwhile, the zero point of an antenna directional diagram still points to the external interference incoming direction.
Further, the specific process of the constrained space-time adaptive processing algorithm is as follows:
first, the following algorithm model is constructed: setting M array elements in total for the antenna array, arranging an N-order FIR filter behind each array element channel, and inputting signals { w ] of each tap of the FIR filtermnM is 1,2, and M, N is 1,2, and N is a space-time two-dimensional weight coefficient;
let the received signals of M array elements be respectively represented as x1(n),...,xM(n), then the input signal of each tap of FIR after array element m is xm1(n)=xm(n),xm2(n)=xm(n-1),……,xmN(n)=xm(n-N+1);
With X representing the input signal matrix as
X=[x11,x12,...,x1N,x21,x22,...,x2N,...,xM1,xM2,...,xMN]T(1)
The weight vector is represented by MN x 1 dimensional vector w, then
w=[w11,w12,...,w1N,w21,...,w2N,...,wM1,...,wMN]T(2)
The covariance matrix of each array element received data is denoted as R ═ E [ XX ═ XXH]The minimum variance criterion, constrained by linearity, is described as the following optimization problem
Figure DEST_PATH_GDA0002543754400000021
If omegas,ωtRespectively representing a spatially normalized frequency and a temporally normalized frequency,
Figure DEST_PATH_GDA0002543754400000024
representing the ronecker product (Kronecker product), the space-time two-dimensional steering vector S can be written as:
Figure DEST_PATH_GDA0002543754400000022
wherein the space guide vector SsAnd a time-oriented vector StRespectively expressed as:
Figure DEST_PATH_GDA0002543754400000023
Figure DEST_PATH_GDA0002543754400000031
the optimal solution of the formula (6) is that the output signal-to-interference-and-noise ratio is maximum, and the solution of the optimal space-time processor is deduced by utilizing a Lagrange multiplier method
Figure DEST_PATH_GDA0002543754400000032
Solving the above formula by using a self-adaptive method;
then, setting K constraints, selecting K to be the same as the number N of the channel delay units, and obtaining a kth constraint equation as follows:
Figure DEST_PATH_GDA0002543754400000033
the kth constraint is when the angular frequency is ωkUnit plane wave of thetakWhen incident on the array, the output of the array is bkThe minimum variance LCMV optimization equation with K linear constraints is:
Figure DEST_PATH_GDA0002543754400000034
wherein the constraint matrix C ═ C1,c2,...,cK]The output response vector b ═ b1,b2,...,bK]T
The solution of the multi-constraint minimum variance processor can be deduced by utilizing the Lagrange multiplier method
wopt=R-1C(CHR-1C)-1b (11);
R is represented as follows:
Figure DEST_PATH_GDA0002543754400000035
r is written in the form of M × M sub-arraysEach sub-array containing N × N elements, and sub-arrays on the main diagonal
Figure DEST_PATH_GDA0002543754400000036
Figure DEST_PATH_GDA0002543754400000037
Are all Toeplitz matrices of the Hermite type, using correlation matrices
Figure DEST_PATH_GDA0002543754400000038
The above properties of (a) simplify the process.
Further, the optimization criterion of the unconstrained space-time adaptive algorithm is to minimize the filter output power, i.e. to minimize the filter output power
Figure DEST_PATH_GDA0002543754400000039
The specific process is as follows:
first, the following algorithm model is constructed: setting the antenna array to have M array elements, the first array element channel as main channel, the second to M channels as auxiliary channels, each auxiliary channel being followed by an N-order FIR filter to make the input signal x1(n),...,xM(n), then the input signal of each tap of FIR after array element m is xm1(n)=xm(n),xm2(n)=xm(n-1),……,xmN(n)=xm(n-N+1);
With X representing the input signal matrix as
X=[x1,x21,x22,...,x2N,...,xM1,xM2,...,xMN]T(16)
The filter coefficients are denoted wmnM2, M, N1, 2, N is a space-time two-dimensional weight coefficient, and the processor weight vector is represented by an MN × 1-dimensional vector w, then
W=[w21,...,w2N,...,wM1,...,wMN]T(17)
The optimization criteria can be summarized as the following unconstrained optimization problem:
Figure DEST_PATH_GDA0002543754400000041
in the formula X1=x1(n),
Figure DEST_PATH_GDA0002543754400000042
Data length of L, X1Is a vector of 1 × L and,
Figure DEST_PATH_GDA0002543754400000043
Pouttaking the best weight W of the minimumoptCan be composed ofoutThe gradient for W is found to be zero:
Figure DEST_PATH_GDA0002543754400000044
to obtain WoptThe equation to be satisfied is
Figure DEST_PATH_GDA0002543754400000045
The above formula is called normal equation; when in use
Figure DEST_PATH_GDA0002543754400000046
When full rank, the normal equation has a unique solution
Figure DEST_PATH_GDA0002543754400000047
The optimal solution is the optimal solution of the unconstrained space-time adaptive algorithm;
will be provided with
Figure DEST_PATH_GDA0002543754400000048
Expressed in the following form:
Figure DEST_PATH_GDA0002543754400000049
Figure DEST_PATH_GDA0002543754400000051
written in the form of (M-1) × (M-1) sub-arrays, each sub-array comprising N × N elements, using a correlation matrix
Figure DEST_PATH_GDA0002543754400000052
The above properties of (a) simplify the process.
Further, the specific process of frequency domain narrowband interference suppression is as follows:
firstly, performing FFT (fast Fourier transform) on an input time domain signal;
secondly, windowing is carried out on the signals obtained after conversion, and then DFT conversion is carried out;
and finally, carrying out interference detection in a frequency domain, and carrying out inverse transformation IDFT after interference spectral line processing to weaken and inhibit narrow-band interference.
The utility model also provides an anti-interference module for anti-broadband interference Beidou vehicle-mounted all-in-one machine, which comprises a digital signal acquisition unit, an anti-interference processing unit, an anti-interference filtering unit, an interface communication unit and a power supply unit; an anti-interference intermediate frequency unit is adopted to receive 4 paths of RDSS S intermediate frequency analog signals and 4 paths of RNSS B3 intermediate frequency analog signals, the digital signal acquisition unit is used for realizing analog signal digitization and sending the digitized signals to an anti-interference processing unit, and the anti-interference processing unit is used for realizing anti-interference operation according to the received digital signals; the anti-interference filtering unit realizes the space-time domain filtering processing of signals;
the interface communication unit realizes the output of the debugging information interface of the anti-interference processing unit, and the power supply unit realizes the conversion and distribution of all power supplies on the board.
Furthermore, the anti-interference processing unit adopts a processing mode of cascade connection of frequency domain narrow-band interference suppression and space-time adaptive notch processing, up-converts the signals after the interference cancellation into radio frequency signals, and then processes the radio frequency signals according to a conventional method.
The utility model discloses following beneficial effect has:
compared with the prior art, the utility model discloses a core technology is self-adaptation processing (STAP) algorithm, and self-adaptation processing (STAP) algorithm makes the interference suppression go on in space-time two-dimensional space through space-time joint processing multi-array element (airspace) and a plurality of time domain received data. The technology can effectively separate the target and the interference by utilizing the mutual independence of the interference and the useful signal space angle, thereby realizing the filtering. The space-time self-adaptive processing technology overcomes the defects of airspace filtering, and improves the freedom degree of the array surface on the premise of not increasing array elements.
Based on above-mentioned algorithm, the utility model provides an anti-interference module and on-vehicle all-in-one can realize anti broadband interference function, can anti B3 frequency point and each 3 broadband interferences of S frequency point, and the interference covers B3 and S frequency point 100% bandwidth (interfering signal and signal arrival are not less than 30 °), and B3 frequency point interference-to-signal ratio is not less than 70dB, and S frequency point interference-to-signal ratio is not less than 60 dB. Compared with the prior Beidou vehicle-mounted all-in-one machine, the Beidou vehicle-mounted all-in-one machine has greater practicability progress, and can provide positioning, navigation, communication and other services based on the Beidou satellite for users in an interference environment.
Drawings
FIG. 1 is a functional block diagram of a navigation device;
FIG. 2 is a schematic diagram of a time domain power detection method;
FIG. 3 is a block diagram of the anti-interference processing unit (taking a single frequency point as an example);
FIG. 4 is a schematic diagram of the hardware structure of the anti-interference processing unit of the present invention;
FIG. 5 is a configuration connection circuit diagram;
FIG. 6 is a diagram of the structure of chip AD 9653;
FIG. 7 is a block diagram of an ADC input analog signal conditioning circuit;
FIG. 8 is a block diagram of an input analog signal conditioning circuit;
FIG. 9 is a functional block diagram of a chip AD 9707;
FIG. 10 is a block diagram of a DAC output signal conditioning circuit;
FIG. 11 is a diagram of a model structure of a constrained space-time adaptive algorithm;
FIG. 12 is a diagram of an unconstrained space-time algorithm model;
FIG. 13 is a schematic diagram of the structure of the tamper resistant module;
fig. 14 is a frequency domain narrowband interference suppression schematic;
fig. 15 is a diagram of a DFT based narrowband interference suppression algorithm;
fig. 16 is a diagram of a commonly used window function time domain waveform and its power spectrum.
Detailed Description
The technical solution of the present invention will now be fully described with reference to fig. 1-16. The following description is merely exemplary of some, but not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of the present invention.
Example 1
The utility model provides an anti-interference big dipper vehicle-mounted all-in-one, it adopts integral type structural design, comprises host computer and cable, comprises anti-interference antenna array element, receiving channel module, power amplifier/combiner, anti-interference module, transmitting filter, baseband signal processing board, power information board, power filter etc. in the host computer.
The anti-interference antenna array element receives radio frequency signals of frequency point satellite navigation positioning such as RNSS-B1, RNSS-B3 and RDSS _ S, the two navigation radio frequency signals of RDSS-S and RNSS-B3 are respectively received by a four-array element receiving array antenna, are amplified by a Low Noise Amplifier (LNA), and then are converted into analog intermediate frequency signals after primary down-conversion, band-pass filtering, amplification and automatic gain control of the four navigation signals.
The method comprises the steps that 4 paths of intermediate frequency analog signals of each frequency point of S and B3 frequency points received by an antenna array element are converted into digital intermediate frequency signals through A/D, the digital intermediate frequency signals enter an anti-interference processing unit, narrowband interference is firstly suppressed, space-time combined adaptive filtering is carried out on the 4-channel digital intermediate frequency signals after narrowband suppression, broadband interference is suppressed, digital AGC processing is carried out, digital baseband (I/Q) signals with constant amplitude are formed, the intermediate frequency analog signals are converted through D/A, then up-conversion is carried out, and the signals are output to a baseband signal processing board. The antenna directional diagram is controlled by adjusting the weight of each unit of the antenna array, and the anti-interference antenna simultaneously generates null in a plurality of interference directions, so that the effective suppression of interference is realized, and the output signal-to-interference-and-noise ratio is improved. It should be noted that since the narrowband interference may be in the same direction as the useful signal, if a null is formed directly in the interference direction, the useful satellite signal in that direction will be suppressed together. In order to solve the problem, a mode of cascading frequency domain narrowband interference suppression and space-time adaptive notch processing is needed, namely, frequency domain narrowband interference suppression is firstly carried out on the intermediate-frequency signals respectively, after narrowband interference is suppressed, space-time adaptive processing is carried out on a notch result, and broadband interference is suppressed. The method balances factors in multiple aspects such as anti-interference performance, system complexity, reliability and power consumption, adopts a processing mode of cascade connection of frequency domain narrow-band interference suppression and space-time self-adaptive notch processing, and has the capability of resisting narrow-band interference and multiple broadband interference at the same time. The signal after the interference cancellation is further up-converted to a radio frequency signal, and then the navigation signal can be processed according to a conventional method.
The power amplifier/combiner module has the power amplification function on RDSS-L transmitting signals, and sends the RDSS-L transmitting radio frequency signals to the anti-interference antenna to finish the power amplification and the transmission. A28V power supply on the power supply information board is directly fed into the power amplifier through the power supply module, and the opening of a transmitting channel at the transmitting moment is realized through transmitting enabling.
The baseband signal processing board processes three signals of RNSS-B1, RNSS-B3 and RDSS-S in a centralized manner. Various observed quantities are extracted after down-conversion, digitization and baseband signal processing of a radio frequency front end, tasks such as capturing, tracking, navigation message demodulation, time difference measurement and the like of received signals are completed, and PVT resolving is further completed. And simultaneously, performing spread spectrum processing on baseband data to be transmitted, performing up-conversion to an L waveband, and generating a radio frequency signal for output. The processing unit has functions of B3 and B1 frequency point RNSS positioning and the frequency point joint positioning, and can ensure reliable positioning of the command vehicle in moderate fluctuating road surface maneuvering. The unit has two modes of direct capture and guide capture of precise ranging codes of RNSS signals, navigation message conversion and decryption and 1PPS output function. The processing unit has the functions of positioning, communication and command based on RDSS. The method can realize the message communication function according to the BD-2RDSS communication protocol, support the position report, broadcast the communication information to subordinate users and support the user capacity of 200. The positioning result and the observed quantity result are output to the external interface of the equipment through the serial port in a standard protocol format, and the functional principle of the whole machine is shown in fig. 1.
Example 2
The utility model discloses a key lies in anti-interference module, explains anti-interference module's design in detail below:
design of anti-jamming modules
The working principle is as follows:
in an electronic countermeasure environment, a satellite navigation receiver has a large dynamic range of received signals, and is very easy to generate serious nonlinear distortion due to overlarge input signals in a radio frequency amplification link, so that in order to ensure that the receiver normally receives undistorted signals in the electronic countermeasure environment and achieve the purpose of effectively suppressing interference, an automatic gain control system with a large dynamic range is usually required to be designed to realize constant level or fluctuation in a small range. Generally, a feedback type analog AGC circuit is adopted in a traditional receiver, and although the gain control of the feedback type analog AGC circuit is accurate, the response time of the feedback type analog AGC circuit is slow, so that the feedback type analog AGC circuit is not suitable for a complex and fast-changing interference environment.
In order to ensure the fast convergence speed, stability and reliability of the gain control circuit, the digital technology has the advantages of high reliability, strong flexibility and the like, so that the scheme introduces the gain control into a digital domain. After the output of the reference channel is sampled, the demodulation processing is carried out in the FPGA, so that the noise reduction processing is conveniently carried out on the signal and a more flexible and effective control algorithm is adopted, so that the control signal of the 1-bit attenuator is accurately and timely output, and the signal level of the interference cancellation channel is controlled.
The power detection method is an effective detection method for detecting unknown signals, and is often adopted when the interference power is obviously higher than the noise power spectrum without any prior information of the interference signals, as shown in fig. 2. The power detection method makes interference judgment according to different received signal powers under the condition of no interference. The power detection algorithm does not limit the type of the interference signal, so that prior information of the interference signal does not need to be received, and a very ideal detection effect can be achieved through long-time accumulation.
The anti-interference module is composed of:
the anti-interference processing module of the anti-interference processing module S frequency point and the anti-interference processing module of the B1/B3 frequency point have the same composition and respectively comprise a 4-channel parallel receiving module, a baseband anti-interference processing module and an up-conversion channel module.
1) Down conversion channel unit
The down-conversion channel unit consists of an S/B3 radio frequency module and is used for down-converting radio frequency signals (including satellite signals and interference signals) received by the antenna.
2) Anti-interference processing unit
And finishing effective suppression of the narrowband and broadband suppression type interference of the S frequency point and the B3 frequency point based on a frequency domain narrowband interference suppression algorithm and a space-time self-adaptive processing algorithm to obtain an intermediate frequency signal after interference suppression.
3) Up-conversion channel unit
The up-conversion channel unit mainly completes the up-conversion function and converts the intermediate frequency signals after the interference cancellation back to the radio frequency.
Hardware design of an anti-interference module:
the anti-interference module hardware comprises digital signal acquisition, anti-interference processing, anti-interference filtering, an interface communication module and a power supply module. The anti-interference intermediate frequency unit receives 4 paths of RDSS S intermediate frequency analog signals and 4 paths of RNSS B3 intermediate frequency analog signals, and digital signal acquisition realizes analog signal digitization; the anti-interference processing realizes anti-interference operation according to the received digital signals; the anti-interference filtering module realizes the space-time domain filtering processing of the signals; the interface communication module realizes the output of the debugging information interface of the anti-interference processing unit, and the power supply module realizes the conversion and distribution of all power supplies on the board. The hardware circuit structure of the anti-interference processing unit is shown in fig. 4, and comprises a test port, a clock distribution unit, an ADC unit, an FPGA unit, a DSP unit, a power module, and the like.
Some important circuit designs are now described as follows:
a) hardware programmable processor (FPGA) cell design
A core processing device of the anti-interference module is a large-scale FGPA, and is mainly used for finishing functions of narrow-band interference suppression, space-time weight calculation, space-time broadband interference cancellation and the like. The method is characterized by large parallel operation amount, large consumed storage resources and multiplier resources.
1) Chip type selection
The special processor is used as the core of the baseband signal processing module and adopts Xilinx K7 series FPGA. The Xilinx FPGA series related hardware circuit design technology and the hardware description language development technology are relatively mature, and the development period can be effectively shortened by adopting the Xilinx FPGA series. In view of the requirement of low power consumption, the K7 series FPGA core voltage of Xilinx is 1V, and the power consumption is low. The factors such as resources and the like are considered comprehensively, XC7K325T-2FFG676I which is more suitable for baseband signal processing is selected as a special processor, and the main characteristics are as follows:
Figure DEST_PATH_GDA0002543754400000081
the core voltage is 1.0V, and the IO voltage supports 1.2V-2.5V;
Figure DEST_PATH_GDA0002543754400000082
advanced process of 12 layers of metal and 65nm CMOS;
Figure DEST_PATH_GDA0002543754400000091
50950Slices;
Figure DEST_PATH_GDA0002543754400000092
840DSP48E Slices;
Figure DEST_PATH_GDA0002543754400000093
16020Kbit integrated Block RAM resources;
Figure DEST_PATH_GDA0002543754400000094
configurable user I/O is 400;
Figure DEST_PATH_GDA0002543754400000095
advanced numerical control impedance (DCI) I/O termination techniques;
Figure DEST_PATH_GDA00025437544000000922
a differential input clock tree architecture;
Figure DEST_PATH_GDA0002543754400000096
flexible loading configuration options;
Figure DEST_PATH_GDA0002543754400000097
strong software support.
2) Configuration loading circuit design
The main characteristics of the Flash chip XCF128XFTG64C which can be repeatedly written and erased and is selected by Xilinx company are as follows:
Figure DEST_PATH_GDA0002543754400000098
1.8V nuclear voltage, 3.3V I/O voltage;
Figure DEST_PATH_GDA0002543754400000099
the online system can program PROM, the maximum value of the power supply current is 53 mA;
Figure DEST_PATH_GDA00025437544000000910
configuration mode: parallel (maximum 800Mbps) configuration;
Figure DEST_PATH_GDA00025437544000000911
a 128Mbit storage capacity;
Figure DEST_PATH_GDA00025437544000000912
64pinBGA packaging;
Figure DEST_PATH_GDA00025437544000000913
working temperature range: -40 ℃ to 85 ℃.
The circuit configuration connections are shown in fig. 5.
b) ADC circuit
The KGR satellite down-conversion signal has a high performance requirement on the ADC. The ADC scheme is given here for the KGR down-converted signal.
1) Chip type selection
The AD converter adopts an industrial grade chip AD9653 of ADI company. The functional block diagram of the chip is shown in fig. 6, and the main characteristics of the chip are as follows:
Figure DEST_PATH_GDA00025437544000000914
+1.8V power supply;
Figure DEST_PATH_GDA00025437544000000915
typical power consumption: 164mW per channel (125 MSPS);
Figure DEST_PATH_GDA00025437544000000916
four-channel ADC, 16bit resolution;
Figure DEST_PATH_GDA00025437544000000917
650MHz full power analog bandwidth;
Figure DEST_PATH_GDA00025437544000000918
typical 70MHz if sample signal to noise ratio: 76.5 dBFS;
Figure DEST_PATH_GDA00025437544000000919
differential input voltage range: 2Vpp (supporting 2.6 Vpp);
Figure DEST_PATH_GDA00025437544000000920
and (3) outputting: a binary complement;
Figure DEST_PATH_GDA00025437544000000921
working temperature range: minus 40 ℃ to plus 85 ℃.
2) ADC input analog signal conditioning circuit design
The ADC input analog signal conditioning circuit is shown in fig. 7.
In order to obtain better anti-noise performance of the amplifier, the differential input of an analog signal is realized by using a transformer. The VCM termination of the ADC implements an offset to the input analog signal at the midpoint of the transformer secondary. The transformer is ADT1-1WT of Mini-Circuits company, and the main characteristics of the chip are as follows:
Figure DEST_PATH_GDA0002543754400000101
the transformation ratio is 1: 1;
Figure DEST_PATH_GDA0002543754400000102
frequency range: 0.4 MHz-800 MHz;
Figure DEST_PATH_GDA0002543754400000103
amplitude imbalance: typical value 0.1 dB;
Figure DEST_PATH_GDA0002543754400000104
1dB bandwidth phase imbalance typical value: 1 deg;
Figure DEST_PATH_GDA0002543754400000105
1dB insertion loss: 1-400 MHz.
3) ADC sampling clock circuit design
The ADC input clock signal conditioning circuit is shown in fig. 8.
When the clock frequency is below 200M, the circuit in the figure is selected as the clock circuit scheme. The transformer is also ADT1-1WT here. The clocks of the two ADC chips are supplied from two outputs of the clock driver CY 2304. See the clock generation unit design for details.
c) DAC circuit
1) Chip type selection
The D/A conversion circuit is responsible for converting the digital intermediate frequency signals output by the FPGA after the interference cancellation into analog intermediate frequency signals. An industrial extremely-low-power-consumption device AD9707 is adopted, and the main technical indexes are as follows:
(1) resolution ratio: 14bit
(2) Maximum sampling rate: 175MSPS
(3) SFDR: 75dB @20MHz output
(4) Power consumption: less than or equal to 50mW (sampling rate is 62 MSPS)
(5) Power supply: analog 1.8V/digital 1.8-3.3V
(6) Working temperature range: minus 40 ℃ to plus 85 ℃.
2) DAC output signal conditioning circuit design
The DAC output signal conditioning circuit is shown in fig. 10.
d) Clock generation unit
1) Basic function and composition
And the system clock subunit provides differential clocks for the ADC, the DAC and the FPGA. Considering the requirement of synchronism among clocks of all devices, 62MHz and 124MHz clock signals provided by a radio frequency module are taken as references, and are respectively output to an ADC (analog to digital converter), a DAC (digital to analog converter) and an FPGA (field programmable gate array) through four and two clock signals of fan-outs of two clock driving chips respectively
2) System clock demand analysis
Figure DEST_PATH_GDA0002543754400000111
ADC
Figure DEST_PATH_GDA0002543754400000112
Sampling rate: 20MSPS to 80 MSPS;
Figure DEST_PATH_GDA0002543754400000113
support for LVPECL differential clock input;
Figure DEST_PATH_GDA0002543754400000114
the clock waveform is square wave or sine wave;
Figure DEST_PATH_GDA0002543754400000115
input clock amplitude: less than or equal to 3.6VPP
Figure DEST_PATH_GDA0002543754400000116
Duty cycle typical value: 50 percent.
Figure DEST_PATH_GDA0002543754400000117
DAC
Figure DEST_PATH_GDA0002543754400000118
Maximum clock rate: 175 MSPS;
Figure DEST_PATH_GDA0002543754400000119
input differential clock swing: 0.5VPP to 1.5 VPP;
Figure DEST_PATH_GDA00025437544000001110
duty ratio: 40 to 60 percent.
Figure DEST_PATH_GDA00025437544000001111
FPGA
Figure DEST_PATH_GDA00025437544000001112
The global clock input supports the LVPECL level standard.
3) Chip type selection
The clock driver selects CY2CP1504 of CYPRESS company, and the main characteristics of the chip are as follows:
Figure DEST_PATH_GDA00025437544000001113
2.5V power supply;
Figure DEST_PATH_GDA00025437544000001114
output frequency range: less than or equal to 250 MHz;
Figure DEST_PATH_GDA00025437544000001115
output skew maximum: 30 ps;
Figure DEST_PATH_GDA00025437544000001116
additional phase jitter maximum: 0.1ps (rms);
Figure DEST_PATH_GDA00025437544000001117
working temperature range: minus 40 ℃ to plus 80 ℃.
4) Chip power supply design
In order to ensure the performance of the chip and consider the power isolation with analog devices such as ADC and DAC, the power of the chip is obtained by +5V independent conversion.
The technical key point of the method is the design of a broadband interference suppression algorithm and anti-interference module hardware.
Space-time adaptive processing (STAP) is to perform interference suppression in a space-time two-dimensional space by performing space-time joint processing on data received by a plurality of array elements (spatial domain) and a plurality of time domains. The technology can effectively separate the target and the interference by utilizing the mutual independence of the interference and the useful signal space angle, thereby realizing the filtering. The space-time self-adaptive processing technology overcomes the defects of airspace filtering, and improves the freedom degree of the array surface on the premise of not increasing array elements. The key technology of the anti-interference spread spectrum receiver is the space-time adaptive filtering technology.
The space-time adaptive algorithm is divided into a constrained algorithm and an unconstrained algorithm according to whether the prior information of the satellite direction is known or not. The unconstrained space-time adaptive algorithm does not need any prior knowledge, can enable the gain zero point to the interference incoming direction, and can establish a nearly uniform hemispherical gain directional diagram when the external part has no interference; the constrained space-time adaptive algorithm requires the position information of known satellites, the position information of a satellite receiver and the attitude information of a receiving antenna, enables an antenna array to generate a plurality of narrow beams which respectively point to and track each target satellite, and simultaneously, the zero point of an antenna directional diagram still points to the external interference incoming direction.
The idea of the constrained space-time adaptive processing algorithm is to popularize one-dimensional spatial filtering into a two-dimensional domain of time and space to form a space-time two-dimensional processing structure. Brenan firstly proposes the idea of space-time two-dimensional processing, and derives a space-time two-dimensional processing self-adaptive processing structure called as an optimal processor according to a likelihood ratio detection theory under a model of adding a definite signal to a Gaussian clutter background.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are given by way of illustration only, and that various changes and modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims, specification and equivalents thereof.

Claims (2)

1. The anti-broadband interference Beidou vehicle-mounted all-in-one machine is characterized by comprising an anti-interference antenna array element, a receiving channel module, a power amplifier/combiner, an anti-interference module, a transmitting filter, a baseband signal processing board, a power supply information board and a power supply filter; wherein the content of the first and second substances,
the anti-interference antenna array element receives satellite navigation positioning radio frequency signals;
the anti-interference module adopts a processing mode of cascade connection of frequency domain narrow-band interference suppression and space-time adaptive notch processing to up-convert the signal after interference cancellation into a radio frequency signal, and then processes the radio frequency signal according to a conventional method;
the power amplifier/combiner module has a power amplification function for RDSS-L transmission signals, a transmission filter is arranged in the power amplifier/combiner module, and RDSS-L transmission radio frequency signals are sent to an anti-interference antenna to finish power amplification and transmission;
the baseband signal processing board performs centralized processing on the positioning radio frequency signal, extracts various observed quantities after down-conversion, digitization and baseband signal processing of a radio frequency front end, completes tasks of capturing, tracking, navigation message demodulation and time difference measurement of a received signal and further completes PVT resolving;
a power supply on the power supply information board is directly fed into the power amplifier through the power supply module, and a transmitting channel is opened while transmitting is realized through transmitting enabling;
the power supply filter converts an external power supply into a power supply on the power supply information board;
the satellite navigation positioning radio frequency signals received by the anti-interference antenna array elements are satellite navigation positioning radio frequency signals of RNSS-B1, RNSS-B3 and RDSS-S frequency points, and the two navigation radio frequency signals of RDSS-S and RNSS-B3 are received by four-array element receiving array antennas respectively.
2. The anti-interference module is used for the anti-broadband interference Beidou vehicle-mounted all-in-one machine and is characterized by comprising a digital signal acquisition unit, an anti-interference processing unit, an anti-interference filtering unit, an interface communication unit and a power supply unit; an anti-interference intermediate frequency unit is adopted to receive 4 paths of RDSS S intermediate frequency analog signals and 4 paths of RNSS B3 intermediate frequency analog signals, the digital signal acquisition unit is used for realizing analog signal digitization and sending the digitized signals to an anti-interference processing unit, and the anti-interference processing unit is used for realizing anti-interference operation according to the received digital signals; the anti-interference filtering unit realizes the space-time domain filtering processing of signals;
the interface communication unit realizes the output of a debugging information interface of the anti-interference processing unit, and the power supply unit realizes the conversion and distribution of all power supplies on the board;
the anti-interference processing unit adopts a processing mode of cascade connection of frequency domain narrow-band interference suppression and space-time adaptive notch processing, signals after interference cancellation are up-converted into radio frequency signals, and then the radio frequency signals are processed according to a conventional method.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110515098A (en) * 2019-03-11 2019-11-29 江苏无线电厂有限公司 Anti- broadband interference Beidou vehicle-mounted integral machine
CN112737661A (en) * 2020-12-16 2021-04-30 中电科航空电子有限公司 Interference coordination method and system for airborne Beidou equipment and other aircraft iridium equipment
CN113504550A (en) * 2021-08-17 2021-10-15 上海司南卫星导航技术股份有限公司 RDSS-compatible RNSS receiver, RNSS system, and computer-readable storage medium
CN113619650A (en) * 2021-08-09 2021-11-09 卡斯柯信号有限公司 Train positioning device and method based on satellite

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110515098A (en) * 2019-03-11 2019-11-29 江苏无线电厂有限公司 Anti- broadband interference Beidou vehicle-mounted integral machine
CN112737661A (en) * 2020-12-16 2021-04-30 中电科航空电子有限公司 Interference coordination method and system for airborne Beidou equipment and other aircraft iridium equipment
CN113619650A (en) * 2021-08-09 2021-11-09 卡斯柯信号有限公司 Train positioning device and method based on satellite
CN113504550A (en) * 2021-08-17 2021-10-15 上海司南卫星导航技术股份有限公司 RDSS-compatible RNSS receiver, RNSS system, and computer-readable storage medium

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