CN210666756U

CN210666756U - Port expanding device of chip

Info

Publication number: CN210666756U
Application number: CN201921258439.9U
Authority: CN
Inventors: 何仁勇
Original assignee: Beijing L&s Lancom Platform Tech Co ltd
Current assignee: Beijing L&s Lancom Platform Tech Co ltd
Priority date: 2019-08-05
Filing date: 2019-08-05
Publication date: 2020-06-02
Anticipated expiration: 2029-08-05

Abstract

The utility model discloses a port extension device of chip. Wherein, the method comprises the following steps: the system comprises a connector, a riser card and a field programmable gate array FPGA; the chip is connected with the adapter card through the connector, and the adapter card expands one path of data bus of the chip into a plurality of paths of upper-layer expansion buses and lower-layer buses; the chip receives the lower layer bus, and is expanded into a multi-path lower layer expansion bus through the adapter card; and the FPGA is used for expanding each upper layer expansion bus or lower layer expansion bus. The utility model provides a chip port quantity in the correlation technique not enough, can't satisfy the technical problem of user's demand.

Description

Port expanding device of chip

Technical Field

The utility model relates to a port extension field particularly, relates to a port extension device of chip.

Background

With the development of network technology, more and more applications in the field of network security require more network communication ports, and in the field of network security, an output bus of an existing chip is expanded into multiple network ports through an existing expansion circuit, the number of the expanded multiple network ports can support 64 network ports at most, and due to the development of network technology, the expansion circuit with 64 network ports cannot meet the requirement of increasing customer requirements, so that the expansion circuit in the related technology cannot meet the requirement of customers.

In view of the above problems, no effective solution has been proposed.

Disclosure of Invention

An embodiment of the utility model provides a port extension device of chip to it is not enough to solve the chip port quantity in the correlation technique at least, can't satisfy user demand's technical problem.

According to an aspect of the embodiments of the present invention, there is provided a port expansion device of a chip, including: the system comprises a connector, a riser card and a field programmable gate array FPGA; the chip is connected with the adapter card through the connector, and the adapter card expands one path of data bus of the chip into a plurality of paths of upper-layer expansion buses and lower-layer buses; the chip receives the lower layer bus and expands the lower layer bus into a multi-path lower layer expansion bus through the adapter card; and the FPGA is used for expanding the upper-layer expansion bus or the lower-layer expansion bus of each path.

Optionally, the FPGA expands each path of the upper layer expansion bus and the lower layer expansion bus into a plurality of ports.

Optionally, an independent power supply is arranged on the adapter card, and the adapter card is powered through a power supply port arranged on the adapter card.

Optionally, the chip is disposed on the adapter card, and is configured to receive information of the adapter card and send information to the adapter card.

Optionally, the chip receives a lower layer message sent by the adapter card, processes the lower layer message, and sends the lower layer message to the adapter card to expand the lower layer bus.

Optionally, the adapter card and the chip perform data transmission through a PCI-E bus.

Optionally, the FPGA expands each of the four upper layer expansion buses and the five lower layer expansion buses into 8 ports.

Optionally, the chip is an integrated chip.

Optionally, the data bus is a PCI-E bus.

Optionally, the upper layer expansion bus and the lower layer expansion bus are a PCI-EX8 bus or a PCI-EX4 bus.

In the embodiment of the utility model, the chip is connected with the adapter card through the connector, and the adapter card expands one path of data bus of the chip into a plurality of paths of upper layer expansion buses and lower layer buses; the chip receives the lower layer bus, and is expanded into a multi-path lower layer expansion bus through the adapter card; the FPGA is used for expanding each upper-layer expansion bus or lower-layer expansion bus, and achieves the purpose of expanding one-path data bus into multiple paths of data buses through the connector and the adapter card, so that the technical effect of increasing the number of port expansion is achieved, and the technical problems that the number of chip ports in the related technology is insufficient and the user requirements cannot be met are solved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without undue limitation to the invention. In the drawings:

fig. 1 is a schematic diagram of a port expansion device of a chip according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a hardware structure according to an embodiment of the present invention.

Detailed Description

In order to make the technical solution of the present invention better understood, the technical solution of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts shall belong to the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

In accordance with an embodiment of the present invention, there is provided an embodiment of a port expansion device for a chip, it should be noted that the steps shown in the flowchart of the drawings may be executed in a computer system such as a set of computer executable instructions, and that although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in an order different from that shown.

Fig. 1 is a schematic diagram of a port expansion device of a chip according to an embodiment of the present invention, as shown in fig. 1, the device includes: the connector 12, the riser card 14, and the FPGA16, which are described in more detail below.

Connector 12, riser card 14, field programmable gate array FPGA 16; the chip is connected with the adapter card through the connector, and the adapter card expands one path of data bus of the chip into a plurality of paths of upper-layer expansion buses and lower-layer buses; the chip receives the lower layer bus, and is expanded into a multi-path lower layer expansion bus through the adapter card; and the FPGA is used for expanding each upper layer expansion bus or lower layer expansion bus.

The chip may be a south bridge chip, and the south bridge chip may be an integrated south bridge PCH for intel. Because the multiple network ports in the related art are limited by resources under the intel architecture, the multiple network ports can be centralized at most to support 64 network ports at present, and the requirements of customers cannot be met. The embodiment provides a port expansion device of a south bridge. The connector is a high-speed connector, and the high-speed connector comprises two connected parts, wherein one part is arranged on the south bridge, and the other part is arranged on the adapter card.

The method specifically comprises the following steps: the south bridge is connected with the adapter card through the high-speed connector, and the adapter card expands one path of data bus of the south bridge into four paths of upper-layer expansion buses and one path of lower-layer bus; the bridge chip of the south bridge receives the lower layer bus and is expanded into a five-path lower layer expansion bus through the adapter card; and the FPGA is used for expanding each upper layer expansion bus or lower layer expansion bus. The data bus may be a PCIE bus.

The FPGA expands each expansion bus of the four upper-layer expansion buses and the four lower-layer expansion buses into 8 ports, and expands the last lower-layer expansion bus into 12 ports.

Optionally, the chip is disposed on the adapter card, and is configured to receive information of the adapter card and send the information to the adapter card.

In the five expanded buses of the lower bus, the last bus can be expanded into 8 network ports or 12 network ports. Typically 8 net ports, but 12 net ports can also be extended by FPGA applications.

Optionally, the chip is an integrated chip.

Optionally, the data bus is a PCI-E bus.

It should be noted that this embodiment also provides an alternative implementation, which is described in detail below.

This embodiment has solved and has received the few problem of resource restriction network extension net gape under the intel framework, the utility model discloses accessible collocation FPGA network extension application technique makes the network extension not be limited to the intel framework can reach 76 net gapes communication (photoelectricity mouth) as much. The embodiment is compatible with multi-port communication under all intel architectures at present, and simultaneously solves up to 76-port communication (photoelectric port). With the development of network technology, more and more applications in the field of network security require more network communication ports, and the existing multiple network ports in the field of network security are limited by resources under the intel architecture, can currently support 64 network ports at most in a centralized manner, and cannot meet the requirements of customers. The utility model aims at solving the problem of limitation under the intel framework, and also solving up to 76 net gapes communication (photoelectric ports) simultaneously, and can be widely applied to more customer demands.

The embodiment adopts intel architecture matched with FPGA network expansion application technology, and is not limited by resources; the network port under the intel framework is expanded by as much as 76 communication ports, flexible expansion is realized, and the requirements of different applications of clients in the field of network security are met.

Fig. 2 is a schematic diagram of a hardware structure according to an embodiment of the present invention, as shown in fig. 2, a PCH (integrated south bridge of Platform Controller Hub intel) is divided into 1 path of pcie x8 and is transferred out of the upper layer by 1 path of high-speed connector, and the upper layer and the lower layer of pcie x4 or pcie x8 are transferred out through a bridge chip; each path of the pcie network 8 or the pcie network 4 can extend 8 electrical ports or optical ports by using an FPGA application technology. The upper two layers can expand 32 network ports at most, the lower layer can expand 44 network ports, and the two layers can expand 76 network ports in total, and are compatible with a network security hardware platform with an expansion function under an intel architecture.

The key points of the embodiment are as follows: FPGA multiple extension application technology. The protection points of the present embodiment are: the utility model discloses a want the protection point to realize the communication switching of 76 net gapes between PCIEX8/PCIEX4 expansion card through the bridge chip mode this under the intel framework.

Compared with the prior art, the embodiment has the advantages that:

(1) the network communication of multiple network ports can reach 76 optical/electric network port network communication;

(2) the integration level is high, the self-adaptive PCIEX4 or PCIEX8 can be distributed through a high-integration bridging chip without the limitation of intel resources, the upper layer can be expanded 32 network ports (optical/electric), the lower layer can be expanded 44 network ports, and the total 76 network ports (optical/electric ports) are used for network communication;

(3) the PCIEX4 or PCIEX8 client can be matched and used in a random plugging mode through high-integration bridging chip distribution, and the subsequent investment cost can be saved in such a mode.

The above embodiment numbers of the present invention are only for description, and do not represent the advantages and disadvantages of the embodiments.

In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to the related descriptions of other embodiments.

In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. A port expansion device of a chip is characterized by comprising: the system comprises a connector, a riser card and a field programmable gate array FPGA;

the chip is connected with the adapter card through the connector, and the adapter card expands one path of data bus of the chip into a plurality of paths of upper-layer expansion buses and lower-layer buses;

the chip receives the lower layer bus and expands the lower layer bus into a multi-path lower layer expansion bus through the adapter card;

and the FPGA is used for expanding the upper-layer expansion bus or the lower-layer expansion bus of each path.

2. The apparatus of claim 1, wherein the FPGA expands each of the upper layer expansion bus and the lower layer expansion bus into a plurality of ports.

3. The apparatus of claim 2, wherein an independent power source is provided on the adapter card, and the adapter card is powered through a power supply port provided on the adapter card.

4. The apparatus of claim 3, wherein the chip is disposed on the adapter card and configured to receive information from the adapter card and send information to the adapter card.

5. The apparatus of claim 4, wherein the chip receives a lower layer message sent by the riser card, processes the lower layer message, and sends the lower layer message to the riser card to expand the lower layer bus.

6. The apparatus of claim 5, wherein the riser card and the chip communicate data via a PCI-E bus.

7. The apparatus of claim 1, wherein the FPGA expands each of four upper layer expansion buses and five lower layer expansion buses into 8 ports.

8. The apparatus of any one of claims 1 to 7, wherein the chip is an integrated chip.

9. The apparatus of claim 8, wherein the data bus is a PCI-E bus.

10. The apparatus of claim 9, wherein the upper layer expansion bus and the lower layer expansion bus are a PCI-EX8 bus or a PCI-EX4 bus.