CN210181514U

CN210181514U - High-speed acquisition board

Info

Publication number: CN210181514U
Application number: CN201921678897.8U
Authority: CN
Inventors: Hong Xiao; 肖红; Zhongming Jin; 晋中明
Original assignee: Sichuan Di Information Technology Co Ltd
Current assignee: Sichuan Di Information Technology Co Ltd
Priority date: 2019-10-09
Filing date: 2019-10-09
Publication date: 2020-03-24
Anticipated expiration: 2029-10-09

Abstract

The utility model discloses a high-speed acquisition board, which comprises a main control bottom board positioned at the lower layer and a digital top board positioned at the upper layer, wherein a chip layer is arranged between the main control bottom board and the digital top board, the chip layer comprises an FPGA chip and a plurality of ADC chips, a plurality of DAC chips, a DSP chip and a CPLD chip which are respectively connected with the FPGA chip, the utility model solves the problems of lower sampling requirement frequency, higher manufacturing cost of devices and slower signal processing speed of the acquisition board in the prior art, and provides a high-speed acquisition board which can prevent the damage of voltage and current surge to equipment when in use, can prevent a self-checking circuit and a real-time monitoring device from working state, can also quickly position the problem, can reduce fault maintenance time and the like, can detect temperature, can detect the service environment of the real-time monitoring device and can work condition and alarm circuit, and can improve the integral sampling frequency and signal processing speed, the reliability and the stability of the product are ensured.

Description

High-speed acquisition board

Technical Field

The utility model relates to a computer communication field, concretely relates to high-speed collection board.

Background

An ultra-high speed data acquisition system is a system that acquires data using an ultra-high sampling rate. The sampling rate and the resolution ratio are the most important technical indexes for evaluating the ultra-high speed data acquisition system. The structural design of the ultra-high speed data acquisition system mainly designs two modules of A/D conversion and data storage, and in addition, a subsequent digital signal processing part is also considered. The ultra-high speed data acquisition technology is also widely applied to a plurality of fields of radar, missile, communication, sonar, remote sensing, geological exploration, vibration engineering, nondestructive testing, intelligent instruments, voice processing, laser Doppler speed measurement, optical time domain reflection measurement, material spectroscopy and spectral measurement, biomedical engineering and the like.

The transient electric interference has short duration, but can cause overstress of the components and even damage the components, and needs to be protected. Transients in the desired signal (e.g., clock source) and incidental interference (e.g., switching power supply) that may be generated to perform a function or generate the desired signal are sources of transient interference. Transient interference can cause functional faults of circuit misoperation, and can also cause the failure of components in various modes, such as reverse breakdown of the components, burning of surge current and the like. For different types of components, the components are carefully designed according to the types of the overstress failure modes, different protective measures are adopted, analog-digital signal acquisition and processing are applied to the basic stage of the communication technology, and the accuracy of the communication result is directly influenced by the quality degree of the signal acquisition and processing. The existing data acquisition board has the problems of low sampling required frequency, high manufacturing cost of devices and low signal processing speed.

SUMMERY OF THE UTILITY MODEL

The utility model provides a collection board that prior art exists has the frequency of sampling requirement lower, the cost of manufacture of device is higher, signal processing's the slower problem of speed, a high-speed collection board is provided, the service environment of high-speed collection board is considered when it is used, the transient state of envisioning as far as possible, take corresponding measure, avoid transient interference from the design principle, for example, increase overcurrent overvoltage crowbar, prevent that the voltage current surge from causing the damage to equipment, the self-checking circuit, real time monitoring equipment's operating condition, also can fix a position the problem fast simultaneously, reduce fault repair time etc, temperature detection, real time detection equipment's service environment and working condition and warning circuit, when promoting whole sampling frequency and signal processing speed, guarantee the reliability and the stability of product.

The utility model discloses a following technical scheme realizes:

a high-speed acquisition board comprises a main control bottom board positioned on a lower layer and a digital top board positioned on an upper layer, wherein a chip layer is arranged between the main control bottom board and the digital top board and comprises an FPGA chip, a plurality of ADC chips, a plurality of DAC chips, a DSP chip and a CPLD chip, the ADC chips, the DAC chips, the DSP chip and the CPLD chip are respectively connected with the FPGA chip, the high-speed acquisition board further comprises a radio frequency connector connected with the ADC chip, a digital board connector used for connecting the FPGA chip and the digital top board and a bottom board connector used for connecting the FPGA chip and the main control bottom board, and the DSP chip is connected with the main control bottom board through the bottom board connector.

Furthermore, the FPGA chip is communicated with the DSP chip through 1 group of SRIO interfaces.

Furthermore, the high-speed acquisition board further comprises a reset key connected with the CPLD chip.

Furthermore, the DSP chip is respectively connected with the FPGA chip and the CPLD chip through an EMIF interface.

Further, the DSP chip comprises 4 pairs of Serial RapidIO interfaces, and 1 pair of RapidIO interfaces are connected with the high-speed interface of the FPGA chip and used for in-board communication; and 1 pair of RapidIO is connected with the main control board through a bottom board connector and used for inter-board communication.

Furthermore, the DSP chip comprises a plurality of UART interfaces.

Further, the high-speed acquisition board further comprises a temperature monitoring sensor, a current monitoring sensor and a voltage monitoring sensor which are respectively connected with the CPLD chip.

Compared with the prior art, the utility model, following advantage and beneficial effect have:

1. the utility model discloses consider the service environment of high-speed collection board, anticipate the transient state as far as possible, take corresponding measure, avoid transient disturbance from the design principle, for example increase and overflow overvoltage protection circuit, prevent that the voltage current surge from causing damage, self-checking circuit to equipment.

2. The utility model discloses real-time monitoring equipment's operating condition also can fix a position the problem fast simultaneously, reduces trouble repair time etc. and the temperature detects, real-time detection equipment's service environment and behavior and warning circuit.

3. The utility model discloses when promoting whole sampling frequency and signal processing speed, guarantee the reliability and the stability of product.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:

FIG. 1 is a schematic block diagram of the overall structure of the present invention;

FIG. 2 is a diagram of the overall interconnection architecture of the present invention;

FIG. 3 is a schematic view of a partial structure of the present invention;

fig. 4 is a topology structure diagram of the EMIF interface bus according to the present invention.

Detailed Description

To make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the following examples and drawings, and the exemplary embodiments and descriptions thereof of the present invention are only used for explaining the present invention, and are not intended as limitations of the present invention.

Examples

As shown in fig. 1 to 4, a high-speed acquisition board includes a main control bottom board located on a lower layer and a digital top board located on an upper layer, a chip layer is arranged between the main control bottom board and the digital top board, the chip layer includes an FPGA chip and a plurality of ADC chips, a plurality of DAC chips, a DSP chip, and a CPLD chip respectively connected to the FPGA chip, the CPLD chip is connected to the DSP chip, the high-speed acquisition board further includes a radio frequency connector connected to the ADC chip, a digital board connector for connecting the FPGA chip and the digital top board, and a bottom board connector for connecting the FPGA chip and the main control bottom board, and the DSP chip is connected to the main control bottom board through the bottom board connector. The FPGA chip is communicated with the DSP chip through 1 group of SRIO interfaces. The DSP chip is respectively connected with the FPGA chip and the CPLD chip through EMIF interfaces. The DSP chip comprises 4 pairs of Serial RapidIO interfaces, and 1 pair of RapidIO interfaces is connected with the high-speed interface of the FPGA chip and used for on-board communication; and 1 pair of RapidIO is connected with the main control board through a bottom board connector and used for inter-board communication. The DSP chip comprises a plurality of UART interfaces. The CPLD chip is connected with a temperature monitoring sensor, a current monitoring sensor and a voltage monitoring sensor respectively.

The utility model discloses in, contain 10 ADCs in the high-speed acquisition integrated circuit board, 10 DACs, 1 large capacity FPGA, 1 DSP and 1 CPLD. With FPGA as an interconnection center, the board and other board cards directly communicate with the outside mainly through a high-speed data interface and LVDS, and the inside of the board mainly communicates with a DSP through an SRIO, an EMIF bus and a UART; the FPGA chip adopts XC7VX690T-2FFG 1927I; the DSP chip adopts TMS320C6657 CZHA; the CPLD chip adopts XC2C512-7FTG 256I; in the application, 10 paths of AD are input into the AD converter with the AD input voltage of 1V, the conversion rate is not less than 500MHz, and 14-16 bits of AD conversion are input into the AD converter_ppAnd 2V_ppAdopt the binary channels, 500MHz sampling rate's ADC chip, specific model is: AD9680BCPZRL7-1000, to realize 10 ADC collection, needs 5 pieces. In order to implement asynchronous communication between C6657 and FPGA, the EMIF interface is further connected to a general IO of FPGA, and through the asynchronous communication, C6657 may send a control command, or receive status information of the chip, etc. And the EMIF interface is connected to the CPLD, and the CPLD is used for detecting the working state and upgrading online.

The utility model discloses consider the service environment of high-speed collection board, anticipate the transient state as far as possible, take corresponding measure, avoid transient disturbance from the design principle, for example increase and overflow overvoltage protection circuit, prevent that the voltage current surge from causing damage, self-checking circuit to equipment. The working state of the equipment is monitored in real time, meanwhile, the problems can be quickly positioned, the fault maintenance time and the like are reduced, the temperature is detected, the service environment and the working condition of the equipment are detected in real time, and an alarm circuit is arranged. The reliability and the stability of the product are ensured while the integral sampling frequency and the signal processing speed are improved.

The above-mentioned embodiments, further detailed description of the objects, technical solutions and advantages of the present invention, it should be understood that the above description is only the embodiments of the present invention, and is not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. The high-speed acquisition board is characterized by comprising a main control bottom board positioned on a lower layer and a digital top board positioned on an upper layer, wherein a chip layer is arranged between the main control bottom board and the digital top board and comprises an FPGA chip, a plurality of ADC chips, a plurality of DAC chips, a DSP chip and a CPLD chip, the ADC chips, the DAC chips, the DSP chip and the CPLD chip are respectively connected with the FPGA chip, the high-speed acquisition board further comprises a radio frequency connector connected with the ADC chip, a digital board connector used for connecting the FPGA chip and the digital top board and a bottom board connector used for connecting the FPGA chip and the main control bottom board, and the DSP chip is connected with the main control bottom board through the bottom board connector.

2. The board of claim 1, wherein the FPGA chip communicates with the DSP chip via 1 set of SRIO interfaces.

3. The high-speed acquisition board according to claim 1, further comprising a reset button connected to said CPLD chip.

4. The high-speed acquisition board according to claim 1, wherein the DSP chip is connected with the FPGA chip and the CPLD chip respectively through EMIF interfaces.

5. The high-speed acquisition board of claim 1, wherein the DSP chip comprises 4 pairs of SerialRapidIO interfaces, and 1 pair of RapidIO interfaces are connected to the high-speed interface of the FPGA chip for on-board communication; and 1 pair of RapidIO is connected with the main control board through a bottom board connector and used for inter-board communication.

6. The board of claim 1, wherein the DSP chip comprises a plurality of UART interfaces.

7. The high-speed acquisition board according to claim 1, further comprising a temperature monitoring sensor, a current monitoring sensor, and a voltage monitoring sensor respectively connected to the CPLD chip.